CN102780611A - Packet switching circuit and packet switching method - Google Patents
Packet switching circuit and packet switching method Download PDFInfo
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- CN102780611A CN102780611A CN2012101839715A CN201210183971A CN102780611A CN 102780611 A CN102780611 A CN 102780611A CN 2012101839715 A CN2012101839715 A CN 2012101839715A CN 201210183971 A CN201210183971 A CN 201210183971A CN 102780611 A CN102780611 A CN 102780611A
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Abstract
The invention provides a packet switching circuit and a packet switching method. Each input port has input memory, and each output port has output memory; a first polling unit is used for polling the input memory of the input port; a routing computation unit is used for carrying out routing computation on at least one polled data packet stored in the input memory so as to determine the output port corresponding to the data packet; a shared cache is used for storing the data packet determining the output port through the routing computation unit and storing the memory address of the data packet in the shared cache in corresponding control caches according to the output port; and a second polling unit is used for polling a plurality of control caches, obtaining the memory address of at least one data packet in the shared cache in the polled control caches, and storing the data packet obtained in the shared cache in the corresponding output cache of the output port according to the memory address.
Description
Technical field
The present invention relates to the communication technology, relate in particular to a kind of packet switching circuits and package switching method.
Background technology
Packet switch is also referred to as packet switching, and it is that the data that the user transmits are divided into certain length, and each part is called a grouping.Add a packets headers in the front of each grouping, where mail to the location in order to indicate this grouping, then by switch according to the information in the packets headers of each grouping, forward the packet to destination address.In the prior art, packet switching circuits is widely used in fixed network and the wireless communication system.At global mobile communication (Global System For Mobile Communication; Abbreviate as: GSM) and UMTS (Universal Mobile Telecommunications System; Abbreviate as: UMTS) etc. in the radio communication standard; The transmission of packet is normally transmitted with the mode of fixing time slot burst, has a large amount of multicasts or broadcast data packet simultaneously, and this just must cause application scenarios that packet switching circuits is directed against wireless base system needs specific aim to some extent on the chip design structure; Should solve the impact of the big data on flows bag of instantaneous burst, consider the cost problem of buffer memory again.
The packet system that provides in the prior art is generally: storage gets into the packet of packet switching circuits in the buffer memory of each input port of packet switching circuits; Use polling dispatching algorithm poll to handle the packet of storing in the buffer memory of each input port, be distributed to the buffer memory of each output port after calculating through route.
For the packet system of this employing poll way of escape by distribution; Implementation method is simple; Resource overhead is little; But, the situation of the big data on flows bag of instantaneous burst that exists for the wireless base station, this packet system need can guarantee the bag packet loss because buffer memory overflows of packet for each output port provides bigger buffer memory.But, for each output port of packet switching circuits provides bigger output buffers can cause the waste of storage resources and the raising of packet switching circuits cost.
Summary of the invention
The present invention provides a kind of waste problem that is used to solve storage resources; And the packet switching circuits that effectively reduces cost; Comprise: a plurality of input ports, a plurality of output port, first poll units, route computing unit, shared buffer memory, control the buffer memory and second poll units one to one with output port; Wherein, each input port all has input-buffer, and each output port all has output buffers;
Said input port is used for receiving packet and said packet is stored in self input-buffer;
Said first poll units is used for the input-buffer of said input port is carried out poll;
Said route computing unit is used for that at least one packet that the input-buffer that said first poll units is polled to is stored is carried out route and calculates, and confirms the output port that said packet is corresponding;
Said shared buffer memory is used to store the packet of confirming output port through said route computing unit, and according to output port the memory address of packet in shared buffer memory is deposited in the control corresponding buffer memory;
Said second poll units; Be used for a plurality of control buffer memorys are carried out poll; In the control buffer memory that is polled to, obtain the memory address of at least one packet in shared buffer memory; And in shared buffer memory, obtain packet, and deposit in the output buffers of corresponding output port according to said memory address;
Said output port is used to read the output buffers of self and sends packet.
Package switching method based on above-mentioned packet switching circuits provided by the invention comprises:
At least one packet of storing in the input-buffer that is polled to is carried out route calculate the output port of specified data bag;
Deposit the packet of confirming output port in shared buffer memory, the memory address of packet in shared buffer memory deposited in the control corresponding buffer memory according to output port;
In the control buffer memory that is polled to, obtain the memory address of at least one packet in shared buffer memory, and in shared buffer memory, obtain packet, and deposit in the corresponding output buffers according to said memory address.
Technique effect of the present invention is: the big data on flows bag that will happen suddenly all is stored in the shared buffer memory; The memory address of storage packet in shared buffer memory in the control buffer memory of each output port correspondence; Through reading the memory address in the control buffer memory; In shared buffer memory, obtain corresponding packet, the output buffers of each output port only need use less memory space, can effectively reduce the storage resources waste of each output buffers.
Description of drawings
The structural representation of the packet switching circuits that Fig. 1 provides for the embodiment of the invention one;
The flow chart of the package switching method of the packet switching circuits that provides based on the foregoing description that Fig. 2 provides for the embodiment of the invention two;
The flow chart of the package switching method of the packet switching circuits that provides based on the foregoing description that Fig. 3 provides for the embodiment of the invention three;
The flow chart of the package switching method of the packet switching circuits that provides based on the foregoing description that Fig. 4 provides for the embodiment of the invention four.
Embodiment
The structural representation of the packet switching circuits that Fig. 1 provides for the embodiment of the invention one; As shown in Figure 1, this packet switching circuits comprises: a plurality of input ports, a plurality of output port, first poll units, route computing unit, shared buffer memory, control the buffer memory and second poll units one to one with output port.Wherein, each input port all has input-buffer, and each output port all has output buffers.Concrete, input port is used for: receive packet and the packet that receives is stored in self input-buffer; First poll units is used for: the input-buffer to input port carries out poll; Route computing unit is used for: at least one packet that the input-buffer that first poll units is polled to is stored carries out route and calculates, with the corresponding output port of specified data bag; Shared buffer memory is used for: storage process route computing unit is confirmed the packet of output port, and according to output port the memory address of packet in shared buffer memory is deposited in the control corresponding buffer memory; Second poll units is used for: a plurality of control buffer memorys are carried out poll; In the control buffer memory that is polled to, obtain the memory address of at least one packet in shared buffer memory; And in shared buffer memory, obtain packet, and deposit in the output buffers of corresponding output port according to memory address; Output port is used for: read the output buffers of self and send packet.
Wherein, Shared buffer memory is used to store the packet from whole input-buffers, and no matter this packet is to prepare to mail to which output port, all need deposit in the shared buffer memory; Therefore; Packet can sequentially write shared buffer memory, and the memory address of packet in shared buffer memory just can increase progressively according to the priority that packet arrives shared buffer memory in proper order successively so, and memory address can also recycle.Help effective utilization of the memory space of shared buffer memory so more, the storage that is compared to other modes has better system robustness.Simultaneously, do not need special pointer circuit that memory address is safeguarded, practiced thrift system cost.The size of this shared buffer memory can design according to the practical application scene of wireless base station; The entire packet that will can store the big flow of instantaneous burst; Generally speaking; The total amount of the entire packet of the big flow of instantaneous burst can know in advance that so, the capacity of shared buffer memory only need be provided with according to the packet total amount of knowing in advance and get final product.But, can be with the capacity setting of the buffer memory that should share more than or equal to the capacity sum that all is input-buffer for this shared buffer memory is set more expediently.The quantity of control buffer memory is identical with number of output ports, also be each output port all to a control buffer memory should be arranged, each controls the content of storing in buffer memory is the address information of packet in shared buffer memory that is ready for sending its corresponding output end mouth.First poll units and second poll units can the user mode machine or counter etc. realize its function.
The packet switching circuits that the embodiment of the invention provides; All be stored in the big data on flows bag of burst in the shared buffer memory; The memory address of storage packet in shared buffer memory in the control buffer memory of each output port correspondence through reading the memory address in the control buffer memory, obtains corresponding packet in shared buffer memory; The output buffers of each output port only need use less memory space, can effectively reduce the storage resources waste of each output buffers.
On the basis of above-mentioned execution mode, second poll units of this packet switching circuits can also be used for: whether the output buffers that detects the pairing output port of control buffer memory be polled to back-pressure; If back-pressure, the next control of poll buffer memory.
Need to prove; Back-pressure be meant if when the corresponding output buffers of the output port of pre-treatment full; There are not enough memory spaces to continue bag deposit; Then can such feedback information be given the previous stage unit (also being second poll units) of self, require the previous stage unit not give out a contract for a project to oneself again.
If some output buffers back-pressures; Then do not read the address information in its corresponding control buffer memory; But the next control of poll buffer memory; Handle next output buffers, can not exist, also can not change in proper order for giving out a contract for a project of the output port that stops to give out a contract for a project owing to back-pressure simultaneously owing to some output buffers back-pressures time-out that causes giving out a contract for a project.Can effectively reduce the packet loss of packet in this way.
Whether on the basis of above-mentioned execution mode, the shared buffer memory of this packet switching circuits can also be used for: judge between the packet of shared buffer memory to be deposited and the packet that deposits shared buffer memory in identical; If identical, abandon the packet of shared buffer memory to be deposited; If inequality, deposit the packet of shared buffer memory to be deposited in shared buffer memory and get final product.
The packet switching circuits that the foregoing description provides; Packet for multicast or broadcasting; After calculating through route, the storage shared buffer memory be merely a packet, when effectively having avoided the big data on flows bag of instantaneous burst for the congestion situation of packet switching circuits output buffers.
The flow chart of the package switching method of the packet switching circuits that provides based on the foregoing description that Fig. 2 provides for the embodiment of the invention two, as shown in Figure 2, this method comprises:
Concrete, can store packet according to the sequencing that packet arrives shared buffer memory, the memory address of packet is the address successively, and recycles.
On the basis of above-mentioned execution mode, the flow chart of the package switching method of the packet switching circuits that provides based on the foregoing description that Fig. 3 provides for the embodiment of the invention three, as shown in Figure 3, before step 205, this method can also comprise:
If back-pressure, the next control of poll buffer memory;
If back-pressure not, execution in step 205.
On the basis of above-mentioned execution mode, the flow chart of the package switching method of the packet switching circuits that provides based on the foregoing description that Fig. 4 provides for the embodiment of the invention four, as shown in Figure 4, before step 203, this method can also comprise:
Step 202, judge between the packet of shared buffer memory to be deposited and the packet that deposits shared buffer memory in whether identical;
If identical, abandon the packet of shared buffer memory to be deposited;
If inequality, execution in step 203.
All be stored in the big data on flows bag of burst in the shared buffer memory; The memory address of storage packet in shared buffer memory in the control buffer memory of each output port correspondence; Through reading the memory address in the control buffer memory; In shared buffer memory, obtain corresponding packet, the output buffers of each output port only need use less memory space, can effectively reduce the storage resources waste of each output buffers.
What should explain at last is: above each embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although the present invention has been carried out detailed explanation with reference to aforementioned each embodiment; Those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, perhaps to wherein part or all technical characteristic are equal to replacement; And these are revised or replacement, do not make the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.
Claims (10)
1. packet switching circuits; It is characterized in that; Comprise: a plurality of input ports, a plurality of output port, first poll units, route computing unit, shared buffer memory, control the buffer memory and second poll units one to one with output port; Wherein, each input port all has input-buffer, and each output port all has output buffers;
Said input port is used for receiving packet and said packet is stored in self input-buffer;
Said first poll units is used for the input-buffer of said input port is carried out poll;
Said route computing unit is used for that at least one packet that the input-buffer that said first poll units is polled to is stored is carried out route and calculates, and confirms the output port that said packet is corresponding;
Said shared buffer memory is used to store the packet of confirming output port through said route computing unit, and according to output port the memory address of packet in shared buffer memory is deposited in the control corresponding buffer memory;
Said second poll units; Be used for a plurality of control buffer memorys are carried out poll; In the control buffer memory that is polled to, obtain the memory address of at least one packet in shared buffer memory; And in shared buffer memory, obtain packet, and deposit in the output buffers of corresponding output port according to said memory address;
Said output port is used to read the output buffers of self and sends packet.
2. packet switching circuits according to claim 1 is characterized in that, said second poll units also is used for: whether the output buffers that detects the pairing output port of control buffer memory be polled to back-pressure; If back-pressure, the next control of poll buffer memory.
3. whether packet switching circuits according to claim 1 and 2 is characterized in that, said shared buffer memory also is used for: judge between the packet of shared buffer memory to be deposited and the packet that deposits shared buffer memory in identical;
If identical, abandon the packet of said shared buffer memory to be deposited;
If different, deposit the packet of said shared buffer memory to be deposited in shared buffer memory.
4. according to each described packet switching circuits in the claim 1 to 3, it is characterized in that, the memory address of packet in the said shared buffer memory, the sequencing that arrives shared buffer memory according to packet increases progressively successively, and recycles.
5. according to each described packet switching circuits in the claim 1 to 4, it is characterized in that the capacity of said shared buffer memory is more than or equal to the capacity sum of whole input-buffers.
6. the package switching method based on each described packet switching circuits in the claim 1 to 5 is characterized in that, comprising:
At least one packet of storing in the input-buffer that is polled to is carried out route calculate the output port of specified data bag;
Deposit the packet of confirming output port in shared buffer memory, the memory address of packet in shared buffer memory deposited in the control corresponding buffer memory according to output port;
In the control buffer memory that is polled to, obtain the memory address of at least one packet in shared buffer memory, and in shared buffer memory, obtain packet, and deposit in the corresponding output buffers according to said memory address.
7. method according to claim 6 is characterized in that, said in the control buffer memory that is polled to, the acquisition before the memory address of at least one packet in shared buffer memory, and said method also comprises:
Whether the output buffers of the pairing output port of control buffer memory that detection is polled to back-pressure;
If back-pressure, the next control of poll buffer memory.
8. according to claim 6 or 7 described methods, it is characterized in that saidly will confirm that the packet of output port deposits in before the shared buffer memory, said method also comprises:
Whether identically judge between the packet of shared buffer memory to be deposited and the packet that deposits shared buffer memory in;
If identical, abandon the packet of said shared buffer memory to be deposited;
If different, carry out and saidly will confirm that the packet of output port deposits the step of shared buffer memory in.
9. according to each described method in the claim 6 to 8, it is characterized in that the said packet that will confirm output port deposits shared buffer memory in and specifically comprises:
The sequencing that arrives shared buffer memory according to packet is stored said packet, and the memory address of packet increases progressively successively, and recycles.
10. according to each described method in the claim 6 to 9, it is characterized in that the capacity of said shared buffer memory is more than or equal to the capacity sum of whole input-buffers.
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| CN2012101839715A CN102780611A (en) | 2012-06-06 | 2012-06-06 | Packet switching circuit and packet switching method |
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| CN2012101839715A CN102780611A (en) | 2012-06-06 | 2012-06-06 | Packet switching circuit and packet switching method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113098798A (en) * | 2021-04-01 | 2021-07-09 | 烽火通信科技股份有限公司 | Method for configuring shared table resource pool, packet switching method, chip and circuit |
| US11599649B2 (en) * | 2020-06-29 | 2023-03-07 | Rockwell Automation Technologies, Inc. | Method and apparatus for managing transmission of secure data packets |
| US11606346B2 (en) | 2020-06-29 | 2023-03-14 | Rockwell Automation Technologies, Inc. | Method and apparatus for managing reception of secure data packets |
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| US20060291458A1 (en) * | 1999-03-05 | 2006-12-28 | Broadcom Corporation | Starvation free flow control in a shared memory switching device |
| CN101729407A (en) * | 2009-12-04 | 2010-06-09 | 西安电子科技大学 | Low delay jitter exchanging method and equipment based on unicast and multicast differentiated treatment |
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| US20060291458A1 (en) * | 1999-03-05 | 2006-12-28 | Broadcom Corporation | Starvation free flow control in a shared memory switching device |
| CN1848803A (en) * | 2005-07-27 | 2006-10-18 | 华为技术有限公司 | Down queue fast back pressure transmitting based on three-stage exchange network |
| CN101729407A (en) * | 2009-12-04 | 2010-06-09 | 西安电子科技大学 | Low delay jitter exchanging method and equipment based on unicast and multicast differentiated treatment |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11599649B2 (en) * | 2020-06-29 | 2023-03-07 | Rockwell Automation Technologies, Inc. | Method and apparatus for managing transmission of secure data packets |
| US11606346B2 (en) | 2020-06-29 | 2023-03-14 | Rockwell Automation Technologies, Inc. | Method and apparatus for managing reception of secure data packets |
| CN113098798A (en) * | 2021-04-01 | 2021-07-09 | 烽火通信科技股份有限公司 | Method for configuring shared table resource pool, packet switching method, chip and circuit |
| CN113098798B (en) * | 2021-04-01 | 2022-06-21 | 烽火通信科技股份有限公司 | Method for configuring shared table resource pool, packet switching method, chip and circuit |
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Application publication date: 20121114 |