CN102804409A - Method for producing locally structured semiconductor layers - Google Patents

Method for producing locally structured semiconductor layers Download PDF

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Publication number
CN102804409A
CN102804409A CN2010800579372A CN201080057937A CN102804409A CN 102804409 A CN102804409 A CN 102804409A CN 2010800579372 A CN2010800579372 A CN 2010800579372A CN 201080057937 A CN201080057937 A CN 201080057937A CN 102804409 A CN102804409 A CN 102804409A
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substrate
described method
semiconductor
aforementioned
layer
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伊夫林·施米希
法比安·基弗
斯蒂芬·雷伯
斯蒂芬·林德库格尔
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Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Albert Ludwigs Universitaet Freiburg
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Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Albert Ludwigs Universitaet Freiburg
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Abstract

The invention relates to a method for producing a locally structured semiconductor layer on a substrate, a reactive gas being supplied to the surface of the substrate while the substrate is etched or doped or a semiconductor substance is deposited onto the substrate. The term "structured" does not only refer to purely mechanical or topographical structures but also to locally doped regions.

Description

Be used to generate the method for the semiconductor layer of partial structurtesization
Technical field
The present invention relates to a kind of method that is used on substrate, generating the semiconductor layer of partial structurtesization, wherein, the surface of this substrate places under the active gas.Carry out etching, doping or deposition thus to the semiconductor substance on the substrate or in the substrate." structuring " not only represented simple mechanical or topological structure, but also the local doping of expression etc.
Background technology
As standard, the emitter that is used for Si (silicon) solar cell is made into the plane through diffusion in industry.Yet, think at this:, need high surface doping, thereby the surface has high recombination rate for low contact resistance.
In high performance solar batteries, use optionally (being surface structuration) emitter, to guarantee good front side passivation and low auger recombination (low surface doping) and good cross conduction property and low contact resistance (high surface doping).For example, at this, implement smooth low-doped diffusion in the follow-up zone that is arranged in below the contact, it has follow-up dark highly doped diffusion.Therefore, need two diffusing steps and masking process, this masking process is on the surface between the protection contact between second diffusion period.
Alternatively, can use laser means, wherein, specifically mixed in the surface below the contact.Yet, for this purpose, except diffusion furnace, also need other laser element.Can come to recover selectively the emitter region by mask method as an alternative.
Summary of the invention
The objective of the invention is to use the emitter deposition or combine to replace being used to generate the complicated diffusion technology (and/or laser technology or reverse etching technics) of selective emitter with the reverse etching of emitter.
This purpose realizes through the method with Patent right requirement 1 said characteristic.Through Patent right requirement 15, pointed out to use the possibility of said method, and Patent right requirement 16 has been described by solar cell, this solar cell comprises the emitter layer that generates through according to the method for the invention.At this, other dependent claims is represented favourable development.
According to the present invention; Therefore a kind of method that is used on substrate, generating the semiconductor layer of partial structurtesization is provided; Wherein, the surface of this substrate at least once suffers the effect of gas by the zone, deposition, doping and/or the etching in the zone of the partial structurtes semiconductor layer that this gas is used for generating.
Method in this proposition provides the attractive alternative to the diffusion selective emitter, has the attendant advantages that describes in further detail after a while.
Essence of the present invention is: with depositional fabric layer and/or array (in-line) structuring through utilizing etching gas to carry out, generate selective emitter through shadow mask.For wafer or crystalline silicon material and thin-film solar cells, but extension emitter deposition advantageous particularly, thus can in a processing step, very generate selective emitter apace.
Because deposition rate can and be optimized emitter thickness between 1 μ m and 5 μ m greater than 1 μ m/min, therefore can in a few minutes, generate the selective epitaxial emitter.Obtain following advantage thus: can be deposited on favourable especially thick highly doped zone, below, contact (, introduce the dark doping of 2 μ m and continue nearly 1-2 hour) apace for diffusion.According to gas componant, can generate emitter quickly with＞50 the factor (multiple) according to the method for the invention.
In addition, can dispose the emitter profile by any way.Therefore, that can avoid not expecting in the emitter is compound, and can increase the electric current of solar cell.But selective emitter deposition original position is carried out completely.For silicon film solar batteries, additional deposition BSF and substrate in position in advance.
In the preferred embodiment of said method, propose to corrode by the zone, make through at least one shadow mask (its recess is corresponding with the structure of partial structurtes layer to be generated) and/or pass through at least one nozzle especially that the surface of substrate receives the air-flow effect.
Through skillfully choosing mask and deposition parameter, therefore can deposit the emitter that is suitable for follow-up metallization design with different layers resistance.Mask has material impact to follow-up metallized erosion.Thus, when being printed on grid on the selective emitting electrode structure, need adjustment.Can have different floor heights through mask regions coated and uncoated zone.Because this species diversity is so adjust this grid more easily when being printed on grid on the selective emitting electrode structure.For example, therefore can use visual method adjustment.
In the embodiment of the said method of using nozzle, preferably, use nozzle with integrated gas activation possibility (for example to gas heated and/or plasma-activated possibility).
In another advantageous embodiment of said method, propose: the interval on said at least one shadow mask and/or said at least one said surface of nozzle distance is between 0.1mm and 10mm, preferably between 0.5mm and 5mm, particularly preferably between 1mm and 2mm.
Mask preferably includes and is difficult for depositing above that (for example applying SiO 2, Si 3N 4, SiC and/or Al 2O 3) and the material that during the reverse etching of chamber of the reactor, do not weather.For the mask obstruction that can not become, the conventional reverse etching between the depositional stage of selective structure is favourable.
According to the present invention, therefore can generate the semiconductor layer of partial structurtesization, the zone of carrying out semiconductor deposition can change very on a large scale.Yet preferably, the surface of substrate is with the width between 0.1mm and the 20mm, preferably at the width between 0.2mm and the 2mm, particularly preferably the width between 0.3mm and 1mm receives the gas effect, thereby can generate corresponding wide semiconductor structure.
At this, operable favorable activity gas is selected from and comprises following group according to the present invention: hydrogen chloride, hydrogen, chlorosilane, phosphine, hydride, boron chloride, trimethyl-phosphine and/or vapor-phase fluoride (CF particularly 4Or SF 6) and/or its mixture.
At this, carry out said method preferred temperature (be underlayer temperature or active gases temperature, and possibly under corresponding temperature, rub up substrate and active gases the two) between 200 and 2000 ℃, preferably between 500 and 1500 ℃.The special preferred embodiment of said method proposes: this temperature is between 1000 ℃ and 1200 ℃ or between 500 ℃ and 999 ℃.Can propose similarly: implement said method with temperature gradient, promptly for example, the gas that substrate surface receives is in the certain limit adjusted.Therefore, can be implemented in the more or less semiconductor of deposition on the corresponding substrate.
Therefore there is the option of realizing following technology:
1. for example at approximate 1100 ℃ of deposition selective epitaxial layers;
2. for example at the deposition of the temperature below 1000 ℃ selectivity microcrystalline coating;
The cooling period of wafer the temperature between 1100 and 700 ℃ be diffused into selective structure;
4. the reverse etching of selective structure before or after deposition step.
Specifically, the CVD coating unit is suitable for implementing according to the method for the invention.
In addition, advantageously, if said method is implemented as continuation method, then this substrate moves with respect to the zone of corroding with etching gas in one dimension, two dimension or three-dimensional.
A large amount of possible substrates is fit to said method; At this; Favourable substrate is selected from Semiconductor substrate, particularly Si-, GaAs-, Ge-, SiC Semiconductor substrate and/or its combination, has the combination of the carrier substrate of coated semiconductor, the semiconductor layer that is deposited on the partial structurtesization on the coated semiconductor, metal, glass and/or pottery and above-mentioned substrate.For above-mentioned coated semiconductor, comprise that particularly for example the coating of Si, CdTe, CdS, CdSe, CuIn (Ga) Se and/or CuIn (Ga) S is possible.Can be molybdenum and/or be applied to the molybdenum on the glass substrate for example by structurized preferable alloy.For glass or pottery, for example SiC, ZrSiO 4, Si 3N 4Or be possible based on glass or the pottery of sintering Si, yet, utilize and can carry out the structuring of graphite or carbon equally according to the method for the invention.Certainly, solar cell also can be used as substrate.
For the electrical characteristics of the coated semiconductor that improves substrate or deposition,, then be especially favourable if before implementing said method and/or implement the plane doping of semiconductor substrate surface afterwards.
In order to improve structuring, can implement the reverse etching of part at least in addition, as subsequent method step to the semiconductor layer of partial structurtesization.
In addition, advantageously, continuously several times are implemented said method, thereby deposited semiconductor material repeatedly perhaps can be carried out particular structured to other zone of substrate with semi-conducting material, thereby also can be generated the complex texture of the structure of institute's deposited semiconductor.
According to the present invention; Further said method (particularly in the manufacturing of solar cell) is used in indication, be used for epitaxial semiconductor be deposited upon Semiconductor substrate, be used for crystallite semiconductor be deposited upon Semiconductor substrate, be used for the doping semiconductor layer of Semiconductor substrate partial structurtesization inside diffusion, be used for semiconductor layer structuring, the structuring that be used for metal level connected in series to be used for to be used for connected in series and/or to be used for the localized metallic deposition.
According to the present invention, comprise solar cell similarly, this solar cell has can be according to the emitter layer of the inventive method manufacturing.
Subsequently, through the mode of example, each preferred embodiment of the present invention is shown, but is not that the present invention is limited to special parameter.Specifically, relevant with the structuring of emitter and emitter example is interpreted as: " normally " original position structuring of layer that deposited or to be deposited also falls in the present invention.
Embodiment
Example 1
The deposition of selective epitaxial layer
By mask, can deposit the epitaxial loayer (see figure 1) that at high temperature generates selectively.At this, wafer must closely be advanced along mask, with " defiling " of avoiding depositing.Therefore, can in high-throughput atmospheric pressure CVD unit, implement successive sedimentation technology.At this, substrate is advanced through different settling chambers.For the selective emitter deposition, the settling chamber of the separation with high-dopant concentration can be provided.
Importantly, implement conventional reverse etch step, the obstruction thereby mask can not become, thereby the surface that is coated can not diminish or complete obiteration.This technology make can deposition be very thick very apace emitter (deposition rate be 1-4 μ m/min (minute)).
Example 2
The deposition of selectivity crystallite or microcrystalline coating
The technology of describing in the example 1 also can more carried out under the low temperature.At this, the deposition crystallite-or polycrystal layer.For example, can use corresponding layer for the thin-film solar cells on the foreign substrate (high temp glass or pottery for example insulate).This always needs structurized element, for example is used for connected in seriesly, and these structurized elements generate according to laser whole surface deposition after usually, still utilize method described herein, even can between depositional stage, generate.
Example 3
The inside diffusion of selective structure during cooling
Can carry out dopant and mix, rather than deposit highly doped zone through mask.Under high-temperature, the hydrogen phosphide diffusion can very in depth penetrate into silicon fast.In fact the cooling that in being no more than 750 ℃ the reactor atmosphere of temperature, utilizes 120ppm hydrogen phosphide to carry out is enough to approximate 10 18Individual atom/cm 3The Si laminar surface on doping content increase by an one magnitude.
Example 4
Etching after the emitter deposition
Purge/contact with etching gas through the part, 2 rank type emitter layers of homogeneity are removed and structuring by part.For example, from the purpose of contact, the emitter region of etching does not keep highly doped.Through making etching gas overheated,, therefore can improve selectivity on (" cold ") layer because dispensing gas cools off fast and loses its activity.
Example 5
Structuring etching after the emitter deposition
If choose the correct temperature of etching gas, then can carry out veining to the zone of reverse etching simultaneously.At this, advantage is that the height in the reverse etch areas absorbs and the medium and small surface (for example, the solar cell contact site on this zone has reduced compound) of non-etch areas, also has the admixture of gas by plasma generation.
In all configurations, the cooling wafer can be favourable in hydrogen/hydrogen phosphide atmosphere.Prevent that thus phosphorus is to outdiffusion after emitter epitaxy.By means of phosphorous environment, do not produce the concentration gradient on the gas phase direction, this concentration gradient will cause to outdiffusion.Therefore, the phosphorus for silicon layer inside more preferably is retained in the solid body.Because always need be with wafer cooling and the atmosphere that only need define, therefore said technology can be very well, almost industrially be integrated in the continuous processing.
Operation stage
At first, the emission polar body that mixes with planar fashion deposition appropriateness.Subsequently, through mask, deposit or spread highly doped zone.Similarly, can deposit the layer of second order type, the more highly doped layer of then local removal.
Fig. 1 to Fig. 3 illustrates in greater detail the sequence of layer or the semiconductor device that can generate through this method.
Fig. 1 has described the possibility for the integrated form connection of institute's depositing metal layers.At first, here, sedimentary deposit 1 (highly doped p-semiconductor layer) and layer 2 (p mix semiconductor layers) in succession on non-conductive substrate 0 have the local reverse etching of layer 1 and layer 2 subsequently.After this, on layer 2, carry out the structuring deposition of layer 3 (semiconductor layer that n mixes), and carry out the structuring deposition of layer 4, each layer applies according to the method for the invention.The stratification 1 of making a living possibly need the deposition process of interrupting layer 1 to 4.After the deposition of layer 1, this can (for example through zone melt) externally crystallization again, and after this (for example through structuring in coated elements) is by further processing.This also is applied to the embodiment shown in Fig. 3 to Fig. 4 similarly.At this, the advantage of bringing is: can obtain simple relatively layer structure, in addition, metal can be made as the finger with particular structured.
The integrated form that Fig. 2 relates on the semiconductor device with metal and insulator that the different layers sequence is separated from one another is connected.Realize making the highly doped p-semiconductor layer of layer 1 expression, layer 2 expression doped p-semiconductor layer, and the semiconductor layer that layer 3 expression n mix through the planar depositions of on non-conductive substrate 0, carrying out layer 1,2 and 3.Be the local reverse etch step of layer 1,2 and 3 after this deposition step, and possibly introduce selective emitting electrode structure (emitter that the local reverse etching of possibility is highly doped or local the doping).Deposit insulator 5 subsequently, this insulator 5 can for example generate through on semiconductor structure, printing.In last step, implement metallization, on semiconductor device, applying for example is metallic finger portion metal level 4 form, that accomplish this semiconductor device.Through these metallic finger portions, the different layers sequence that is applied on the substrate can contact each other.At this, very conservative layer structure and can be favourable through the high flexibility of the every cell stripes that is no more than 7cm wide (strip width) realization.
Shown in Fig. 2 a to the modification of embodiment shown in Fig. 3, and described with the integrated form of metal and be connected, ARC serves as insulator.At this, same, at first on substrate 0, carry out the planar depositions of layer 1,2 and 3, layer 1,2 and 3 expressions with described in Fig. 3 identical layer.After deposition step, carry out the local reverse etching of layer 1,2 and 3 and introduce optionally emitter structure (possibly be the local reverse etching or local doping of highly doped emitter).Subsequently, on layer 3, deposit ARC (it represents insulating barrier simultaneously).As final step, metallize, depositing metal layers 4 is as last layer on semiconductor device.Particularly advantageously thus be: the insulating barrier that need not add.
In Fig. 3, show the selective emitter contact structures on the standard wafer, said structure can be used according to the method for the invention and make.At this, on silicon wafer, carry out the planar depositions of layer 3 (n mix emitters), subsequently local deposits or diffuse out layer 4 (a highly doped n-semiconductor) above that.Subsequently, carry out standard metallization process, consequently generate metallic finger structure 5.Then,, can carry out the planar depositions (carrying out the local reverse etching of layer 4 subsequently) of layer 3 and 4 equally, follow by standard metallization process, to make up described semiconductor structure as substituting of said process.At this, the advantage that can mention is only to obtain such semiconductor structure through extremely low expense.

Claims (16)

1. method that is used on substrate generating the semiconductor layer of partial structurtesization; Wherein, The surface of said substrate at least once receives the effect of gas by the zone, and this gas is used for deposition, doping and/or the etching in the zone of partial structurtes semiconductor layer to be generated.
2. the method for claim 1 is characterized in that, realizes the erosion by the zone, makes the surface of said substrate receive the air-flow effect through following:
A) through at least one shadow mask, the recess of this mask is corresponding with the structure of partial structurtes layer to be generated, and/or
B) especially through at least one nozzle.
3. like the described method of last claim, it is characterized in that said air communication is crossed nozzle and realized that this nozzle has integrated gas activation possibility, preferably gas heated and/or plasma-activated possibility.
4. like one of preceding two claims described method; It is characterized in that; The interval on said at least one shadow mask and/or said at least one said surface of nozzle distance is between 0.1mm and 10mm, preferably between 0.5mm and 5mm, particularly preferably between 1mm and 2mm.
5. like a described method in the claim 2 to 4, it is characterized in that said shadow mask is coated with SiO 2, Si 3N 4, SiC and/or Al 2O 3
6. like one of aforementioned claim described method; It is characterized in that, said surface, utilize the zone that said gas corrodes be defined between 0.1mm and the 20mm, preferably between 0.2mm and the 2mm, the width between 0.3mm and 1mm particularly preferably.
7. like one of aforementioned claim described method; It is characterized in that; Said gas is selected from the group that is made up of hydrogen chloride, hydrogen, chlorosilane, phosphine, hydride, boron chloride, trimethyl-phosphine and/or vapor-phase fluoride and/or its mixture, and said vapor-phase fluoride is CF particularly 4Or SF 6
8. like one of aforementioned claim described method, it is characterized in that:
A) during corroding the temperature of said substrate and/or said gas between 200 ℃ and 2000 ℃, preferably between 500 ℃ and 1500 ℃, more preferably between 1000 ℃ and 1200 ℃ or between 500 ℃ and 999 ℃, perhaps
B) said method serviceability temperature gradient realizes.
9. like one of aforementioned claim described method, it is characterized in that this method utilizes the CVD coating unit to realize.
10. like one of aforementioned claim described method, it is characterized in that said method is implemented as continuation method, said substrate moves with respect to the zone that utilizes etching gas to corrode in one dimension, two dimension or three-dimensional.
11., it is characterized in that said substrate is selected from and comprises following group like one of aforementioned claim described method:
A) Semiconductor substrate, particularly Si-, GaAs-, Ge-, SiC Semiconductor substrate and/or its combination,
B) have the carrier substrate of coated semiconductor, the semiconductor layer of said partial structurtesization is fabricated on the said coated semiconductor and/or in the said coated semiconductor,
C) metal,
D) glass and/or pottery, and also have
E) combination of aforesaid substrate.
12. as the described method of one of aforementioned claim, it is characterized in that, before implementing said method and/or afterwards, implement the plane doping on the surface of said Semiconductor substrate.
13., it is characterized in that the reverse etching of part at least of the semiconductor layer of said partial structurtesization is implemented as another subsequent method step like one of aforementioned claim described method.
14., it is characterized in that this method is implemented repeatedly like one of aforementioned claim described method.
15. according to the purposes of the described method of one of aforementioned claim in solar cell generates, be used for the epitaxial semiconductor layer on the Semiconductor substrate deposition, be used for the microcrystalline semiconductor layer on the Semiconductor substrate deposition, be used for Semiconductor substrate partial structurtesization doping semiconductor layer inside diffusion, be used for semiconductor layer structuring with the structuring that is used for circuit connected in series, is used for metal level to be used for connected in series and/or to be used for the localized metallic deposition.
16. a solar cell comprises emitter layer, this emitter layer can be according to generating like the described method of one of claim 1 to 14.
CN2010800579372A 2009-12-18 2010-12-17 Method for producing locally structured semiconductor layers Pending CN102804409A (en)

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Application publication date: 20121128