CN102810502A - Method for forming shallow trench isolating structure - Google Patents
Method for forming shallow trench isolating structure Download PDFInfo
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- CN102810502A CN102810502A CN2011101461938A CN201110146193A CN102810502A CN 102810502 A CN102810502 A CN 102810502A CN 2011101461938 A CN2011101461938 A CN 2011101461938A CN 201110146193 A CN201110146193 A CN 201110146193A CN 102810502 A CN102810502 A CN 102810502A
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Abstract
The invention discloses a method for forming a shallow trench isolating structure. The method comprises the following steps of: providing a semiconductor substrate; forming a hard mask layer on the substrate; etching the hard mask layer and the substrate to form grooves; forming groove widening parts at the bottoms of the grooves; filling insulating layers in the grooves; and polishing so as to remove the insulating layers on the substrate. By the method for forming the shallow trench isolating structure, the technical problem that the insulating effect of the shallow trench isolating structure is reduced when photoetching for injection of ions of the well regions is deviated in a semiconductor manufacturing process can be effectively solved, an isolating effect can be improved, a process window is enlarged, and accordingly the yield of semiconductor devices is increased.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly be used to form the method for isolation structure of shallow trench.
Background technology
In recent years, along with the development of semiconductor integrated circuit manufacturing technology, the quantity of contained device constantly increases in the chip, and size of devices is also constantly dwindled because of the lifting of integrated level, and the line width that uses on the production line has got into the tiny scope of sub-micron.Yet no matter how downsizing of device size still must have suitably insulation or isolates between each device in chip, can obtain good device performance.This technology is commonly referred to as device separation (device isolation technology); Its main purpose is between each device, to form spacer; And under the situation of guaranteeing the good effect; Dwindle the zone of spacer as far as possible, hold more device to vacate more chip area.In various element separation technology, the localized oxidation of silicon method (Loca1 Oxidation, LOCOS) and shallow trench isolation (Shallow Trench Isolation STI) is the most normal adopted two kinds of technology.
Fig. 1 (A)-1 (D) is the sketch map that forms isolation structure of shallow trench in the prior art.Shown in Fig. 1 (A), semiconductor front end device 100 at first is provided, comprise Semiconductor substrate 102, and on Semiconductor substrate 102, form pad silicon oxide layer 104, silicon nitride layer 106 successively respectively; Shown in Fig. 1 (B),,, thereby form shallow grooves 108 with dry etching method etch silicon nitride layer 106, pad silicon oxide layer 104 and Semiconductor substrate 102 then through the shallow trench isolation etching technics; Shown in Fig. 1 (C); Through high density plasma CVD method (HDPCVD; High Density Plasma Chemical Vapor Deposition) or high-aspect-ratio technology (HARP) on silicon nitride layer 106, form insulating barrier 110, and said insulating barrier 110 is filled said shallow grooves 108 full.Then, shown in Fig. 1 (D), insulating barrier 110 is carried out planarization; For example, adopt CMP process (CMP, Chemical Mechanical Polishing) to remove the insulating barrier 110 on the silicon nitride layer 106; And then through wet etching removal silicon nitride layer 106 and pad silicon oxide layer 104; Final formation isolation structure of shallow trench is a shallow trench isolation channels 108, and wherein, the part of removing in the substrate 102 outside the shallow trench isolation channels 108 is an active area.
Yet, more serious defective often appears when adopting above-mentioned technical process to form isolation structure of shallow trench.Fig. 2 (A)-2 (B) has explained the defective sketch map of the isolation structure of shallow trench existence of using prior art formation, and wherein semiconductor device 200 comprises N type ion implanted region 202, well region mask 204, shallow trench isolation channels 210, P well region 206 and N well region 208.Shown in Fig. 2 (A); Arrow 212 expression isolation structure of shallow trench can provide the good insulation performance effect in the ordinary course of things; But shown in Fig. 2 (B); When the photoetching skew of well region ion injection took place in semiconductor fabrication, the insulation effect of arrow 212 expression isolation structure of shallow trench was lowered, and this influences the yields of semiconductor device probably.
Therefore; This area needs a kind of method of improved formation isolation structure of shallow trench; The technical problem that the insulation effect of isolation structure of shallow trench reduces in the time of can overcoming the photoetching skew that the injection of well region ion takes place effectively in semiconductor fabrication; Thereby improve the yields of making semiconductor device, and have simple manufacturing process and lower cost simultaneously.
Summary of the invention
The technical problem that the insulation effect of isolation structure of shallow trench reduces when squinting in order to overcome the photoetching that the injection of well region ion takes place effectively in semiconductor fabrication, the present invention improves the method that forms isolation structure of shallow trench.
The present invention proposes a kind of method that is used to form isolation structure of shallow trench, comprises the following steps: to provide Semiconductor substrate; On said substrate, form hard mask layer; Said hard mask layer and substrate are carried out etching, to form groove; Form the groove those widened sections at said bottom portion of groove; In said groove, fill insulating barrier; And carry out polishing step, to remove the said insulating barrier on the said substrate.
Wherein further comprise etching step, to remove the said hard mask layer on the said substrate.
Wherein forming said hard mask layer comprises and forms first oxide skin(coating) and silicon nitride layer successively.
Wherein said formation groove those widened sections comprises the following steps: deposition second oxide skin(coating) on said hard mask layer and said groove; Said second oxide skin(coating) is carried out etching, be positioned at second oxide skin(coating) of bottom portion of groove with removal; Said groove is carried out isotropic etching, to form the groove those widened sections.
Wherein, said bottom portion of groove further comprises the following steps: in said groove those widened sections, to form the trioxide layer after forming the groove those widened sections; Said trioxide layer is carried out etching, with the trioxide layer of the bottom of removing said groove those widened sections; And carry out etch step, with further intensification groove.
Wherein said groove those widened sections is in the middle and lower part of said groove.
The degree of depth on the surface of the said substrate of wherein said groove those widened sections distance is the 100-2000 dust.
The thickness of wherein said groove those widened sections is the 20-2000 dust.
Wherein said second oxide skin(coating) is carried out the step use dry etching of etching.
Wherein in the step that forms the groove those widened sections, use isotropic silicon wet etching.
Wherein form said trioxide layer and use thermal oxidation technology.
The wherein said step use dry etching that said trioxide layer is carried out etching.
Wherein carry out the step of said further intensification groove and use dry etching.
Method according to formation isolation structure of shallow trench of the present invention; The technical problem that the insulation effect of isolation structure of shallow trench reduces in the time of can overcoming the photoetching skew that the injection of well region ion takes place effectively in semiconductor fabrication; And can improve isolation effect and increase process window, thereby improve the yields of making semiconductor device.And method of the present invention has simple manufacturing process and lower cost simultaneously.
Description of drawings
Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 (A)-1 (D) is the method sketch map that forms isolation structure of shallow trench in the prior art;
The defective sketch map that Fig. 2 (A)-2 (B) exists for the isolation structure of shallow trench that uses prior art formation;
Fig. 3 (A)-3 (G) is for form the method sketch map of isolation structure of shallow trench according to one embodiment of present invention;
Fig. 4 is the isolation structure of shallow trench sketch map according to the embodiment formation of Fig. 3 (A)-3 (G);
Fig. 5 (A)-5 (E) is the method sketch map of formation isolation structure of shallow trench according to an embodiment of the invention;
Fig. 6 is the isolation structure of shallow trench sketch map according to the embodiment formation of Fig. 5 (A)-5 (E);
Fig. 7 is for form the method flow diagram of isolation structure of shallow trench according to one embodiment of present invention;
Fig. 8 is the method flow diagram of the groove those widened sections of isolation structure of shallow trench formed according to the present invention; And
When being isolation structure of shallow trench formed according to the present invention, further deepens Fig. 9 the method flow diagram of groove.
Embodiment
Next, will combine accompanying drawing more intactly to describe the present invention, embodiments of the invention be shown in the accompanying drawing.But the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, it is thorough and complete to provide these embodiment to expose, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, the size in layer and district and relative size maybe be by exaggerative.Same reference numerals is represented components identical from start to finish.
Only if in addition definition has the identical implication with the those of ordinary skill institute common sense in field of the present invention at all terms (comprising technology and scientific terminology) of this use.Also will understand; Defined term is to be understood that to having and the consistent implication of they implications in the environment of association area and/or these specifications in the dictionary such as common use; And can not on desirable or excessively formal meaning, explain, only if show ground definition so here clearly.
In order to solve the problems referred to above that exist in the prior art, the present invention improves the method that forms isolation structure of shallow trench.Fig. 3 (A)-3 (G) is for form the method sketch map of isolation structure of shallow trench according to one embodiment of present invention.Shown in Fig. 3 (A); Semiconductor front end device 300 at first is provided; Comprise Semiconductor substrate 302; And on Semiconductor substrate 302, form pad silicon oxide layer 304, silicon nitride layer 306 successively respectively as hard mask layer, and can adopt the method for deposition to form said hard mask layer, for example use chemical meteorology deposition or physics vapor phase deposition; Shown in Fig. 3 (B), through the shallow trench isolation etching technics, the photoresist that utilizes patterning with dry etching method etch silicon nitride layer 306, pad silicon oxide layer 304 and Semiconductor substrate 302, thereby forms groove 308 as mask; Shown in Fig. 3 (C), deposited oxide layer 310 on silicon nitride layer 306 and groove 308 specifically can be silicon oxide layer 310, for example uses chemical meteorology deposition or physics vapor phase deposition; Shown in Fig. 3 (D), silicon oxide layer 310 is carried out etching, for example use the oxide dry etching, remove the silicon oxide layer of bottom portion of groove, and the silicon oxide layer 310 on the sidewall of reservation groove 308; Shown in Fig. 3 (E); Groove 308 is carried out isotropic etching, be specially the isotropic wet etching, to form groove those widened sections 312; Preferably the degree of depth on the surface of the said substrate of groove those widened sections 312 distances is the 100-2000 dust, and groove those widened sections 312 preferred thickness are the 20-2000 dust; Shown in Fig. 3 (F); In groove 308, fill insulating barrier 316; Promptly in groove 308, fill insulating barrier 316 and make insulating barrier 316 cover silicon nitride layer 306; For example use high density plasma CVD or high-aspect-ratio technology, said insulant can be oxide, is specially silica; Shown in Fig. 3 (G); Insulating barrier 316 is carried out planarization, for example use CMP process, and remove silicon nitride layer 306 and pad silicon oxide layer 304 through etching; The final isolation structure of shallow trench that comprises shallow trench isolation channels 308 that forms; Wherein, comprise insulating barrier 316 in the shallow trench isolation channels 308, and the part of removing in the substrate 302 outside the shallow trench isolation channels 308 is an active area.
Fig. 4 is the isolation structure of shallow trench sketch map according to the embodiment formation of Fig. 3 (A)-3 (G).As shown in Figure 4, semiconductor device 400 comprises N type ion implanted region 402, well region mask 404, shallow trench isolation channels 410, P well region 406 and N well region 408.Wherein shallow trench isolation channels 410 has the groove those widened sections; Therefore shown in arrow 412; Even when the photoetching skew of well region ion injection took place in semiconductor fabrication, shallow trench isolation channels 410 also can provide the good insulation performance effect, thereby improved the yields of semiconductor device 400.
Fig. 5 (A)-5 (E) is the method sketch map of formation isolation structure of shallow trench according to an embodiment of the invention, compares with the embodiment of Fig. 3 (A)-3 (G), after the step of Fig. 3 (F), before the step of Fig. 3 (G), groove is further deepened.Shown in Fig. 5 (A), carry out step of thermal oxidation in groove those widened sections 512, to form oxide skin(coating) 514, specifically can be silicon oxide layer 514; Shown in Fig. 5 (B), silicon oxide layer 514 is carried out dry etching, with the silicon oxide layer of removal exposure, and the silicon oxide layer 514 on the sidewall of reservation groove those widened sections 512; Shown in Fig. 5 (C), carry out etching technics, with further intensification groove 508; Shown in Fig. 5 (D); In groove 508, fill insulating barrier 516; Promptly in groove 508, fill insulating barrier 516 and make insulating barrier 516 cover silicon nitride layer 506; For example use high density plasma CVD or high-aspect-ratio technology, said insulant can be oxide, is specially silica; Shown in Fig. 5 (E), insulating barrier 516 is carried out planarization, for example use CMP process, and remove silicon nitride layer 506 and pad silicon oxide layer 504, the final isolation structure of shallow trench that comprises shallow trench isolation channels 508 that forms through etching.Wherein, groove those widened sections 512 is positioned at the middle and lower part of groove 508.
Fig. 6 is the isolation structure of shallow trench sketch map according to the embodiment formation of Fig. 5 (A)-5 (E).As shown in Figure 6, semiconductor device 600 comprises N type ion implanted region 602, well region mask 604, shallow trench isolation channels 610, P well region 606 and N well region 608.Wherein shallow trench isolation channels 610 has the groove those widened sections; And the degree of depth of groove is darker; Therefore shown in arrow 612, even when photoetching skew that the well region ion injects takes place in semiconductor fabrication, shallow trench isolation channels 610 also can provide the good insulation performance effect; And have better insulation effect with respect to further not deepening groove 508, thereby improve the yields of semiconductor device 600.
Fig. 7 is for form the method flow of isolation structure of shallow trench according to one embodiment of present invention.As shown in Figure 7, in step 702, Semiconductor substrate is provided at first, and on Semiconductor substrate, forms hard mask layer, said hard mask layer comprises first silicon oxide layer, silicon nitride layer; In step 704,,, thereby form groove with dry etching method etching hard mask layer and Semiconductor substrate through the shallow trench isolation etching technics; In step 706, form the groove those widened sections at bottom portion of groove; In step 708, in groove, form insulating barrier, promptly in groove, fill insulating barrier; In step 710, insulating barrier is carried out planarization, and remove said hard mask layer, thus the final isolation structure of shallow trench that comprises shallow trench isolation channels that forms.
Fig. 8 is the method flow diagram according to the groove those widened sections of formation isolation structure of shallow trench of the present invention.As shown in Figure 8, in step 802, deposition second oxide skin(coating) specifically can be a silicon oxide layer on hard mask layer and groove; In step 804, second oxide skin(coating) is carried out etching, in order to second oxide skin(coating) on the sidewall that only keeps groove, and remove second oxide skin(coating) of other part; In step 806, groove is carried out etching, to form the groove those widened sections.
When being isolation structure of shallow trench formed according to the present invention, further deepens Fig. 9 the method flow diagram of groove.As shown in Figure 9, in step 902, in the groove those widened sections, form the trioxide layer, specifically can be silicon oxide layer; In step 904, the trioxide layer is carried out etching, in order to the trioxide layer of the bottom of removing the groove those widened sections, and only keep the trioxide layer on the sidewall of groove those widened sections; In step 906, carry out etching technics, with further intensification groove.
According to method provided by the invention; The technical problem that the insulation effect of isolation structure of shallow trench reduces in the time of can overcoming the photoetching skew that the injection of well region ion takes place effectively in semiconductor fabrication; And can enlarge semi-conductive process window, thereby improve the yields of making semiconductor device.And said method has simple manufacturing process and lower cost simultaneously.
Although described a plurality of embodiment among this paper, should be appreciated that it may occur to persons skilled in the art that multiple other modifications and embodiment, they will fall in the spirit and scope of design disclosed by the invention.More particularly, in the scope of, accompanying drawing open and accompanying claims, carry out various modifications and change aspect the arrangement mode that can arrange in the combination of theme and/or the part in the present invention.Except the modification of part and/or arrangement mode with the change, the use of replaceable mode also is conspicuous selection to those skilled in the art.
Claims (13)
1. a method that is used to form isolation structure of shallow trench comprises the following steps:
Semiconductor substrate is provided;
On said substrate, form hard mask layer;
Said hard mask layer and substrate are carried out etching, to form groove;
Form the groove those widened sections at said bottom portion of groove;
In said groove, fill insulating barrier; And
Carry out polishing step, to remove the said insulating barrier on the said substrate.
2. the method for claim 1 further comprises etching step, to remove the said hard mask layer on the said substrate.
3. according to claim 1 or claim 2 method wherein forms said hard mask layer and comprises and form first oxide skin(coating) and silicon nitride layer successively.
4. the method for claim 1, wherein said formation groove those widened sections comprises the following steps:
Deposition second oxide skin(coating) on said hard mask layer and said groove;
Said second oxide skin(coating) is carried out etching, be positioned at second oxide skin(coating) of bottom portion of groove with removal;
Said groove is carried out isotropic etching, to form the groove those widened sections.
5. the method for claim 1 wherein further comprises the following steps: after said bottom portion of groove forms the groove those widened sections
In said groove those widened sections, form the trioxide layer; And
Said trioxide layer is carried out etching, with the trioxide layer of the bottom of removing said groove those widened sections; And
Carry out etch step, with further intensification groove.
6. method as claimed in claim 5, wherein said groove those widened sections is in the middle and lower part of said groove.
7. the method for claim 1, the degree of depth on the surface of the said substrate of wherein said groove those widened sections distance is the 100-2000 dust.
8. the method for claim 1, the thickness of wherein said groove those widened sections is the 20-2000 dust.
9. method as claimed in claim 4 is wherein used dry etching to the step that said second oxide skin(coating) carries out etching.
10. method as claimed in claim 4 is wherein used the isotropism wet etching in the step that forms the groove those widened sections.
11. method as claimed in claim 5 wherein forms said trioxide layer and uses thermal oxidation technology.
12. method as claimed in claim 5, the wherein said step use dry etching that said trioxide layer is carried out etching.
13. method as claimed in claim 5 is wherein carried out the step of said further intensification groove and is used dry etching.
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| CN2011101461938A CN102810502A (en) | 2011-06-01 | 2011-06-01 | Method for forming shallow trench isolating structure |
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| CN2011101461938A CN102810502A (en) | 2011-06-01 | 2011-06-01 | Method for forming shallow trench isolating structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113539949A (en) * | 2020-04-21 | 2021-10-22 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207532B1 (en) * | 1999-09-30 | 2001-03-27 | Taiwan Semiconductor Manufacturing Company | STI process for improving isolation for deep sub-micron application |
| CN1374689A (en) * | 2001-03-14 | 2002-10-16 | 矽统科技股份有限公司 | Prepn of shallow-channel isolating element with low pressure lining |
| CN101213649A (en) * | 2005-06-28 | 2008-07-02 | 美光科技公司 | Semiconductor processing methods, and semiconductor constructions |
| US20090045482A1 (en) * | 2007-08-14 | 2009-02-19 | Jhon-Jhy Liaw | Shallow Trench Isolation with Improved Structure and Method of Forming |
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- 2011-06-01 CN CN2011101461938A patent/CN102810502A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207532B1 (en) * | 1999-09-30 | 2001-03-27 | Taiwan Semiconductor Manufacturing Company | STI process for improving isolation for deep sub-micron application |
| CN1374689A (en) * | 2001-03-14 | 2002-10-16 | 矽统科技股份有限公司 | Prepn of shallow-channel isolating element with low pressure lining |
| CN101213649A (en) * | 2005-06-28 | 2008-07-02 | 美光科技公司 | Semiconductor processing methods, and semiconductor constructions |
| US20090045482A1 (en) * | 2007-08-14 | 2009-02-19 | Jhon-Jhy Liaw | Shallow Trench Isolation with Improved Structure and Method of Forming |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113539949A (en) * | 2020-04-21 | 2021-10-22 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| WO2021213129A1 (en) * | 2020-04-21 | 2021-10-28 | 长鑫存储技术有限公司 | Semiconductor structure and fabrication method therefor |
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Application publication date: 20121205 |