CN102810509A - Preparation process of dual-damascene shallow-redundancy metal - Google Patents
Preparation process of dual-damascene shallow-redundancy metal Download PDFInfo
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- CN102810509A CN102810509A CN2012102931526A CN201210293152A CN102810509A CN 102810509 A CN102810509 A CN 102810509A CN 2012102931526 A CN2012102931526 A CN 2012102931526A CN 201210293152 A CN201210293152 A CN 201210293152A CN 102810509 A CN102810509 A CN 102810509A
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Abstract
The invention discloses a manufacturing process of dual-damascene shallow-redundancy metal. A redundant metal pattern is added on a light mask plate of a through hole, and a dual-damascene structure with the shallow-redundancy metal is formed by adopting a prior dual-damascene process in a part of a groove of a metal hard mask. Therefore, the parasitic capacitance of a metal interconnection wire can be reduced, the interconnection RC (resistor-capacitor) delay can be improved, and the chemical-mechanical polishing (CMP) process cannot be deteriorated simultaneously. Moreover, the process is simple, the steps of the process cannot be increased, and the preparation process is fully compatible with the prior copper dual-damascene process in the part of the groove of the metal hard mask.
Description
Technical field
The present invention relates to the semiconductor process techniques field, relate in particular to the shallow redundant metal preparation technology of a kind of dual damascene.
Background technology
Along with the semiconductor integrated circuit characteristic size continue reduce; Back segment interconnection resistance electric capacity (Resistor Capacitor; Abbreviation RC) postpones to appear the trend of remarkable increase; Postpone in order to reduce back segment interconnection RC, introduce low-k (Low-k) material, and the interconnection of copper-connection replacement aluminium becomes main flow technology.Because the manufacture method of copper interconnecting line can not form through etching sheet metal as aluminum interconnecting, so copper Damascus mosaic technology becomes the standard method that copper interconnecting line is made.
Copper Damascus technics processing procedure is: deposit one dielectric layer on planar substrates; In dielectric layer, form through hole and the groove of inlaying through photoetching and etching technics; Depositing metal barrier layer and copper seed layer; Plated metal copper fills up through hole and groove in the dielectric layer; Excess metal on the dielectric layer is removed in cmp (CMP) planarization, forms planar copper interconnect.
In order to improve the CMP process uniformity, reduce metallic copper dish (Dishing) and dielectric material erosion (Erosion) defective that CMP technology causes, redundant (Dummy) metal filled technology is arisen at the historic moment; So-called redundant metal filled, be meant that filling redundant metal at the white space of domain improves the metal layer image density uniformity.Common redundant metal is filled on the metal level mask in metal level mask manufacturing process, and together makes with the layer metal interconnection line.Therefore, final redundant metal thickness and the metal interconnecting wires consistency of thickness that forms of dual damascene process.
Yet the introducing of redundant metal can cause the increase of interconnection line parasitic capacitance, worsen back segment interconnection resistance electric capacity (Resistor Capacitor is called for short RC) and postpone, particularly along with characteristic size to reduce its influence more obvious.Irrespective problem must not become in the influence that reduces redundant metal pair interconnection line parasitic capacitance.
In order to address the above problem, a kind of mode that proposes at present is to reduce the thickness of redundant metal.Yet the making of common shallow redundant metal needs to increase an independent redundancy metallic mask and carries out chemical wet etching, to form shallow redundant metal valley; This can increase processing step, improves production cost.
In addition; Introducing along with low-K material; Particularly in the introducing of 45nm and following processing procedure porous low dielectric constant material (Porous Low-k), in order to reduce the damage of etching technics to Porous Low-k material, the preferential dual damascene process of metal hard mask part groove becomes main flow technology.And above-mentioned present employing pass through increase an independent redundancy metallic mask make the method for shallow redundant metal can not be compatible with the preferential dual damascene process of metal hard mask part groove.
Therefore, be necessary to propose a kind of simple and shallow redundant metal fabrication methods of the preferential dual damascene process of compatible metal hard mask part groove fully, to reduce the interconnection line parasitic capacitance that redundant metal causes.
Summary of the invention
The object of the present invention is to provide the shallow redundant metal preparation technology of a kind of dual damascene; Reducing the interconnection line parasitic capacitance that redundant metal causes, and the shallow redundant metal fabrication methods of the preferential dual damascene process of compatible metal hard mask part groove fully.
For addressing the above problem, the present invention proposes the shallow redundant metal preparation technology of a kind of dual damascene, comprises the steps:
The semiconductor matrix is provided, wherein, has been formed with N layer metal level on the said semiconductor substrate;
Deposit etching barrier layer, dielectric layer, dielectric protection layer and metal hard mask layer successively on said N layer metal level;
Spin coating photoresist on said metal hard mask layer, and said photoresist is carried out photoetching through the metal level photomask, in said photoresist, form the metal interconnecting wires groove figure;
With said patterned photoresist is mask, and said metal hard mask layer is carried out etching, in said metal hard mask layer, forms the metal interconnecting wires groove figure, and removes remaining photoresist;
The spin coating photoresist, and said photoresist is carried out photoetching through the through hole photomask, wherein said through hole photomask is provided with redundant metallic pattern, in said photoresist, forms via hole image and redundant metallic pattern;
With said patterned photoresist is mask, and said dielectric protection layer is carried out etching, and said dielectric layer is carried out partial etching, in said dielectric layer, forms the partial through holes figure; Simultaneously said metal hard mask layer is carried out partial etching, in said metal hard mask layer, form redundant metallic pattern; And remove remaining photoresist;
With patterned metal hard mask layer is that mask carries out etching to said dielectric protection layer and dielectric layer; In said dielectric layer, form metal interconnected line trenches and redundant metal valley; And open the etching barrier layer of said partial through holes figure bottom, form double damask structure;
Said double damask structure is metallized, form N+1 layer metal level with metal interconnecting wires, through-hole interconnection and redundant metal.
Optional, said N layer metal level is the ground floor metal level, said N+1 layer metal level is the second layer metal layer.
Optional, the technology of said deposit etching barrier layer, dielectric layer and dielectric protection layer is CVD method.
Optional, the material of said etching barrier layer is one or more among SiCN, SiN, SiC, the SiCO.
Optional, the material of said dielectric layer is a low-K dielectric material.
Optional, said low-K dielectric material is SiOCH.
Optional, the material of said dielectric protection layer is any among SiO2, SiON, the SIN.
Optional, the technology of said depositing metal hard mask layer is the physical vapor deposition method.
Optional, the material of said metal hard mask layer is one or more among TiN, Ti, TaN, Ta, WN, the W.
Optional, the degree of depth of the said partial through holes figure that in dielectric layer, forms is the 120%-200% of through-hole interconnection height.
Optional, the degree of depth of the said redundant metallic pattern that in metal hard mask layer, forms is the 70%-90% of metal hard mask layer thickness.
Optional, said double damask structure is metallized comprises the steps: to carry out at first successively metal barrier deposit, copper seed layer deposit, plating filling metallic copper; The cmp planarization is removed excess metal to dielectric layer then, forms the N+1 layer metal level with metal interconnecting wires, through-hole interconnection and redundant metal.
Optional, the degree of depth of said redundant metal valley is between dielectric layer height and metal interconnecting wires gash depth that cmp is removed.
Optional, the degree of depth of said redundant metal valley equals the dielectric layer height that cmp is removed.
Compared with prior art; The shallow redundant made technology of dual damascene provided by the invention is through adding redundant metallic pattern on the through hole photomask; Adopt the preferential dual damascene process of metal hard mask part groove to form the double damask structure that has shallow redundant metal; Thereby can reduce the metal interconnecting wires parasitic capacitance, improve interconnection RC and postpone can not worsen cmp (CMP) technology simultaneously; And technology is simple, does not increase processing step, fully the preferential copper dual damascene of the hard mask part of compatible metal groove manufacturing process.
Description of drawings
The flow chart of the shallow redundant made technology of dual damascene that Fig. 1 provides for the embodiment of the invention;
Fig. 2 A to Fig. 2 G is the corresponding device architecture sketch map of each step of the shallow redundant made technology of dual damascene that provides of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the shallow redundant made technology of dual damascene that the present invention proposes is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is; Provide a kind of dual damascene shallow redundant made technology; Through on the through hole photomask, adding redundant metallic pattern, adopt the preferential dual damascene process of metal hard mask part groove to form the double damask structure that has shallow redundant metal, thereby can reduce the metal interconnecting wires parasitic capacitance; Improving interconnection RC postpones can not worsen cmp (CMP) technology simultaneously; And technology is simple, does not increase processing step, fully the preferential copper dual damascene of the hard mask part of compatible metal groove manufacturing process.
Please refer to Fig. 1 and Fig. 2 A to Fig. 2 G; Wherein, The flow chart of the shallow redundant made technology of dual damascene that Fig. 1 provides for the embodiment of the invention; Fig. 2 A to Fig. 2 G is the corresponding device architecture sketch map of each step of the shallow redundant made technology of dual damascene that provides of the embodiment of the invention, and shown in Fig. 1 and Fig. 2 A to Fig. 2 G, the shallow redundant made technology of the dual damascene that the embodiment of the invention provides comprises the steps:
S101, semiconductor matrix 101 is provided, wherein, has been formed with N layer metal level 102 on the said semiconductor substrate 101; In embodiments of the present invention, this N layer metal level 102 is a first metal layer;
S102, on said N layer metal level 102 deposit etching barrier layer 103, dielectric layer 104, dielectric protection layer 105 and metal hard mask layer 106 successively, shown in Fig. 2 A;
S103, on said metal hard mask layer 106 spin coating photoresist 107, and said photoresist 107 is carried out photoetching through the metal level photomask, in said photoresist 107, form the metal interconnecting wires groove figure, shown in Fig. 2 B;
S104, be mask, said metal hard mask layer 106 is carried out etching, in said metal hard mask layer 106, form the metal interconnecting wires groove figure, and remove remaining photoresist with said patterned photoresist 107; Remove device architecture figure behind the remaining photoresist shown in Fig. 2 C;
S105, spin coating photoresist 108, and said photoresist 108 is carried out photoetching through the through hole photomask, wherein said through hole photomask is provided with redundant metallic pattern, in said photoresist 108, forms via hole image and redundant metallic pattern, shown in Fig. 2 D;
S106, be mask, said dielectric protection layer 105 carried out etching, and said dielectric layer 104 is carried out partial etching, in said dielectric layer 104, form partial through holes figure 109 with said patterned photoresist 108; Simultaneously said metal hard mask layer 106 is carried out partial etching, in said metal hard mask layer 106, form redundant metallic pattern 110; And remove remaining photoresist; Remove device architecture figure behind the remaining photoresist shown in Fig. 2 E;
S107, be that mask carries out etching to said dielectric protection layer 105 and dielectric layer 104 with patterned metal hard mask layer 106; In said dielectric layer 104, form metal interconnected line trenches 111 and redundant metal valley 113; And open the etching barrier layer 103 of said partial through holes figure bottom; Form through-hole interconnection figure 112, thereby form double damask structure; Device architecture figure after this step is accomplished is shown in Fig. 2 F;
S108, said double damask structure is metallized, form N+1 layer metal level, shown in Fig. 2 G with metal interconnecting wires 114, through-hole interconnection 115 and redundant metal 116; Wherein in embodiments of the present invention, said N+1 layer metal level is second metal level.
Further, the technology of said deposit etching barrier layer 103, dielectric layer 104 and dielectric protection layer 105 is CVD method; Wherein, the material of said etching barrier layer 103 is one or more among SiCN, SiN, SiC, the SiCO; The material of said dielectric layer 104 is a low-K dielectric material, and particularly, said low-K dielectric material is SiOCH; The material of said dielectric protection layer 105 is any among SiO2, SiON, the SIN.
Further, the technology of said depositing metal hard mask layer 106 is the physical vapor deposition method; The material of said metal hard mask layer 106 is one or more among TiN, Ti, TaN, Ta, WN, the W.
Further; The degree of depth of the said partial through holes figure 109 that in dielectric layer 104, forms is the 120%-200% of through-hole interconnection 115 height; Thereby can guarantee that follow-up trench dielectric layer etching both had been unlikely to the insufficient over etching that also do not take place of etching, and adjustment via etch process control redundancy structural region keeps suitable metal hard mask thickness.
Further, the degree of depth of the said redundant metallic pattern 110 that in metal hard mask layer 106, forms is the 70%-90% of metal hard mask layer 106 thickness, is beneficial to the control of the redundant metal valley degree of depth in follow-up trench dielectric layer etching technics and the etching process.
Further, said double damask structure is metallized comprises the steps: to carry out at first successively metal barrier deposit, copper seed layer deposit, plating filling metallic copper; The cmp planarization is removed excess metal to dielectric layer then, forms the N+1 layer metal level with metal interconnecting wires, through-hole interconnection and redundant metal.
Further, the degree of depth of said redundant metal valley 113 is between the dielectric layer height and metal interconnected line trenches 111 degree of depth that cmp is removed.
Preferably, the degree of depth of said redundant metal valley 113 equals the dielectric layer height that cmp is removed, thereby can in the CMP process, just in time remove redundant metal fully, eliminates the influence of redundant metal pair interconnection line parasitic capacitance.
Wherein, in a specific embodiment of the present invention, said N layer metal level is the ground floor metal level, and said N+1 layer metal level is the second layer metal layer; Yet should be realized that, repeat above-mentioned steps, can make the metal level that multilayer more has shallow redundant metal; Be that said N layer metal level can also be the second layer metal layer, said N+1 layer metal level can be three-layer metal layer etc.
In sum; The invention provides the shallow redundant made technology of a kind of dual damascene; Through on the through hole photomask, adding redundant metallic pattern, adopt the preferential dual damascene process of metal hard mask part groove to form the double damask structure that has shallow redundant metal, thereby can reduce the metal interconnecting wires parasitic capacitance; Improving interconnection RC postpones can not worsen cmp (CMP) technology simultaneously; And technology is simple, does not increase processing step, fully the preferential copper dual damascene of the hard mask part of compatible metal groove manufacturing process.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (14)
1. the shallow redundant metal preparation technology of dual damascene is characterized in that, comprises the steps:
The semiconductor matrix is provided, wherein, has been formed with N layer metal level on the said semiconductor substrate;
Deposit etching barrier layer, dielectric layer, dielectric protection layer and metal hard mask layer successively on said N layer metal level;
Spin coating photoresist on said metal hard mask layer, and said photoresist is carried out photoetching through the metal level photomask, in said photoresist, form the metal interconnecting wires groove figure;
With said patterned photoresist is mask, and said metal hard mask layer is carried out etching, in said metal hard mask layer, forms the metal interconnecting wires groove figure, and removes remaining photoresist;
The spin coating photoresist, and said photoresist is carried out photoetching through the through hole photomask, wherein said through hole photomask is provided with redundant metallic pattern, in said photoresist, forms via hole image and redundant metallic pattern;
With said patterned photoresist is mask, and said dielectric protection layer is carried out etching, and said dielectric layer is carried out partial etching, in said dielectric layer, forms the partial through holes figure; Simultaneously said metal hard mask layer is carried out partial etching, in said metal hard mask layer, form redundant metallic pattern; And remove remaining photoresist;
With patterned metal hard mask layer is that mask carries out etching to said dielectric protection layer and dielectric layer; In said dielectric layer, form metal interconnected line trenches and redundant metal valley; And open the etching barrier layer of said partial through holes figure bottom, form double damask structure;
Said double damask structure is metallized, form N+1 layer metal level with metal interconnecting wires, through-hole interconnection and redundant metal.
2. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that said N layer metal level is the ground floor metal level, and said N+1 layer metal level is the second layer metal layer.
3. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that the technology of said deposit etching barrier layer, dielectric layer and dielectric protection layer is CVD method.
4. the shallow redundant metal preparation technology of dual damascene as claimed in claim 3 is characterized in that the material of said etching barrier layer is one or more among SiCN, SiN, SiC, the SiCO.
5. the shallow redundant metal preparation technology of dual damascene as claimed in claim 3 is characterized in that the material of said dielectric layer is a low-K dielectric material.
6. the shallow redundant metal preparation technology of dual damascene as claimed in claim 5 is characterized in that said low-K dielectric material is SiOCH.
7. the shallow redundant metal preparation technology of dual damascene as claimed in claim 3 is characterized in that the material of said dielectric protection layer is any among SiO2, SiON, the SIN.
8. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that the technology of said depositing metal hard mask layer is the physical vapor deposition method.
9. the shallow redundant metal preparation technology of dual damascene as claimed in claim 8 is characterized in that the material of said metal hard mask layer is one or more among TiN, Ti, TaN, Ta, WN, the W.
10. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that the degree of depth of the said partial through holes figure that in dielectric layer, forms is the 120%-200% of through-hole interconnection height.
11. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1 is characterized in that the degree of depth of the said redundant metallic pattern that in metal hard mask layer, forms is the 70%-90% of metal hard mask layer thickness.
12. the shallow redundant metal preparation technology of dual damascene as claimed in claim 1; It is characterized in that said double damask structure is metallized comprises the steps: to carry out at first successively metal barrier deposit, copper seed layer deposit, plating filling metallic copper; The cmp planarization is removed excess metal to dielectric layer then, forms the N+1 layer metal level with metal interconnecting wires, through-hole interconnection and redundant metal.
13. the shallow redundant metal preparation technology of dual damascene as claimed in claim 12 is characterized in that, the degree of depth of said redundant metal valley is between dielectric layer height and metal interconnecting wires gash depth that cmp is removed.
14. the shallow redundant metal preparation technology of dual damascene as claimed in claim 13 is characterized in that, the degree of depth of said redundant metal valley equals the dielectric layer height that cmp is removed.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111564409A (en) * | 2020-05-18 | 2020-08-21 | 南京诚芯集成电路技术研究院有限公司 | Manufacturing method of advanced node back-end metal through hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6001733A (en) * | 1998-06-26 | 1999-12-14 | United Microelectronics Corp. | Method of forming a dual damascene with dummy metal lines |
| US20040087140A1 (en) * | 2002-08-30 | 2004-05-06 | Srdjan Kordic | Process for fabricating an electrical circuit comprising a polishing step |
| US20070224795A1 (en) * | 2006-03-22 | 2007-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy vias for damascene process |
| US20080174022A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method thereof |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
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2012
- 2012-08-16 CN CN2012102931526A patent/CN102810509A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6001733A (en) * | 1998-06-26 | 1999-12-14 | United Microelectronics Corp. | Method of forming a dual damascene with dummy metal lines |
| US20040087140A1 (en) * | 2002-08-30 | 2004-05-06 | Srdjan Kordic | Process for fabricating an electrical circuit comprising a polishing step |
| US20070224795A1 (en) * | 2006-03-22 | 2007-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy vias for damascene process |
| US20080174022A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method thereof |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111564409A (en) * | 2020-05-18 | 2020-08-21 | 南京诚芯集成电路技术研究院有限公司 | Manufacturing method of advanced node back-end metal through hole |
| WO2021232604A1 (en) * | 2020-05-18 | 2021-11-25 | 南京诚芯集成电路技术研究院有限公司 | Manufacturing method for advanced node rear-section metal through hole |
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Application publication date: 20121205 |