CN102832244A - Semiconductor device with device-side electrode exposed at substrate end and manufacture method thereof - Google Patents
Semiconductor device with device-side electrode exposed at substrate end and manufacture method thereof Download PDFInfo
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Abstract
The innovation comprises a semiconductor device with a device-side electrode exposed at a substrate end (SEDE). The semiconductor device is provided with a semiconductor substrate (SCS) with a device side, a substrate end and a semiconductor device region (SDR) arranged at the device side. In order to run the device, the device-side electrode (DSE) is formed. A through substrate groove (TST) penetrates through a semiconductor substrate to extend and touch the device-side electrode so as to be changed into the device-side electrode exposed at the substrate end. Electric connecting wires penetrate through the through substrate groove to mutually connect with the device-side electrode exposed at the substrate end. The device-side electrode can further comprise an extended support frame which is stacked under the device-side electrode exposed at the substrate end, so that the structure support can be conveniently provided for the device-side electrode when a wafer is packed.
Description
Technical field
The present invention relates generally to the semiconductor device structure field.Or rather, the invention relates to device architecture and preparation method that the power semiconductor of wafer reprocessing has been simplified in preparation, for example power metal-oxide-semiconductor field (MOSFET) and igbt (IGBT).
Background technology
For the system in package of power MOSFET device, need the bottom source power MOSFET to optimize chip layout and/or the reduction parasitic interconnected impedance relevant sometimes with encapsulation.U. S. application 11/830951 has just proposed such example, has wherein proposed a kind of polycrystal chip semiconductor encapsulation of the DC-DC of being used for transducer incremental, has a lead frame that has the wafer pad of ground connection; Be positioned at the vertical base source electrode N-passage MOSFET of wafer pad top; And an anode-substrate Schottky diode, its anode is connected in the drain electrode of vertical MOSFET.Above independent wafer pad, the Schottky diode wafer is positioned at vertical MOSFET wafer top with the mode mutual encapsulation of storehouse for Schottky diode wafer and vertical MOSFET wafer, makes the source inductance of vertical MOSFET minimum, and is convenient to heat radiation.Yet, because source electrode and grid are formed on the wafer top usually, be difficult to be connected on the gate pad, therefore upside-down mounting MOSFET wafer is very difficult simply.
Because hanging down, build device (Bulk Device) resistance brings many benefits; Therefore ten minutes needs the build device in the semi-conductor industry; When thermal resistance is low, can also keep small size, and with the ability of the thin chip of the very little substrate thickness of power semiconductor preparation etc.
Figure 1A is shown in the profile of bottom-source electrode laterally diffused MOS (BS-LDMOS) device described in the United States Patent (USP) 7554154 that is entitled as " bottom source LDMOSFET structure and method thereof " of people such as the Hebert invention of authorizing on June 30th, 2009.Through implanting very dark decanting zone 115, prepare bottom-source electrode device architecture.The BSLDMOS device is positioned on the P+ substrate 105, and P+ substrate 105 is as the bottom source electrode.P-epitaxial loayer 110 is positioned at substrate 105 tops.Below the active cell district of device; With the very dark decanting zone 115 of P+ dopant ion doping, be formed on the depths of epitaxial loayer, and extend laterally to the bottom of drain-drift region 125; To compensate the N-alloy of some savings in transistor; Thereby the doped level of adjustment N-drift region 125 makes the minimized while of gate-to-drain electric capacity, keeps very low drain-source resistance R.sub.dson.Dark decanting zone 115 also extends to bottom P+ substrate 105 downward vertically, upwards extends vertically up to body 150, on the end face below the gate oxide 135, constitutes a passage.Decanting zone 115 is both as a combining passage; Also as a source-body joint of imbedding, be used to be connected near the P+ body contact zone 155 that is formed on the end face, as a top channel; Covered by source metal 170-S, N+ doping source region 160 surrounds source metal 170-S.By the grid 140 of grid partition 165 cingens platform shapes, covered by grid cover material 170-G, be deposited on grid oxic horizon 135 tops, grid oxic horizon 135 is formed on the end face between source area 160 and the drain-drift region 125.Therefore, the passage that the body 150 through grid 140 belows forms, the electric current between grid 140 Controlling Source polar regions 160 and the drain-drift region 125 plays a lateral MOS device.Drain region 125 is deposited on field oxide 130 belows, is covered by bpsg layer 180, also can select for use passivation layer 185 to cover.Pass passivation layer 185 and bpsg layer 180, etching drain electrode joint opening makes top-side drain metal 199 through joint N+ doped region 190 contact drain regions 125, reduces contact resistance.As shown in the figure, the oxide 130 of the platform shape below platform grid 140 and 135 can form through diverse ways.These methods comprise growth or deposition oxide, from channel region or utilize the LOCOS type etching of oxidate technology.The grid 140 of platform shape has long grid length, and does not increase cell pitch and above the drain electrode extension, carry out field plating.Platform grid 140 is electric current flowing between the drain electrode below passage and gate oxide 135 and the field oxide 130, and necessary connection is provided, and reduces gate leakage capacitance.Yet units corresponding spacing and this structure and method are closely related.That is to say that because decanting zone 115 has occupied too many space, what the unit interval that is therefore obtained can be suitable is big.
Along with the technological appearance of the straight-through substrate through vias (TSV) of original technology (for example shown in Figure 1B); Nowadays the bottom source power MOSFET device also can provide the preparation of flip chip method; Make its device end downward; Through a conductive through hole independently,, redirect to its substrate terminal gate metal (top) with its device end gate metal (bottom).Otherwise, just do not have other parts of flow of charge to device architecture basically, and front end prepares process.As an example, independently the structure of conductive through hole can be the metal charge that is covered with oxide.Although have above-mentioned advantage, the independence of TSV, and the preparation process of on the back side of attenuate wafer, being correlated with all still can be brought unnecessary technologic loaded down with trivial details and cost.Therefore, still need further to simplify device architecture and preparation technology.
The application relates to following patent application:
Patent Application No. is 11/830951, and the patent that is entitled as " the polycrystalline sheet DC-DC enhanced power transducer that has efficient encapsulation " by people such as Francois Hebert submitted on July 31st, 2007 is called U. S. application 11/830951 hereinafter.
Patent Application No. is 12/749696, and the patent that is entitled as " the hybrid power semiconductor device and the method thereof at the true linerless end " by people such as Tao Feng submitted on March 30th, 2010 is called U. S. application 12/749696 hereinafter.
Quote above-mentioned patent content hereby, as being used for any and all references of intention.
Summary of the invention
Proposed to have the exposed device termination electrode (SEDE) of substrate terminal.This semiconductor device has:
A Semiconductor substrate (SCS), the semiconductor device region (SDR) that has the substrate terminal on device end, device end opposite and be positioned at the device end.
A plurality of device termination electrodes (DSE) are formed on device end top, and contact with semiconductor device region, are used for the operation of semiconductor device.
At least one straight-through substrate trenches (TST) passes Semiconductor substrate and extends, and touches the device termination electrode, thereby it is become the device termination electrode that exposes in substrate terminal.
For encapsulated semiconductor device, can pass the straight-through interconnected device termination electrode that exposes in substrate terminal of substrate trenches through conduction connecting line (or be referred to as to conduct electricity inner lead).Conduction inner lead (Conductive interconnector) can be a bonding wire, joint intermediate plate or solder projection pad.
In typical embodiment, semiconductor device comprises one and the contacted substrate terminal electrode of substrate terminal (SSE), and the substrate terminal passivation (SSPV) of a SSE top band window.SSPV has defined the exposed area of SSE, is used for when the wafer reprocessing encapsulates, smearing soldering tin material at this place.Semiconductor device can be a kind of vertical semiconductor devices (Vertical semiconductor device), and its principal current flow to the bottom from top device, or vice versa.
In a preferred embodiment, semiconductor device comprises a device end passivation (DSPV), covers the device end that exposes at the device termination electrode of substrate terminal.At least one exposes the device termination electrode in substrate terminal correspondence; A non-bracing frame that has an extension at the device termination electrode of substrate terminal that exposes in the device termination electrode; Be deposited in the device termination electrode that exposes in substrate terminal through device end passivation and this simultaneously below (exposing device termination electrode) and separate, so that expose the support on the device end-electrode structure of substrate terminal when the wafer reprocessing encapsulates, for this in substrate terminal.In addition; The bracing frame of this extension is incident upon the size on the main semiconductor substrate plane; Basically encased and exposed in the corresponding projected dimension of the device termination electrode of substrate terminal, promptly bracing frame is incident upon on the general size on the main semiconductor substrate plane more than or equal to the corresponding size that is incident upon on the main semiconductor substrate plane of device termination electrode.
In another preferred embodiment, straight-through substrate trenches is TSTW along the width of main semiconductor substrate plane, is TSTD perpendicular to the degree of depth of main semiconductor substrate plane, and preferable aspect ratio TSTW/TSTD is about 0.2 to 20.
In typical embodiment, this semiconductor device is a kind of bottom source metal oxide semiconductor field effect tube (MOSFET), have and the contacted substrate terminal drain electrode of Semiconductor substrate (SSDE), and correspondingly:
Semiconductor device region has a source area, a gate regions and a body.
The device termination electrode has:
The source electrode of contact source area and a body, and have the bracing frame of extension.
The device termination electrode that exposes that contacts gate regions in substrate terminal.
In the embodiment of an expansion, on its device end, this semiconductor device also comprises, through the bonded device end carrier (device end carrier) of insulation intermediary's knitting layer (ILBL).Wherein:
Semiconductor substrate has a substrate and is close to the thickness T SCS that disappears, and this thickness can be compared with the thickness T SDR of semiconductor device region mutually.
Device end carrier has patterned back side carrier metal; The contact devices termination electrode; This device termination electrode is not the device termination electrode that exposes in substrate terminal, and a patterned front carrier metal pad and a plurality of straight-through carrier conductive through hole are connected to back side carrier metal on the carrier metal pad of front respectively.
The thickness T DSC of device end carrier is enough big; Can sufficient structural rigidity be provided for semiconductor device; Substrate is close to the thickness T SCS that disappears makes the device termination electrode of contact produce very low back resistance substrate, and straight-through carrier conductive through hole makes the device termination electrode of contact produce very low front contact resistance.
A kind of method that has the exposed device termination electrode (SEDE) of at least one substrate terminal that is used to prepare has been proposed, so that interconnected with external environment condition.This method comprises:
A) a preparation semiconductor device region (SDR) in the device end of Semiconductor substrate (SCS).
B) on the device end, prepare a plurality of device termination electrodes (DSE) and device end passivation (DSPV), and contact with semiconductor device region, be used for the operation of semiconductor device, device end passivation makes device termination electrode mutually insulated.
C) prepare at least one straight-through substrate trenches (TST), extend through Semiconductor substrate, touch prefabricated device termination electrode, thereby it is become the device termination electrode that exposes in substrate terminal.
In typical embodiment, the straight-through substrate trenches of preparation comprises:
On Semiconductor substrate, use and form the pattern of the trench mask of band window, mask window is equivalent to the size of straight-through substrate trenches.
Directed etching is passed in that part of Semiconductor substrate and semiconductor device region in the mask window; And terminate in semiconductor device region-expose and end, thereby process straight-through substrate trenches at the interface of the device termination electrode of substrate terminal and the interface of semiconductor device region-device end passivation.
Remove the trench mask of band window.
In an additional embodiment; At above-mentioned steps b) and c) between; Also above device end passivation, extend a device termination electrode that has the horizontal expansion bracing frame, cover the device end surfaces that under device end passivation, exposes at the device termination electrode of substrate terminal basically up to it.This device termination electrode is not described predetermined device termination electrode.Can be through utilizing the mask of band window, plated metal above the device end surfaces of selected device termination electrode is till forming the bracing frame that extends.
In another exemplary embodiments, a kind of method that minimal thickness is the bottom source MOSFET of TMOSFET that is used to prepare has been proposed.This bottom source MOSFET has the exposed device end gate electrode of a substrate terminal (the device end gate electrode that substrate terminal is exposed), is convenient to be interconnected to when technology encapsulates behind wafer external environment condition.This method comprises:
A) interim Semiconductor substrate (ISS) that thickness is TISS＞TMOSFET of preparation, TISS is enough big, can be compatible with traditional semiconductor wafer process.
B) above interim semiconductor, utilize traditional semiconductor wafer process, prepare MOSFET device region (FETDR) continuously and add device end source electrode (DSSE), device end gate electrode (DSGE) and the device end passivation (DSPV) above device region, wherein:
Device end gate electrode is positioned near the device end source electrode.
Device end passivation makes device end gate electrode and device end source electrode mutually insulated.
Device end passivation has also covered the device end surfaces of device end gate electrode.
C) at the interim semi-conductive back side, be in the Semiconductor substrate of TSCS～TMOSFET at desired thickness, the interim semiconductor of attenuate, and at a substrate terminal drain electrode of its above-prepared (SSDE).
D) a preparation straight-through substrate trenches (TST); Passing substrate terminal drain electrode, Semiconductor substrate adds device region and extends; And expose the substrate terminal of device end gate electrode, thereby it is become the exposed device end gate electrode of the exposed device end gate electrode substrate terminal of substrate terminal.
In typical embodiment, the straight-through substrate trenches of preparation comprises:
Above the device end of the device in preparation, connect an interim support substrates, and with its upset.
Above the substrate terminal drain electrode; Use and form the pattern of the trench mask of a band window; Mask window is equivalent to the size of straight-through substrate trenches, etches away that part of substrate terminal drain electrode in the mask window, but ends at substrate terminal drain electrode-Semiconductor substrate interface place.
Directed etching is passed in that part of Semiconductor substrate and device region in the mask window, but ends at the interface of device region-device end gate electrode and the interface of device region-device end passivation, thereby processes straight-through substrate trenches.
Remove the trench mask of band window.
Remove interim support substrates.
Before using and forming the pattern of trench mask of a band window; Can do following improvement for foregoing; The substrate terminal passivation (SSPV) that above the substrate terminal drain electrode, can prepare a band window; The exposed area of definition substrate terminal drain electrode is so that during the technology encapsulation, apply soldering tin material behind the wafer of bottom source MOSFET.
In another embodiment, a kind of semiconductor device with following structure has been proposed:
First conductive pad on semiconductor wafer first limit;
Groove below first conductive pad has wherein been removed semi-conducting material, and wherein first pad exposes out from second limit, and second limit is on the opposite side of semiconductor wafer; And
A conduction connecting line is connected to conductive pad from second limit.
In typical embodiment, the conduction connecting line is bonding wire, conductive clip, conductive strips or solder projection pad.In another typical embodiment, conduction connecting line part at least is arranged in groove, and first end is connected on first pad, outside the groove of second end on second limit of semiconductor wafer.
In another typical embodiment, semiconductor device can be a vertical field-effect pipe (FET), and first pad is a gate pad.The residing position of gate pad can be surrounded or partly surround by the active area of vertical field-effect pipe.Semiconductor device also comprises a supporting construction above gate pad.Gate pad can be surrounded by the active area of device fully, and supporting construction can be the source electrode of an extension.The conduction connecting line can be a bonding wire, conductive clip, conductive strips or solder projection pad.
For those skilled in the art, these aspects of the present invention and a plurality of embodiment thereof will explain in the remainder of this explanation.
Description of drawings
For various embodiment of the present invention more intactly is described, can be with reference to accompanying drawing.But these accompanying drawings are only as explaining, not as the limitation of the scope of the invention.
Figure 1A representes the profile of bottom source laterally diffused MOS (BS-LDMOS) device of the with groove of first original technology described in the United States Patent (USP) 7554154;
Figure 1B representes to utilize the profile of second original technological bottom source power MOSFET device of straight-through substrate through vias (TSV);
Fig. 1 C representes to have the profile of bottom drain power MOSFET device of original technology of the grid of a plurality of with grooves;
Fig. 2 A representes the profile of the bottom source power MOSFET device of the described grid that has a plurality of with grooves of one embodiment of the present of invention;
Fig. 2 B representes the profile of the bottom source power MOSFET device of the described grid that has a plurality of with grooves of an optional embodiment of the present invention;
Fig. 3 A representes the profile of the described bottom source power MOSFET device of the first embodiment of the present invention;
Fig. 3 B representes to utilize bonding wire, technology encapsulation behind the wafer of device shown in Fig. 3 A;
Fig. 3 C representes a kind of semiconductor packages that contains bottom source power MOSFET device of the present invention;
Fig. 4 A to Fig. 4 H representes to prepare device preparing process shown in Fig. 3 A;
Fig. 5 representes the profile of second embodiment of bottom source power MOSFET device of the present invention;
Fig. 6 representes the profile of the 3rd embodiment of the bottom source power MOSFET device that has an additional devices end carrier of the present invention; And
Fig. 7 representes the profile of another embodiment of bottom source power MOSFET device of the present invention.
Embodiment
This paper contained on address following explanation and accompanying drawing only is used to explain one or more existing preferred embodiment of the present invention, and some typical selectable units and/or optional embodiment.Explain and accompanying drawing is used to explain, in itself, do not limit to the present invention.Therefore, those skilled in the art will easily grasp various changes, variation and correction.These changes, variation and correction also should be thought and belong to scope of the present invention.
Fig. 1 C representes the profile of the bottom drain power MOSFET device 1 of original technology, and this device has an active part 1a and a gate interconnection part 1b, and they all are positioned at Semiconductor substrate (SCS) 21 tops that have bottom drain metal level 22.Active part 1a has the source electrode-body 23 of a plurality of spaces and the gate regions 24 of with groove in the semiconductor device region (SDR) 3 of Semiconductor substrate 21, they all are positioned at Semiconductor substrate 21 tops.In this example, Semiconductor substrate 21 can be made up of a lightly doped extension drift layer 21b above heavily doped contact layer 21a.A plurality of source electrode-body 23 are connected with a patterned close source electrode (Intimate source electrode) 25 and parallel connection.Similar with it; Although for fear of those skilled in the art being produced unnecessary obscuring; The connection details does not here detail; But the gate regions 24 of active part 1a with groove (X-Y plane) on third dimension degree is parallel on the patterned gate electrode 26 of the gate interconnection part 1b that is positioned at device end passivation (DSPV) 29 belows through the grid slideway district 24a of a with groove.Device end insulant 28a, 28b are positioned at Semiconductor substrate 21 tops, make patterned gate electrode 26 and patterned close source electrode 25 and following semiconductor device structure insulation respectively, except those places that need contact.
Fig. 2 A representes the profile of bottom source power MOSFET 31 of the present invention, and wherein active part 31a and gate interconnection part 31b are positioned on the Semiconductor substrate (SCS) 21 that has drain metal layer 22.Although do not detail at this, after positive the processing, bottom source power MOSFET 31 can upside-down mounting.Should be clear and definite; The active part 31a of bottom source power MOSFET 31 is except having extra patterned source electrode 55 above the patterned close source electrode 25 and being electrically connected with it, and other are all similar with the active part 1a of bottom drain power MOSFET device 1.In gate interconnection part 31b, straight-through substrate trenches (TST) 57 has passed Semiconductor substrate 21 and has extended, and touches the exposed device end gate electrode (SEDGE) 56 of substrate terminal, has the exposed device end gate electrode part 56a of exposed substrate terminal.Straight-through substrate trenches 57 has a straight-through substrate trenches size 57a, and its geometric properties is that the degree of depth is TSTD, and width is TSTW.
The device end gate electrode 56 that the corresponding substrate end is exposed; Patterned source electrode 55 has also extended to gate interconnection part 31b; The bracing frame 55a that also has an extension, storehouse opened with the exposed device end gate electrode of the substrate terminal that has device end passivation 29 below simultaneously in 56 minutes.In addition, the projected dimension (X-Y plane) of the bracing frame 55a of extension must surround the exposed device end gate electrode 56 corresponding projected dimension of substrate terminal basically.Therefore, when technology encapsulated behind the wafer of bottom source power MOSFET 31, the bracing frame 55a of extension can be from the exposed device end gate electrode 56 of support substrates end on the structure.
Fig. 2 B representes the profile of an optional embodiment of the present invention, and the gate interconnection part 31b that wherein contains straight-through substrate trenches 57 is between active part 31a.Therefore, source electrode 55 has the bracing frame 55a of an extension, can cover and support straight-through substrate trenches 57 fully.
Fig. 3 A representes the profile of first embodiment of bottom source power MOSFET 35 of the present invention.According to the explanation of Fig. 2 A, for a person skilled in the art, for the ease of explanation, the detailed description of saving device end (for example source electrode-body, gate trench etc.) hereinafter for the bottom source power MOSFET device.Be noted that Fig. 3 A is the flipchart of Fig. 2 A.As special case, Semiconductor substrate 21 can be processed by silicon, has a heavily doped contact layer 21a and a lightly doped drift layer 21b, and lightly doped drift layer 21b processes through epitaxial growth above heavily doped contact layer 21a.Drain metal layer 22 can be processed by titanium-nickel-Yin (TiNiAg).Patterned close source electrode 25 can be processed by Solder for Al-Cu Joint Welding (AICu) with the exposed device end gate electrode 56 of substrate terminal.Device end passivation 29 can be processed by oxide and/or polyimides.Patterned source electrode 55 can be processed by copper (Cu).Some relevant geometric parameter scopes are: thickness～1 of device end passivation 29 is micron to 10 microns; Thickness～5 of the bracing frame 55a that extends are micron to 20 microns.The bracing frame 55a that extends can the exposed device end gate electrode 56 of (in vertical direction) complete overlapping substrate terminal, even extends to exposed device end gate electrode 56 tops of substrate terminal, so that extra support to be provided.
Fig. 3 B representes that bottom source power MOSFET 35 saves technology encapsulation behind the wafer of active part.In this example,, pass straight-through substrate trenches 57, be connected on the exposed device end gate electrode 56 of substrate terminal through a conduction connecting line 33 (for example bonding wire).For a person skilled in the art, as long as TSTD can adapt to conduction connecting line and relevant encapsulation tool thereof with TSTW, just can replace conduction connecting line 33 with fish plate or solder projection pad (Solder bump).In this, the preferable aspect ratio of TSTW/TSTD is about 0.2 to 20.As typical embodiment, the scope of TSTW can be from 100 microns to 500 microns, and the scope of TSTD can be from 25 microns to 500 microns.Be also noted that; Straight-through if desired substrate trenches 57 is lined with insulating material; During with the different exposed surface of passivated semiconductor substrate 21 (referring to U. S. application 12/749696); At this moment, as the part of technology encapsulation behind the wafer, can fill straight-through substrate trenches 57 with the moulding batch mixing that surrounds bonding wire 33 and while passivated semiconductor substrate 21.
As an example, Fig. 3 C representes to contain the semiconductor packages 50 of bottom source MOS EFT 35 and lead frame 32.Bottom source power MOSFET 35 is installed on the lead frame part 32b, and lead frame part 32b is as lower bolster.Therefore, close source electrode 25 is connected on the lead frame part 32b, (for example through patterned source electrode 55 is installed on part 32b).Through the conduction connecting line 33a that is fit to arbitrarily, for example bonding wire, conductive strips, conductive clip etc. pass straight-through substrate trenches 57, can gate electrode (SEDGE 56) be connected on the lead frame part 32c.Through conduction connecting line 36 (also can comprise bonding wire, conductive strips, conductive clip etc.); Drain metal layer 22 also can be connected on the lead frame part 32a; If be necessary, other semiconductor wafer (not expressing among the figure) also can encapsulate with bottom source power MOSFET 35 together.After this, moulding batch mixing 37 (its profile is shown in dotted line among the figure) sealed package 50.Moulding batch mixing 37 also can be filled in the straight-through substrate trenches 57.
The preparation process of the bottom source power MOSFET device shown in Fig. 4 A to Fig. 4 H presentation graphs 3A.In Fig. 4 A; With traditional semiconductor wafer process; In interim Semiconductor substrate (ISS) 70 tops; Prepare MOSFET device region (FETDR) 71 together with patterned close source electrode 25, patterned gate electrode 26 and device end passivation 29, the thickness T ISS of interim Semiconductor substrate (ISS) 70 is enough big, can be compatible with traditional semiconductor wafer process.As a typical case, the scope of TISS can be between the 600-800 micron.Patterned close source electrode 25 is positioned near the patterned gate electrode 26, and patterned gate electrode 26 is through device end passivation 29 and its insulation, and device end passivation 29 has also covered the device end surfaces of patterned gate electrode 26.
In Fig. 4 B, above device end passivation 29, extend patterned close source electrode 25 together with the bracing frame 55a that extends, covered the device end surfaces of the patterned gate electrode 26 of device end passivation 29 belows basically up to it.Its realization can be through above the device end surfaces of patterned close source electrode 25, through mask (omitting, the to simplify view) plated metal of a band window here, till forming the bracing frame 55a that extends.As a typical case, can use thick copper (Cu) electroplating technology of band mask.In addition, thick Cu can carry out chemico-mechanical polishing (CMP) after electroplating, and makes the end face of plating smooth, forms a nickel-Jin (Ni-Au) layer or thin soldering-tin layer then, and is oxidized to prevent copper.
In Fig. 4 C, the back side of interim Semiconductor substrate (ISS) 70 is thinned to the Semiconductor substrate 21 that desired thickness is TSCS downwards.Then, substrate terminal (being the opposite of the device end) top in Semiconductor substrate 21 forms a substrate terminal drain metal layer 22.For example, through the back grinding technics, the thickness of TSCS can reduce between 50 microns-300 microns, and with titanium-nickel-Yin (Ti-Ni-Ag) preparation drain metal layer 22.
Fig. 4 D to Fig. 4 G representes to prepare straight-through substrate trenches 57, passes drain metal layer 22 and extends, and Semiconductor substrate 21 contains MOSFET device region (FETDR) 71 and exposes the exposed device end gate electrode 56 of substrate terminal.In Fig. 4 D, interim support substrates 72 of directed connection on the device end of device in preparation, and make its substrate (drain electrode) end upwards.For example, can use the interim support substrates 72 of preparation such as processing wafer of glass, silicon or broad sense.
In Fig. 4 E, above drain metal layer 22, use the trench mask 74 of a band window and form pattern, mask window 75 is equivalent to the prefabricated straight-through substrate trenches size 57a (X-Y plane) of straight-through substrate trenches 57.For example, the trench mask 74 of band window can be a kind of photoresist.
In Fig. 4 F, etch away that part of drain metal layer 22 in mask window 75, etching terminates in the interface place of drain metal layer 22-Semiconductor substrate 21.
In Fig. 4 G; That part of Semiconductor substrate 21 and device region 71 below the directed etch mask window 75; Etching terminates in the interface of the exposed device end gate electrode 56 of device region 71-substrate terminal and the interface place of device region 71-device end passivation 29, thereby processes straight-through substrate trenches 57.For example, can utilize some to have the plasma etching of the vertical furrow cell wall of tapering this moment.In typical embodiment, the scope of TSTD is 100 microns to 300 microns, and the scope of typical TSTW is 150 microns to 200 microns, and minimum is about 100 microns.
In Fig. 4 H, peel off the trench mask 74 of band window, unsticking and remove interim support substrates 72 is processed the bottom source power MOSFET with desired thickness TMOSFET then.
Fig. 5 representes the profile of another embodiment of bottom source power MOSFET part 33b of the present invention.At this moment, above drain metal layer 22, add the substrate terminal passivation (SSPV) 27 of a band window, thereby limit an exposed drain metal district 80, be used for when the wafer reprocessing encapsulates, smear and limit soldering tin material and flow into here.For example, can use preparation SSPV27 such as oxide, nitride or polyimides.In the preparation process, can be before drain metal layer 22 (Fig. 4 E) top be used the trench mask 74 of band window and is formed pattern, preparation SSPV 27.
Fig. 6 has represented to add the profile of another embodiment of the bottom source power MOSFET part 34b of device end carrier (DSC) 40.Bottom source power MOSFET part 34b is except source electrode 55 that does not have extension and the bracing frame 55a that extends; And adding on its device end outside the device end carrier of processing by carrier material 40a (DSC) 40 (for example through insulation intermediary's adhesive layer (ILBL) 60 carrier material 40a is made up or is bonded on the device end), other are all basic identical with the device shown in Fig. 3 A.More details one skilled in the art should appreciate that following characteristics please with reference to U. S. application 12/749,696:
Device end carrier (DSC) 40 has a plurality of patterned back side carrier metal 41a, 41b, 41c; Contact 25, one patterned front carrier metal pad 42a of patterned source electrode and a plurality of straight-through carrier conductive through hole 43a, 43b, 43c is connected to patterned back side carrier metal 41a, 41b, 41c on the patterned front carrier metal pad 42a respectively.
The thickness T DSC of device end carrier 40 is enough big; Can sufficient structural rigidity be provided for semiconductor device; Substrate is close to the thickness T SCS that disappears and produces a very low back resistance substrate, and straight-through carrier conductive through hole 43a, 43b, 43c produce very low front contact resistance to the patterned close source electrode 25 of contact.
Another not too outstanding feature be; Because when the wafer-process of bottom source power MOSFET part 34b; Device end passivation 29 need not cover the exposed device end gate electrode 56 of substrate terminal, so the exposed exposed device end gate electrode 56 of substrate terminal in top has been simplified and mounted relevant wafer scale probing test before the device end carrier 40.In some typical more embodiment, the scope of TDCS is about 100 microns to 400 microns.The scope of TSCS is about 5 microns to 100 microns, and there is not the danger of puncture in the rigidity in view of device end carrier 40, and TSCS also can be less than 50 microns.
Fig. 7 representation class is similar to the profile of another embodiment of the bottom source power MOSFET of Fig. 6; But wherein device end carrier 40 is replaced by moulding batch mixing 90; Moulding batch mixing 90 surrounds solder projection pad 95, through source electrode 55a, is connected on the close source electrode 25.Also can select, on the exposed device end gate electrode 56 of substrate terminal, form gate electrode 55b,, but not connect from source electrode 55a or from solder projection pad 95 as the byproduct of preparation source electrode 55a.The source electrode 55a that is added can help being connected to smoothly on the soldering tin material of solder projection pad 95.
Above-mentioned explanation comprises many specific details, and these details are only explained as the existing preferred embodiment of the present invention is provided, and should not regard the limitation to the scope of the invention as.For example, add the power MOSFET device that has trench-gate, the principle of bottom source power MOSFET of the present invention is applicable to that also lateral direction bilateral diffusion MOS FET (LDMOS) and vertical double-diffused MOS FET (VDMOS) wait other type of device.Again for example, principle of the present invention also is applicable to the structure and the preparation of micro electronic mechanical system (MEMS).More than explanation and accompanying drawing have provided various typical embodiment with reference to concrete structure.Should be obvious for those skilled in the art, the present invention also can be used for other concrete form, and above-mentioned various embodiment just can be suitable for other concrete application through easily revising.In view of this patent file, scope of the present invention should not limited above-mentioned concrete exemplary embodiments, and should be limited following claims.In content of claims and any and all corrections in the full scope of equivalents thereof, all should belong in true intention of the present invention and the scope.
Claims (23)
1. one kind has the semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal, it is characterized in that this semiconductor device comprises:
A Semiconductor substrate (SCS), the semiconductor device region (SDR) that has the substrate terminal on device end, device end opposite and be positioned at the device end;
A plurality of device termination electrodes (DSE) are formed on device end top, and contact with semiconductor device region, are used for the operation of semiconductor device; And
At least one straight-through substrate trenches (TST); Passing Semiconductor substrate extends; Touch the device termination electrode; Thereby described device termination electrode is become the device termination electrode that exposes in substrate terminal, thereby can pass the straight-through interconnected device termination electrode that exposes in substrate terminal of substrate trenches through the conduction connecting line.
2. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 1 is characterized in that this semiconductor device is a vertical semiconductor devices.
3. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 1 is characterized in that, also comprises one and the contacted substrate terminal electrode of substrate terminal (SSE).
4. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 1 is characterized in that, the conduction connecting line is a bonding wire, joint intermediate plate, conductive strips or solder projection pad.
5. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 1 is characterized in that, also comprises the device end passivation (DSPV) that is positioned at the device end at the device termination electrode of substrate terminal corresponding to exposing.
6. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 1 is characterized in that at least one exposes the device end passivation (DSPV) at the device termination electrode of substrate terminal also to comprise a correspondence, and
Except described at least one expose the device termination electrode of substrate terminal; In described device termination electrode, also have a preset electrode to have the bracing frame of an extension; Be deposited in the below separate through described device end passivation and described at least one device termination electrode that exposes in substrate terminal simultaneously so that when the wafer reprocessing encapsulates to described at least one expose the support on the device end-electrode structure of substrate terminal.
7. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 6; It is characterized in that; The bracing frame size of this extension is incident upon the size on the main semiconductor substrate plane, has encased the said corresponding projected dimension of device termination electrode of exposing in substrate terminal.
8. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 1; It is characterized in that; Straight-through substrate trenches is TSTW along the width of main semiconductor substrate plane, is TSTD perpendicular to the degree of depth of main semiconductor substrate plane, and aspect ratio TSTW/TSTD is 0.2 to 20.
9. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 8 is characterized in that TSTW is 100 microns to 500 microns, and TSTD is 25 microns to 500 microns.
10. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 1 is characterized in that, also comprises one and the contacted substrate terminal drain electrode of Semiconductor substrate, and correspondingly:
Semiconductor device region has a source area, a gate regions and a body; And
The device termination electrode has:
The source electrode of contact source area and a body, and have the bracing frame of extension; And
The device termination electrode that exposes that contacts gate regions in substrate terminal,
Thereby making this semiconductor device is a kind of bottom source metal oxide semiconductor field effect tube (MOSFET).
11. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 10 is characterized in that source electrode also comprises the bracing frame of an extension, is supporting the device termination electrode that exposes in substrate terminal.
12. the described semiconductor device that exposes at the device termination electrode (SEDE) of substrate terminal that has of claim 1 is characterized in that, also is included in its device end, through the bonded device end carrier (DSC) of insulation intermediary's knitting layer (ILBL), wherein:
Semiconductor substrate has a substrate and is close to the thickness T SCS that disappears, and this thickness can be compared with the thickness T SDR of semiconductor device region mutually;
Device end carrier has patterned back side carrier metal; Contact a device termination electrode; This device termination electrode is not a device termination electrode that exposes in substrate terminal, and a patterned front carrier metal pad and a plurality of straight-through carrier conductive through hole are connected to back side carrier metal on the carrier metal pad of front respectively; And
The thickness T DSC of device end carrier is large enough to
Device end carrier can provide sufficient structural rigidity for semiconductor device; Substrate is close to the thickness T SCS that disappears makes the device termination electrode of contact produce very low back resistance substrate, and straight-through carrier conductive through hole makes the device termination electrode of contact produce very low front contact resistance.
13. one kind is used to prepare and has at least one and expose the method at the device termination electrode (SEDE) of substrate terminal,, it is characterized in that this method comprises so that interconnected with external environment condition:
A) a preparation Semiconductor substrate (SCS), and in its device end, prepare a semiconductor device region (SDR);
B) on the device end, prepare a plurality of device termination electrodes (DSE), and contact with semiconductor device region, be used for the operation of semiconductor device; And
C) prepare at least one straight-through substrate trenches (TST), extend through Semiconductor substrate, touch a predetermined device termination electrode, thus with described device termination electrode become described at least one expose device termination electrode in substrate terminal.
14. the described method of claim 13 is characterized in that, the straight-through substrate trenches of preparation comprises:
Directed etching is passed in that part of Semiconductor substrate and the semiconductor device region in the predetermined mask window, and terminates in semiconductor device region-expose the interface at the device termination electrode of substrate terminal, thereby processes straight-through substrate trenches.
15. the described method of claim 13 is characterized in that, also comprises, at step b) and c) between:
B1) provide a bracing frame that has horizontal expansion to extend a device termination electrode; Up to cover described at least one expose device end surfaces at the device termination electrode of substrate terminal; This device termination electrode is not described predetermined device termination electrode; Provide device end passivation (DSPV) at the bracing frame that extends with expose between the device termination electrode in substrate terminal, and they are separated.
16. the described method of claim 15 is characterized in that, extends described device termination electrode and comprises the mask through the band window, plated metal above the device end surfaces of described device termination electrode is till forming the bracing frame that extends.
17. a semiconductor device is characterized in that having:
A semiconductor wafer of processing by semi-conducting material, and have first limit and second limit;
Conduction first pad that is positioned on semiconductor wafer first limit;
Groove below conduction first pad is wherein removed semi-conducting material, and through described groove, first pad exposes out from second limit of semiconductor wafer; And
The connecting line of a conduction passes described groove from described second limit, is connected on described conduction first pad.
18. the described semiconductor device of claim 17 is characterized in that, the connecting line of conduction is bonding wire, conductive clip or conductive strips or solder projection pad.
19. the described semiconductor device of claim 17 is characterized in that, conduction connecting line part at least is positioned at described groove, and conduction connecting line first end is connected on first pad, and conduction connecting line second end is outside the above groove of semiconductor wafer second limit.
20. the described semiconductor device of claim 17 is characterized in that, described semiconductor device is vertical field-effect pipe (FET), and described first pad is gate pad.
21. the described semiconductor device of claim 20 is characterized in that, the position at gate pad place part is at least surrounded by the active area of FET.
22. the described semiconductor device of claim 20 is characterized in that, also comprises a supporting construction of gate pad top.
23. the described semiconductor device of claim 20 is characterized in that, the conduction connecting line is bonding wire, conductive clip, conductive strips or solder projection pad.
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| CN113394291A (en) * | 2021-04-29 | 2021-09-14 | 电子科技大学 | Lateral power semiconductor device |
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Effective date of registration: 20200518 Address after: Ontario, Canada Patentee after: World semiconductor International Limited Partnership Address before: 475 oakmead Avenue, Sunnyvale, California 94085, USA Patentee before: Alpha and Omega Semiconductor Inc. |