CN102867761A - Defect scanning method and system capable of realizing dynamic complementation of wafers - Google Patents
Defect scanning method and system capable of realizing dynamic complementation of wafers Download PDFInfo
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- CN102867761A CN102867761A CN2012103434465A CN201210343446A CN102867761A CN 102867761 A CN102867761 A CN 102867761A CN 2012103434465 A CN2012103434465 A CN 2012103434465A CN 201210343446 A CN201210343446 A CN 201210343446A CN 102867761 A CN102867761 A CN 102867761A
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Abstract
The invention discloses a defect scanning method and system capable of realizing dynamic complementation of wafers, belonging to the technical field of wafer selection defect scanning. The defect scanning method comprises the following steps: a, establishing a defect scanning site; b, selecting fixed two wafers in a first site-passing product, and performing defect scanning on neighboring two wafers of the fixed two wafers; c, selecting fixed two wafers in a second site-passing product, and performing defect scanning on neighboring two wafers which are not scanned before; d, selecting fixed two wafers in a third site-passing product, and performing defect scanning on neighboring two wafers which are not scanned before in the previous two steps; and e, scanning all the other site-passing products by using the above method until all wafers in the positions of clamping grooves of a wafer box are scanned. The technical scheme has the following beneficial effects: the situation that a defect is caused can be found in time, the quantity of affected products can be effectively reduced, the yield can be increased, and the cost can be lowered.
Description
Technical field
The present invention relates to wafer chip select Defect Scanning technical field, relate in particular to a kind of defects scanning method and system of dynamic complementation wafer.
Background technology
Along with the accelerated development of semiconductor technology and production, the wafer percent of pass of process work bench is more and more faster.In order to reduce the cycle time of production, the sampling of Defect Scanning and chip select also become and more and more have challenge, when effectively the chip select system can not affect the product output rate, quick and precisely omit the wafer that notes abnormalities, in time check the unusual of process work bench, reduce the number of influenced product.So an effective Defect Scanning wafer chip select rule seems particularly important.
Process work bench is varied in wafer factory, and different operation principles is arranged.When some part of process work bench, when unusual such as appearance such as certain reaction chamber, certain mechanical arms, can continue specific one or several position wafer of wafer cassette draw-in groove in the product is produced defective.If the Defect Scanning website is to fixing wafer chip select rule (as shown in Figure 1), namely fixing the 1st, 2,23,24 wafer of selecting are carried out Defect Scanning, and do not choose the wafer of this specific draw-in groove to scan, and just are difficult in time find the unusual of process work bench.Often continued for a long time when by the time finding, had influence on the yield of large-tonnage product.
Summary of the invention
According to the defective that exists in the prior art, a kind of defects scanning method of dynamic complementation wafer and the technical scheme of system now are provided, specific as follows:
A kind of defects scanning method of dynamic complementation wafer is applicable to the chip select Defect Scanning of dynamic complementation wafer, and wherein, step comprises:
Step a sets up the Defect Scanning website, and described Defect Scanning website is used for the dynamic complementation wafer is carried out Defect Scanning;
Step b chooses by two wafer of fixing in first product that misses the stop of described Defect Scanning website, and chooses described vicinity two wafer of fixing two wafer, and above-mentioned four wafer are carried out Defect Scanning;
Step c chooses by described in second product that misses the stop of described Defect Scanning website and fixes two wafer, and not scanned vicinity two wafer before choosing, and above-mentioned four wafer are carried out Defect Scanning;
Steps d is chosen by described in the 3rd product that misses the stop of described Defect Scanning website and is fixed two wafer, and twice equal not scanned vicinity two wafer before choosing, and above-mentioned four wafer are carried out Defect Scanning;
Step e adopts said method to scan all the other products that miss the stop, until the wafer of all wafer cassette draw-in groove positions all is scanned.
Preferably, the defects scanning method of this dynamic complementation wafer wherein, after finishing described step e, returns described step b.
Preferably, the defects scanning method of this dynamic complementation wafer, wherein, described defects scanning method was finished within a default time cycle.
Preferably, the defects scanning method of this dynamic complementation wafer, wherein, the wafer of selecting to be positioned at the fixed card slot position carries out Defect Scanning.
Preferably, the defects scanning method of this dynamic complementation wafer, wherein, the wafer of selecting to be positioned at on-fixed draw-in groove position carries out Defect Scanning.
A kind of Defect Scanning system of dynamic complementation wafer wherein, adopts the defects scan method.
The beneficial effect of technique scheme is: make the Defect Scanning website to the wafer of different wafer cassette draw-in grooves position defectiveness scanning result all within a time cycle, in time find to cause the situation of defective, can effectively reduce the quantity of influenced product, promote yield, and reduce cost.
Description of drawings
Fig. 1 is the schematic diagram of defects scanning method in the prior art;
Fig. 2 is the schematic diagram of embodiment of the defects scanning method of a kind of dynamic complementation wafer of the present invention;
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, but not as limiting to the invention.
Add the defects scanning method of novel dynamic complementation wafer in present Defect Scanning chip select system, the wafer that this defects scanning method scans includes but not limited to select the wafer of fixed card slot position.As shown in Figure 2, at first, scanning defective website is set, first product that misses the stop of this website is fixedly chosen two wafer 1 and 24, and choose vicinity two wafer 2 and 23 of wafer 1 and 24, above-mentioned four wafer are carried out Defect Scanning;
Secondly, second product that misses the stop of this website fixedly chosen wafer 1 and 24, and choose vicinity two wafer 3 and 22 that were not scanned, above-mentioned four wafer are carried out Defect Scanning;
Again, the 3rd product that misses the stop of this website fixedly chosen wafer 1 and 24, and choose vicinity two wafer 4 and 21 that were not scanned, above-mentioned four wafer are carried out Defect Scanning;
By that analogy, all the other wafers are carried out the scanning of same dynamic defect, until after the wafer of all wafer cassette draw-in groove positions all was scanned, then accent began dynamic chip select, namely reselects and fixes two wafer, repeats above step.
In another specific embodiment of the present invention, a process work bench first has six reaction chambers, and wherein No. six reaction chamber is unusual; Another process work bench second has four reaction chambers, wherein second reaction chamber has unusually, specified defect can appear in the wafer of successively crossing two reaction chambers of six reaction chambers of first board and second board, be that the wafer cassette slot is set to 6 and 18 wafer and defective can occur, then use to comprise that the Defect Scanning system of defects scan method carries out Defect Scanning, can when the 5th this Defect Scanning website of product process, detect the problems referred to above.
Comprise a timing device in the Defect Scanning system of this use defects scan method, this timing device can be used for setting a default time cycle, within this default time cycle, the Defect Scanning system finishes the Defect Scanning work of above-mentioned wafer, and to wafer defectiveness scanning result all.
The above only is preferred embodiment of the present invention; be not so restriction embodiments of the present invention and protection range; to those skilled in the art; should recognize that being equal to that all utilizations specification of the present invention and diagramatic content done replace and the resulting scheme of apparent variation, all should be included in protection scope of the present invention.
Claims (6)
1. the defects scanning method of a dynamic complementation wafer is applicable to the chip select Defect Scanning of dynamic complementation wafer, it is characterized in that, step comprises:
Step a sets up the Defect Scanning website, and described Defect Scanning website is used for the dynamic complementation wafer is carried out Defect Scanning;
Step b chooses by two wafer of fixing in first product that misses the stop of described Defect Scanning website, and chooses described vicinity two wafer of fixing two wafer, and above-mentioned four wafer are carried out Defect Scanning;
Step c chooses by described in second product that misses the stop of described Defect Scanning website and fixes two wafer, and not scanned vicinity two wafer before choosing, and above-mentioned four wafer are carried out Defect Scanning;
Steps d is chosen by described in the 3rd product that misses the stop of described Defect Scanning website and is fixed two wafer, and twice equal not scanned vicinity two wafer before choosing, and above-mentioned four wafer are carried out Defect Scanning;
Step e adopts said method to scan all the other products that miss the stop, until the wafer of all wafer cassette draw-in groove positions all is scanned.
2. the defects scanning method of dynamic complementation wafer as claimed in claim 1 is characterized in that, after finishing described step e, returns described step b.
3. the defects scanning method of dynamic complementation wafer as claimed in claim 1 is characterized in that, described defects scanning method was finished within a default time cycle.
4. the defects scanning method of dynamic complementation wafer as claimed in claim 1 is characterized in that, the wafer of selecting to be positioned at the fixed card slot position carries out Defect Scanning.
5. the defects scanning method of dynamic complementation wafer as claimed in claim 4 is characterized in that, the wafer of selecting to be positioned at on-fixed draw-in groove position carries out Defect Scanning.
6. the Defect Scanning system of a dynamic complementation wafer is characterized in that, adopts the defects scanning method such as the described dynamic complementation wafer of any one among the claim 1-5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210343446.5A CN102867761B (en) | 2012-09-17 | 2012-09-17 | Defect scanning method and system capable of realizing dynamic complementation of wafers |
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| CN201210343446.5A CN102867761B (en) | 2012-09-17 | 2012-09-17 | Defect scanning method and system capable of realizing dynamic complementation of wafers |
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| CN102867761A true CN102867761A (en) | 2013-01-09 |
| CN102867761B CN102867761B (en) | 2014-12-10 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4618938A (en) * | 1984-02-22 | 1986-10-21 | Kla Instruments Corporation | Method and apparatus for automatic wafer inspection |
| US5874309A (en) * | 1996-10-16 | 1999-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for monitoring metal corrosion on integrated circuit wafers |
| CN1219757A (en) * | 1997-12-08 | 1999-06-16 | 三菱电机株式会社 | Semiconductor wafer processing apparatus and method of controlling the same |
| KR20070074987A (en) * | 2006-01-11 | 2007-07-18 | 삼성전자주식회사 | Wafer-to-wafer defect inspection system |
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2012
- 2012-09-17 CN CN201210343446.5A patent/CN102867761B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4618938A (en) * | 1984-02-22 | 1986-10-21 | Kla Instruments Corporation | Method and apparatus for automatic wafer inspection |
| US5874309A (en) * | 1996-10-16 | 1999-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for monitoring metal corrosion on integrated circuit wafers |
| CN1219757A (en) * | 1997-12-08 | 1999-06-16 | 三菱电机株式会社 | Semiconductor wafer processing apparatus and method of controlling the same |
| KR20070074987A (en) * | 2006-01-11 | 2007-07-18 | 삼성전자주식회사 | Wafer-to-wafer defect inspection system |
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