CN102881335A

CN102881335A - Strain test analysis system for double date rate (DDR) memory bank

Info

Publication number: CN102881335A
Application number: CN2011101989243A
Authority: CN
Inventors: 施杰; 刘椿峰
Original assignee: Individual
Current assignee: Individual
Priority date: 2011-07-16
Filing date: 2011-07-16
Publication date: 2013-01-16

Abstract

The invention discloses a strain test analysis system for a double date rate (DDR) memory bank. The strain test analysis system comprises a sensor, a programmable control signal amplifier and an analog filter, wherein a controllable bridge supply circuit, the sensor, the programmable control signal amplifier, the analog filter and a 16-bit analog-to-digital converter are sequentially connected in series with one another to form a signal front-end processing part; a subtractor and a 16-bit digital-to-analog converter are connected in series with each other and then are connected in parallel with a comparator to form a balance circuit; the 16-bit analog-to-digital converter is divided into two parallel branches, namely a digital signal processing (DSP) branch and a DDR memory branch; the other ends of the two parallel branches, namely the DSP branch and the DDR memory branch, are connected with a universal asynchronous receiver/transmitter (UART) to universal serial bus (USB) 12; and the UART to USB 12, a USB data transmitter and computer signal test analysis software are sequentially connected in series with one another. By a DDR memory, the cache capacity can be greatly improved, and the storage rate can be guaranteed; and data storage at high frequency can be realized.

Description

The strain testing analytic system of DDR memory bar

Technical field

The present invention relates to a kind of strain testing analytic system of DDR memory bar.

Background technology: the DDR full name is DDR SDRAM (Double Date Rate SDRAM, Double Data Rate SDRAM).DDR SDRAM is proposed in 1996 by Samsung, the memory standards of being concluded by NEC, Mitsubishi, Fujitsu, Toshiba, Hitachi, Texas Instrument, Samsung and eight companies' agreements such as modern, and obtained the support of the main chip group manufacturers such as AMD, VIA and SiS.It is the upgraded version of SDRAM, therefore is also referred to as " SDRAM II ".Its most important change is in interface data transmission, and he all can carry out the data processing at the rising edge of clock signal with negative edge, makes data transmission rate reach 2 times of SDR (Single Data Rate) SDRAM.Then identical with SDRAM with control signal as for addressing, only transmit at rising edge clock.

DDR is present main flow internal memory standard, and the main product of each large chip group manufacturer all is to support its.Up-to-date memory bar is DDR3 now, and DDR3 is the new generation product after DDR2 and DDR memory techniques more early, and this product will be broken the limitation of kilo-mega cycles per second speed, and memory speed is risen to a unprecedented level.The characteristics of DDR3 internal memory are faster speed, higher data bandwidth, lower operating voltage and power consumption, and better heat dispersion.The purpose of DDR3 internal memory design is need to support the next generation's four core processors of higher data bandwidth, makes its performance outstanding.The DDR3 memory modules is divided into 1066MHz, 1333MHz and three kinds of frequencies of 1600MHz (message transmission rate), wherein 1066MHz and the 1333MHz DDR3 comprehensively listing in 2007, and 1600MHz DDR3 is formal the release in 2008.

Along with expanding economy, for changing very fast transient signal or high-frequency signal, such as vehicle impact testing, engineering explosion test etc., the number of times of testing is more and more, and the accurate test of these impact signals plays vital effect for the test of a lot of structure members.Such as vehicle impact testing, engineering explosion test etc.; Because data volume is very large in a flash, and the time often is exactly in a flash, because the restriction of USB transfer rate, data have little time to be transferred to computer by USB interface; At this moment in order to guarantee sample rate and precision, often instrument internal built-in internal memory RAM, the data that will gather moment are temporarily deposited in first among the internal memory RAM, wait and data are derived after gather finishing, existing built-in buffer memory generally only has about 10MB, can't satisfy the data storage under the high-frequency.

Summary of the invention;

Purpose of the present invention is exactly the strain testing analytic system that a kind of DDR memory bar will be provided, and it can overcome present USB interface transmission, the existing problem of internal memory RAM.The object of the present invention is achieved like this, the strain testing analytic system of DDR memory bar, comprise that sensor, program control signal amplifier, analog filter form, it is characterized in that: controlled bridge circuit, sensor, program control signal amplifier, analog filter, 16 analog-to-digital converters of supplying are sequentially connected, and form the signal front-end processing part; Subtracter, 16 bit digital to analog converter are connected rear in parallel with comparer, the Compositional balance circuit; 16 analog-to-digital converters divide the processing of two parallel branch DSP data, DDR internal memory, and two parallel branch DSP data are processed, the other end and the UART of DDR internal memory turn USB12 and link to each other; Described UART turns the transmission of USB, usb data, Computer signal test analysis software is sequentially connected; Computer signal test analysis software, usb data transmission, UART turn USB, singlechip controller, controlled for the series connection of bridge circuit order; Program control signal amplifier, subtracter are connected with 16 bit digital to analog converter, comparer, 16 analog-to-digital converters, DSP data are processed, the DDR memory bars are parallel to single-chip microcomputer.The present invention is because the now develop rapidly of DDR memory bar technology, and general DDR memory bar capacity has developed into 2G, 4G even higher, and fully enough storage data of collection in a flash can significantly promote buffer memory capacity and can guarantee memory rate by the DDR internal memory.

Description of drawings:

Fig. 1 is structural representation of the present invention;

1. controlled for bridge voltage, 2. sensor, 3. program control signal amplifier, 4. analog filter, 5. subtracter, 6.16 bit digital are to analog converter, 7. comparer, 8.16 the position analog-to-digital converter, the 9.DSP data are processed, 10. singlechip controller, 11.DDR memory bar, 12.UART turn USB, 13.USB data transmission, 14. Computer signal test analysis softwares.

Embodiment: the invention will be further described below in conjunction with accompanying drawing;

The strain testing analytic system of DDR memory bar, comprise that sensor 2, program control signal amplifier 3, analog filter 4 form, it is characterized in that: controlled for bridge voltage 1, sensor 2, program control signal amplifier 3, analog filter 4,16 analog-to-digital converter 8 order series connection, form the signal front-end processing part; Subtracter 5,16 bit digital to analog converter 6 are connected rear in parallel with comparer 7, the Compositional balance circuit; The other end and the UART of the two parallel branch DSP data processing 9 in 8 minutes of 16 analog-to-digital converters, DDR internal memory 11, two parallel branch DSP data processing 9, DDR memory bar 11 turn USB12 and link to each other; Described UART turns USB12, usb data transmission 13, the 14 order series connection of Computer signal test analysis software; Computer signal test analysis software 14, usb data transmission 13, UART turn USB12, singlechip controller 10, controlled for bridge circuit 1 order series connection; Program control signal amplifier 3, subtracter 5 are connected with 16 bit digital to analog converter 6, comparer 7,16 analog-to-digital converters 8, DSP data process 9, DDR memory bars 11 are parallel to single-chip microcomputer 10.During implementation, sensor power supply, instrument internal voltage signal Balance Treatment, signal acquisition process and storage.At first the signal testing analysis software turns USB by UART and gives an order to singlechip controller, and singlechip controller communicates for the bridge voltage circuit with controlled, and controlled confession bridge voltage circuit output voltage is to sensor, for sensor provides operating voltage.Simultaneously, the signal testing analysis software turns USB by UART and sends instruction to singlechip controller, singlechip controller sends instruction for 16 bit digital to analog converter, make 16 bit digital to analog converter output aanalogvoltage enter subtracter, carry out computing, after comparing through comparer, transmission is ceased and desisted order to singlechip controller again, built-in voltage in the circuit is removed, avoided having influence on measuring-signal.Sensor output signal is to the program control signal amplifier, signal enters analog filter through after amplifying, the elimination irrelevant signal again through 16 analog-to-digital converters, converts useful signal to digital signal, signal is divided into two-way, one the road to the processing of DSP data, and store to the DDR memory bar on another road, and the signal after the DSP digital processing carries out UART and turns USB, transfer to Computer signal test analysis software by usb data, be presented on the acquisition software; Be stored in the data on the DDR memory bar, after collection is finished, carry out UART and turn USB, transfer on the Computer signal test analysis software by usb data.

Claims

1.DDR the strain testing analytic system of memory bar, comprise that sensor (2), program control signal amplifier (3), analog filter (4) form, it is characterized in that: controlled for bridge circuit (1), sensor (2), program control signal amplifier (3), analog filter (4), the series connection of 16 analog-to-digital converters (8) order, form the signal front-end processing part; Subtracter (5), 16 bit digital to analog converter (6) are connected rear in parallel with comparer (7), the Compositional balance circuit; 16 analog-to-digital converters (8) minute two parallel branch DSP data are processed (9), DDR memory bar (11), and the other end that two parallel branch DSP data are processed (9), DDR memory bar (11) turns USB(12 with UART) link to each other; Described UART turns USB(12), usb data transmission (13), the series connection of Computer signal test analysis software (14) order; Computer signal test analysis software (14), usb data transmission (13), UART turn USB(12), singlechip controller (10), controlled for the series connection of bridge circuit (1) order; Program control signal amplifier (3), subtracter (5) are connected with 16 bit digital to analog converter (6), comparer (7), 16 analog-to-digital converters (8), DSP data are processed (9), DDR memory bar (11) is parallel to single-chip microcomputer (10).