CN102890232A - Parallel testing method - Google Patents
Parallel testing method Download PDFInfo
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- CN102890232A CN102890232A CN2011102080346A CN201110208034A CN102890232A CN 102890232 A CN102890232 A CN 102890232A CN 2011102080346 A CN2011102080346 A CN 2011102080346A CN 201110208034 A CN201110208034 A CN 201110208034A CN 102890232 A CN102890232 A CN 102890232A
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Abstract
The invention provides a parallel testing method, which comprises the following steps that: a testing machine is provided, wherein the testing machine contains a driving channel and a power channel, and the driving channel contains a first group and a second group; a plurality of chips to be tested are provided, wherein each chip to be tested contains a plurality of signal pins and at least a power pin; the signal pins of each chip to be tested are connected to the driving channel located at the first group; the power pins of each chip to be tested are respectively parallelly connected to the driving channel located at the second group; and the signal pins of each chip to be tested receives driving signals from the connected driving channel located at the first group, and the power pins of each chip to be tested respectively receive power signals with mutually exclusive sources from the parallelly connected driving channel located at the second group so as to carry out parallel testing on the chips to be tested.
Description
Technical field
The invention relates to a kind of electronic device test method, and particularly relevant for a kind of parallel test method.
Background technology
It is the final step in the chip processing procedure that circuit point is surveyed (circuit probing).Yet a large amount of chips often needs to expend many times to be tested, if on single board simultaneously to many chip testings, will save many testing costs and time cost.In order to reach parallel testing, usually share the power supply that tester table provides by several chips to be measured, under the passage of tester table power supply supply and few situation, to reach the purpose of parallel testing in the past.Yet such design, when one of them produces short circuit at these chips to be measured, the impact of large electric current will make the chip to be measured of power supply shared with it also and then damage.Moreover, in the test procedure of part to the power pin of chip to be measured, the relation that also will share because of power supply, and can't one chip be measured, and indistinguishable is that whichever causes when producing unusual condition.
Therefore, how designing a new parallel test method, to overcome above-mentioned problem, is an industry problem demanding prompt solution for this reason.
Summary of the invention
The object of the present invention is to provide a kind of parallel test method, to overcome above-mentioned problem.
Therefore, an aspect of of the present present invention is that a kind of parallel test method is being provided, comprise the following step: tester table is provided, and wherein tester table comprises a plurality of driving passages (driver channel) and a plurality of power channel, wherein drives passage and comprises the first group and the second group; A plurality of chips to be measured are provided, and wherein each chip to be measured comprises a plurality of signal pins and at least one power pin; Make the signal pin of each chip to be measured be connected in the driving passage that is positioned at the first group; The power pin that makes each chip to be measured respectively parallel be connected to be positioned at the second group the driving passage one of them; And make the signal pin of chip to be measured receive the driving signal from the driving passage that is positioned at the first group that links to each other, and the power pin that makes chip to be measured is from the parallel connected driving passage that is positioned at the second group power supply signal of receipt source inequality respectively, so that chip to be measured is carried out parallel testing.
According to one embodiment of the invention, wherein the signal pin of each a chip to be measured identical person wherein share be positioned at the second group the driving passage one of them.
According to another embodiment of the present invention, wherein each signal pin of each chip to be measured parallel be connected in be positioned at the second group the driving passage one of them.
According to further embodiment of this invention, wherein tester table also comprises a plurality of IO channel, and each chip to be measured comprises at least one input and output pin.Parallel test method also comprises the following step: make each input and output pin of each chip to be measured parallel be connected in IO channel one of them; And make each input and output pin of chip to be measured receive respectively input/output signal from parallel connected IO channel, so that chip to be measured is carried out parallel testing.
According to yet another embodiment of the invention, wherein the signal pin comprises write protection pin, chip selection pin to be measured, frequency pin, keeps pin and program pump (program pump) voltage pin.
According to the embodiment that the present invention also has, wherein parallel testing comprises the standby current test.Standby current is tested the standby current in order to the power pin of measuring each chip to be measured.
According to the embodiment that the present invention has again, wherein parallel testing is that circuit point is surveyed (circuit probing) test.Parallel testing is that DC power supply circuit point is surveyed or AC power circuit point is surveyed.
Application the invention has the advantages that by power pin is connected with the driving passage of tester table separately abreast, except the power channel that can avoid tester table is not enough to supply the chip to be measured of massive parallel test, also can increase the accuracy of test, and reach easily above-mentioned purpose.
Description of drawings
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, appended the description of the drawings is as follows:
Fig. 1 is in one embodiment of the invention, the process flow diagram of parallel test method;
Fig. 2 is in one embodiment of the invention, the schematic diagram that tester table and several chips to be measured are connected; And
Fig. 3 is in one embodiment of the invention, the channel attached schematic diagram of various dissimilar pins and board to be measured.
[primary clustering symbol description]
Embodiment
Please refer to Fig. 1.Fig. 1 is in one embodiment of the invention, the process flow diagram of parallel test method.Please be simultaneously with reference to Fig. 2.Fig. 2 is in one embodiment of the invention, the schematic diagram that tester table 20 and several chips 22 to be measured are connected.Parallel test method comprises the following step (should be appreciated that, mentioned step except chatting especially bright its order person, all can be adjusted its front and back order according to actual needs, even can carry out simultaneously simultaneously or partly in the present embodiment).
In step 101, provide the tester table 20 and several chips 22 to be measured that illustrate such as Fig. 2.Chip 22 to be measured for wafer through section, grinding, exposure, development, cloth plant, the finished product of the processing procedure such as etching after finishing.Yet chip 22 to be measured is still needed through some tests, can guarantee the normal of its running, finishes complete manufacturing and testing process.Wherein chip 22 to be measured is to link up and running with other electronic package, comprises a plurality of signal pins 220 and power pin 222.Signal pin 220 can comprise such as write protection pin, chip selection pin to be measured, frequency pin, keep pin and program pump voltage pin etc., receiving the signal from external module, or the signals in the chip 22 to be measured is sent out.222 of power pins are in order to receive power supply, so that whole chip to be measured 22 is operated.Should be noted, in Fig. 2, each chip 22 to be measured only shows a signal pin 220 and power pin 222, in fact in different embodiment, the signal pin 220 of each chip 22 to be measured and the number of power pin 222 can be different according to design requirement, and the number that does not illustrate by Fig. 2 is limit.
Tester table 20 comprises a plurality of driving passages 200 and a plurality of power channel 202.The driving passage 200 of tester table 20 comprises the driving passage 200 of the first group and the driving passage 200 of the second group.Wherein, the first group illustrates with solid line, and the second group illustrates with dotted line.In general, drive passage 200 when carrying out test procedure, can transmit driving signal (not illustrating) and give signal pin 220, power channel 202 then can transmit power supply signal (not illustrating) to the power pin 222 of chip 22 to be measured.
Yet a large amount of chips often needs to expend many times to be tested, if on single board simultaneously to many chip testings, will save many testing costs and time cost.In order to reach parallel testing, usually share the power supplys that tester table 20 provides by several chips to be measured 22, under the passage of tester table 20 power supply supplies and few situation, to reach the purpose of parallel testing in the past.Yet such design, when these chip 22 one of them generation short circuits to be measured, the impact of large electric current will make the chip to be measured 22 of power supply shared with it also and then damage.Moreover, in the test procedure of part to the power pin 222 of chip 22 to be measured, the relation that also will share because of power supply, and can't one chip be measured, and indistinguishable is that whichever causes when producing unusual condition.
Therefore, in step 102, the driving passage 200 that the signal pin 220 of each chip 22 to be measured is connected in be positioned at the first group (part that illustrates with solid line).Then in step 103, the power pin 222 that makes each chip 22 to be measured respectively parallel be connected to be positioned at the second group driving passage 220 one of them.Meaning namely, the signal pin 220 of each chip 22 to be measured is to be connected with the driving passage 200 of the first group, the power pin 222 of each chip 22 to be measured then will be respectively be connected from different driving passage 220, and becomes parallel and mutual connected mode independently.
Should be noted, difference in response to signal pin 220, its mode that is connected with the driving passage 200 of the first group also may be different, for instance, the identical signal pin 220 of 22 parts of each chip to be measured, such as the frequency pin of each chip 22 to be measured, can be connected in one of them identical driving passage 220 of the first group, share the purpose that drives number of active lanes to save to reach.And the identical signal pin 220 of each chip 22 another part to be measured such as the program pump voltage pin of each chip 22 to be measured, because the demand on using also may be connected to a driving passage 200 separately, and becomes parallel connected mode.
Then in step 104, make the signal pin 220 of chip 22 to be measured receive the driving signal from the driving passage that is positioned at the first group 200 that links to each other, and the power pin 222 that makes chip 22 to be measured is from the parallel connected driving passage 200 that is positioned at the second group power supply signal of receipt source inequalities respectively, so that chip 22 to be measured is carried out parallel testing.
Meaning namely, at 22 identical signal pins of each chip to be measured 220 when sharing, for instance such as the frequency pin of each chip 22 to be measured, all will be connected in one of them identical driving passage 220 of the first group, therefore board 20 to be measured only need see through this single and drive passage 220 transmit frequency signals, can be sent to the signal pin 220 of each shared chip 22 to be measured.And at 22 identical signal pins 220 of each chip to be measured when sharing, then need to see through different driving passage 220 and transmit the signal of source inequalities to the signal pin 220 of each chip 22 to be measured.
And on the other hand, the power pin 222 of each chip 22 to be measured is owing to being connected and parallel to each other and independent from different driving passage 220 or power channel 202 respectively, and therefore board 20 to be measured will drive passages 220 by these respectively and transmit power supply signals to the power pin 222 of each chip 22 to be measured.Therefore, the power pin 222 of each chip 22 to be measured will receive the power supply signal of source inequality.
The purpose of parallel testing is that simultaneously a large amount of chips to be measured being carried out various circuit point surveys, and surveys or the survey of AC power circuit point such as DC power supply circuit point.In an embodiment, the content of parallel testing comprises the standby current test.Standby current be for chip 22 to be measured after receiving power supply, do not carry out the electric current that produces under the situation of any operation.
Because among the present invention, power pin 222 is connected with the driving passage 220 of inequality, therefore the power supply that receives is independent each other, can carry out respectively the measurement of standby current, and can be when single chip 22 electric currents to be measured are excessive, learn that it has unusual situation, and the chip to be measured 22 of this bad situation is detected.And parallel to each other and connected mode independently also during therein chip 22 short circuit to be measured, is avoided making other chip 22 to be measured to be affected and is damaged.
Therefore should be noted, in an embodiment, because power channel 202 still can be used for connecting power pin 222 with power supply, chip 22 to be measured still can be under the parallel situation of the power pin 222 that makes each chip 22 to be measured, by power channel 202 power supplies.
In an embodiment, the tester table 20 that Fig. 2 illustrates can also comprise IO channel 204, and each chip 22 to be measured also can comprise at least one input and output pin 224.Aforesaid parallel test method can more comprise each the input and output pin 224 that makes each chip 22 to be measured parallel be connected in IO channel 204 one of them, and make each input and output pin 204 of chip 22 to be measured receive respectively input/output signal (not illustrating) to carry out the step of parallel testing from parallel connected IO channel 224.In the 2nd figure, too complicated for avoiding making diagram, therefore shows in detail does not go out the annexation of IO channel 204 and 224 reality of input and output pin.
Please refer to Fig. 3.Fig. 3 is in one embodiment of the invention, the channel attached schematic diagram of various dissimilar pins and board to be measured 20.
Illustrate such as Fig. 3; the signal pin of write protection, chip selection, frequency and reservation in each chip to be measured can drive passage by one respectively and reach shared purpose, and the program pump voltage is then transmitted by different driving passages respectively owing to user demand.The signal output connecting pin also is connected from different IO channel.And in the present embodiment, each chip to be measured comprises two power supplys, then respectively by different driving passages and power channel connection and supply, to reach parallel connected purpose.
Application the invention has the advantages that by power pin is connected with the driving passage of tester table separately abreast, except the power channel that can avoid tester table is not enough to supply the chip to be measured of massive parallel test, also can increase the accuracy of test, and reach easily above-mentioned purpose.For instance, a chip to be measured may have a power pin, five signal pins and an input and output pin, as want to have 32 power channel at one, carry out the parallel testing of 128 test chips on the board of 480 driving passages and 128 IO channel, owing to can mode described above will drive passage in order to supply power supply, even make its signal pin share drive passage take four chips to be measured as one group, the driving number of active lanes that needs is also only at (128*5)/4+128=288, still in the scope that tester table can be accepted, therefore can realize easily the parallel testing of 128 test chips.In other embodiment, the number of active lanes by adjusting board to be measured and shared mode also can be reached the parallel testing of other number.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention; anyly be familiar with this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the scope that appending claims defines.
Claims (10)
1. a parallel test method is characterized in that, comprises the following step:
One tester table is provided, and wherein this tester table comprises a plurality of driving passages and a plurality of power channel, and wherein these a plurality of driving passages comprise one first group and one second group;
A plurality of chips to be measured are provided, and wherein respectively these a plurality of chips to be measured comprise a plurality of signal pins and at least one power pin;
Making respectively, these a plurality of signal pins of these a plurality of chips to be measured are connected in these a plurality of driving passages that are positioned at this first group;
This power pin that makes these a plurality of chips to be measured respectively respectively parallel be connected to be positioned at this second group these a plurality of driving passages one of them; And
Make these a plurality of signal pins of these a plurality of chips to be measured receive a driving signal from these a plurality of driving passages that are positioned at this first group that link to each other, and this power pin that makes these a plurality of chips to be measured is from parallel connected these a plurality of driving passages that are positioned at this second group power supply signal of receipt source inequalities respectively, so that these a plurality of chips to be measured are carried out a parallel testing.
2. parallel test method according to claim 1 is characterized in that, respectively these a plurality of signal pins identical person wherein of these a plurality of chips to be measured share be positioned at this second group these a plurality of driving passages one of them.
3. parallel test method according to claim 1 is characterized in that, respectively respectively these a plurality of signal pins of these a plurality of chips to be measured parallel be connected in be positioned at this second group these a plurality of driving passages one of them.
4. parallel test method according to claim 1 is characterized in that, this tester table also comprises a plurality of IO channel, and respectively these a plurality of chips to be measured comprise at least one input and output pin.
5. parallel test method according to claim 4 is characterized in that, also comprises the following step:
Make respectively this input and output pins of these a plurality of chips to be measured respectively parallel be connected in these a plurality of IO channel one of them; And
Make respectively this input and output pin of these a plurality of chips to be measured receive respectively an input/output signal from parallel connected these a plurality of IO channel, so that these a plurality of chips to be measured are carried out a parallel testing.
6. parallel test method according to claim 1 is characterized in that, these a plurality of signal pins comprise a write protection pin, a chip selection pin to be measured, a frequency pin, reservation pin and a program pump voltage pin.
7. parallel test method according to claim 1 is characterized in that, this parallel testing comprises standby current test.
8. parallel test method according to claim 7 is characterized in that, this standby current test is in order to measure a respectively standby current of this power pin of these a plurality of chips to be measured.
9. parallel test method according to claim 1 is characterized in that, this parallel testing is that a circuit point is surveyed.
10. parallel test method according to claim 1 is characterized in that, this parallel testing is that a direct current power circuit point is surveyed or an AC power circuit point is surveyed.
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| CN2011102080346A CN102890232A (en) | 2011-07-20 | 2011-07-20 | Parallel testing method |
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| CN2011102080346A CN102890232A (en) | 2011-07-20 | 2011-07-20 | Parallel testing method |
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| WO2020063414A1 (en) * | 2018-09-28 | 2020-04-02 | Changxin Memory Technologies, Inc. | Test method and test system |
| WO2020063483A1 (en) * | 2018-09-28 | 2020-04-02 | Changxin Memory Technologies, Inc. | Chip test method, apparatus, device, and system |
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| US11320484B2 (en) | 2018-09-28 | 2022-05-03 | Changxin Memory Technologies, Inc. | Test method and test system |
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