CN102890234A - SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) application verification system and application verification method - Google Patents
SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) application verification system and application verification method Download PDFInfo
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Abstract
The invention discloses an SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) application verification system and application verification method. The SRAM type FPGA application verification system comprises a PC (Personal Computer), a single-chip, a controlled FPGA, a controllable clock unit, a controllable source unit, a temperature data acquisition unit, a voltage current data acquisition unit and a tested FPGA configuration unit, wherein the SRAM type FPGA application verification system realizes intensive verification of all the functions of a tested FPGA chip. Based on the verification system, the invention also discloses an SRAM type FPGA application verification method. The verification method comprises application verification aiming at basic functions of the FPGA chip, application verification of power adaptability, application verification of a surface temperature trend and application verification of dynamic power consumption. The SRAM type FPGA application verification system and application verification method, disclosed by the invention, have the advantages of adjusting and testing verification project or method based on the need of the application verification of an FPGA device, achieving significance for the application verification of the SRAM type FPGA, and meanwhile, performing comparative testing on functions and performances of devices produced by different manufacturing plants conveniently.
Description
Technical field
The present invention relates to a kind of SRAM type FPGA application verification system and application verification method.
Background technology
In the last few years, SRAM type FPGA used more and morely as reconfigurable large scale integrated circuit device in the satellite development.Because the working environment of satellite is special, such as: can not change in the device course of work, the condition such as space radiation, this requires FPGA to possess higher reliability on the one hand, requires on the other hand FPGA to possess adaptability to space environment.And, in order to ensure the satellite spatial application reliability, before FPGA formally is applied to space flight model task, need to carry out testing experiment with the closely-related functional performance of application state, the i.e. application verification of FPGA to FPGA.
Before this, FPGA uses comparatively and disperses, and along with increasing that FPGA uses, the FPGA checking work of carrying out separately at first has more overlapping content, causes the wasting of resources; The second, different to the requirement of FPGA, checking stresses in a certain respect more, and checking work is not comprehensive; The dispersion checking of the 3rd, FPGA will produce multi-standard, be difficult to form general selection standard, be unfavorable for the unified control and management of FPGA.Therefore, for saving resource, raise the efficiency, propose comprehensively and effectively verification method of a cover, the checking work to FPGA is carried out in unification, and instructs the application of FPGA very necessary with this.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, for the application verification of SRAM type FPGA provide a cover Verification Project comprehensively, SRAM type FPGA application verification system and the application verification method of highly versatile.
Technical solution of the present invention is:
A kind of SRAM type FPGA application verification system comprises PC, single-chip microcomputer, control FPGA, controlled clock unit, controllable electric power unit, temperature data samwpling unit, electric current and voltage data acquisition unit and tested FPGA dispensing unit;
PC is according to default tested FPGA configuration file, by tested FPGA dispensing unit tested fpga chip is configured, PC also sending controling instruction to single-chip microcomputer, send among the control FPGA after the process single-chip microcomputer format transformation, control FPGA adjusts the condition of work of tested fpga chip according to the steering order that receives, that is: control FPGA adjusts the clock input of tested fpga chip and control FPGA adjusts tested fpga chip by the controllable electric power unit supply voltage by controlled clock unit; Described tested fpga chip is SRAM type FPGA;
Control FPGA directly gathers the I/O output signal of tested fpga chip, temperature data samwpling unit gathers the surface temperature of tested fpga chip and exports to control FPGA, the electric current and voltage data acquisition unit gathers the outputting drive voltage of tested fpga chip, core voltage, output driving current and kernel electric current, and the result is outputed among the control FPGA I/O output of the control FPGA tested fpga chip that will collect, the surface temperature data, outputting drive voltage, core voltage, output driving current and kernel electric current send to PC by single-chip microcomputer and show.
Described temperature data samwpling unit is the surface temperature that gathers tested fpga chip by thermopair.
Described SRAM type FPGA application verification method comprises basic function application verification, power adaptation application verification, the checking of surface temperature dynamic application and dynamic power consumption application verification;
Basic function application verification step is as follows:
(a) internal element of tested fpga chip arranged its configuration file, and estimate the I/O output of the tested fpga chip under this configuration file according to configuration file; Described internal element comprises input-output unit IOB, programmed logical module CLB, clock unit DLL and embedded functional module BRAM;
(b) PC is according to tested FPGA configuration file default in the step (a), by tested FPGA dispensing unit tested fpga chip is configured, described SRAM type FPGA application verification system tests tested fpga chip afterwards, gathers the I/O output of tested fpga chip and delivers in the PC;
(c) the I/O Output rusults that compares the actual measurement under each configuration file is estimated I/O output accordingly with it, if all identical, shows that then the basic function of tested fpga chip is normal, otherwise, show that the basic function of tested fpga chip has problems;
The step of power adaptation application verification is as follows:
(1) in the operating voltage range of tested fpga chip, chooses core voltage Vccint and outputting drive voltage Vcco, by the controllable electric power unit tested fpga chip is powered;
(2) PC is configured to counter logic by tested FPGA dispensing unit with tested fpga chip;
(3) keep tested fpga chip under running status, do not change the value of outputting drive voltage Vcco, core voltage Vccint is reduced 0.1V, until the core voltage electricity shortage causes the counter output error at every turn;
(4) magnitude of voltage of the last core voltage Vccint of record is the minimum core operating voltage of tested fpga chip;
(5) re-execute step (1) and (2);
(6) keep tested fpga chip under running status, do not change the value of outputting drive voltage Vcco, core voltage Vccint is increased 0.1V at every turn, the excessive counter output error that causes until core voltage is powered;
(7) magnitude of voltage of the last core voltage Vccint of record is the maximum core operational voltage of tested fpga chip;
(8) re-execute step (1) and (2);
(9) keep tested fpga chip under running status, do not change the value of outputting drive voltage Vcco, core voltage Vccint is reduced 0.1V at every turn, until counter function lost efficacy;
(10) magnitude of voltage of the core voltage Vccint of record last time, the minimum data that is tested fpga chip keeps voltage;
(11) counter logic described in the step (2) is written in the tested FPGA dispensing unit;
(12) in the operating voltage range of tested fpga chip, choose the value of core voltage Vccint and outputting drive voltage Vcco;
(13) slope that powers on of modern outputting drive voltage Vcco remains unchanged, and the slope that powers on of core voltage Vccint is set to 0.1V/50ms;
(14) be supply voltage under tested fpga chip load step (12) and (13) condition, detect the counter logic of tested fpga chip and export whether whether the electric current that powers on normal and tested fpga chip surpasses 2A, if the output of the counter logic of tested fpga chip is normal and the electric current that powers on of tested fpga chip does not surpass 2A, think that then the minimum of the tested fpga chip voltage slope that powers on is 0.1V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 0.1V/50ms, increase progressively 0.2V/50ms at every turn, until satisfy the condition that the counter logic output of the tested fpga chip electric current that powers on normal and tested fpga chip surpasses 2A, the minimum that the is tested fpga chip voltage slope that powers on;
(15) make the slope that powers on of outputting drive voltage Vcco remain unchanged, the slope that powers on of core voltage Vccint is set to 10V/50ms;
(16) be supply voltage under tested fpga chip load step (12) and (15) condition, detect the counter logic of tested fpga chip and export whether whether the electric current that powers on normal and tested fpga chip surpasses 2A, if the output of the counter logic of tested fpga chip is normal and the electric current that powers on of tested fpga chip does not surpass 2A, think that then the maximum of the tested fpga chip voltage slope that powers on is 10V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 10V/50ms, 0.2V/50ms successively decreases at every turn, until satisfy the condition that the counter logic output of the tested fpga chip electric current that powers on normal and tested fpga chip surpasses 2A, the maximum that the is tested fpga chip voltage slope that powers on;
Surface temperature dynamic application verification step is as follows:
(T1) IO of the tested fpga chip of consideration accounts for frequency, resource utilization and three kinds of factors of frequency of operation, designs three kinds of configuration files;
(T2) according to the configuration file in the step (T1), PC is one by one loading configuration file of tested fpga chip by tested FPGA dispensing unit;
(T3) the serviceability temperature data acquisition unit gathers the surface temperature of tested fpga chip, and record data;
(T4) draw relation curve between tested fpga chip surface temperature and its IO occupancy, resource utilization and the frequency of operation according to data;
Dynamic power consumption application verification step is as follows:
(M1) IO occupancy, resource utilization and three kinds of factors of frequency of operation of the tested fpga chip of consideration design three kinds of configuration files;
(M2) according to the configuration file in the step (M1), PC is one by one loading configuration file of tested fpga chip by tested FPGA dispensing unit;
(M3) use voltage and current data collecting unit to gather the value of core voltage Vccint, kernel electric current I ccint, outputting drive voltage Vcco and the output driving current Icco of tested fpga chip, record data also calculate the total power consumption of tested fpga chip;
(M4) draw relation curve between tested fpga chip total power consumption and its IO occupancy, resource utilization and the frequency of operation according to data.
The present invention's advantage compared with prior art is:
(1) the invention provides one completely, dynamic SRAM type FPGA application verification system, can carry out adjustment and measurement to Verification Project or method at any time according to the needs of device application checking, significant for the application verification of SRAM type FPGA.
(2) the present invention can be general for the SRAM type FPGA of domestic different factories same specification, and also can be general for the SRAM type FPGA of external Xilinx company same specification, can be easily to the test of comparing of the device function performance of different factories.
Description of drawings
Fig. 1 SRAM type FPGA verification system schematic diagram;
Fig. 2 SRAM type FPGA application verification method synoptic diagram;
Embodiment
As shown in Figure 1, the invention provides a kind of SRAM type FPGA application verification system, comprise PC, single-chip microcomputer, control FPGA, controlled clock unit, controllable electric power unit, temperature data samwpling unit, electric current and voltage data acquisition unit and tested FPGA dispensing unit;
PC is according to default tested FPGA configuration file, by tested FPGA dispensing unit tested fpga chip is configured, PC also sending controling instruction to single-chip microcomputer, send among the control FPGA after the process single-chip microcomputer format transformation, control FPGA adjusts the condition of work of tested fpga chip according to the steering order that receives, that is: control FPGA adjusts the clock input of tested fpga chip and control FPGA adjusts tested fpga chip by the controllable electric power unit supply voltage by controlled clock unit; Described tested fpga chip is SRAM type FPGA;
Control FPGA directly gathers the I/O output signal of tested fpga chip, temperature data samwpling unit gathers the surface temperature of tested fpga chip and exports to control FPGA, the electric current and voltage data acquisition unit gathers the outputting drive voltage of tested fpga chip, core voltage, output driving current and kernel electric current, and the result is outputed among the control FPGA I/O output of the control FPGA tested fpga chip that will collect, the surface temperature data, outputting drive voltage, core voltage, output driving current and kernel electric current send to PC by single-chip microcomputer and show.
Described temperature data samwpling unit is the surface temperature that gathers tested fpga chip by thermopair.
As shown in Figure 2, SRAM type FPGA application verification method comprises basic function application verification, power adaptation application verification, the checking of surface temperature dynamic application and dynamic power consumption application verification;
Basic function application verification step is as follows:
(a) internal element of tested fpga chip arranged its configuration file, and estimate the I/O output of the tested fpga chip under this configuration file according to configuration file; Described internal element comprises input-output unit IOB, programmed logical module CLB, clock unit DLL and embedded functional module BRAM;
(b) PC is according to tested FPGA configuration file default in the step (a), by tested FPGA dispensing unit tested fpga chip is configured, described SRAM type FPGA application verification system tests tested fpga chip afterwards, gathers the I/O output of tested fpga chip and delivers in the PC;
(c) the I/O Output rusults that compares the actual measurement under each configuration file is estimated I/O output accordingly with it, if all identical, shows that then the basic function of tested fpga chip is normal, otherwise, show that the basic function of tested fpga chip has problems;
The step of power adaptation application verification is as follows:
(1) choosing core voltage Vccint in the operating voltage range of tested fpga chip is that 2.50V and outputting drive voltage Vcco are 3.30V, by the controllable electric power unit tested fpga chip is powered;
(2) PC is configured to counter logic by tested FPGA dispensing unit with tested fpga chip;
(3) keep tested fpga chip under running status, outputting drive voltage keeps Vcco=3.30V, core voltage Vccint is reduced 0.1V at every turn, until the core voltage electricity shortage causes the counter output error;
(4) magnitude of voltage of the last core voltage Vccint of record is the minimum core operating voltage of tested fpga chip;
(5) re-execute step (1) and (2);
(6) keep tested fpga chip under running status, outputting drive voltage keeps Vcco=3.30V, and core voltage Vccint is increased 0.1V at every turn, the excessive counter output error that causes until core voltage is powered;
(7) magnitude of voltage of the last core voltage Vccint of record is the maximum core operational voltage of tested fpga chip;
(8) re-execute step (1) and (2);
(9) keep tested fpga chip under running status, do not change the value of outputting drive voltage Vcco, core voltage Vccint is reduced 0.1V at every turn, until counter function lost efficacy;
(10) magnitude of voltage of the core voltage Vccint of record last time, the minimum data that is tested fpga chip keeps voltage;
(11) counter logic described in the step (2) is written in the tested FPGA dispensing unit;
(12) in the operating voltage range of tested fpga chip, choose the value of core voltage Vccint and outputting drive voltage Vcco;
(13) make the slope that powers on of outputting drive voltage Vcco remain unchanged, the slope that powers on of core voltage Vccint is set to 0.1V/50ms;
(14) be supply voltage under tested fpga chip load step (12) and (13) condition, detect the counter logic of tested fpga chip and export whether whether the electric current that powers on normal and tested fpga chip surpasses 2A, if the output of the counter logic of tested fpga chip is normal and the electric current that powers on of tested fpga chip does not surpass 2A, think that then the minimum of the tested fpga chip voltage slope that powers on is 0.1V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 0.1V/50ms, increase progressively 0.2V/50ms at every turn, until satisfy the condition that the counter logic output of the tested fpga chip electric current that powers on normal and tested fpga chip surpasses 2A, the minimum that the is tested fpga chip voltage slope that powers on;
(15) slope that powers on of modern outputting drive voltage Vcco remains unchanged, and the slope that powers on of core voltage Vccint is set to 10V/50ms;
(16) be supply voltage under tested fpga chip load step (12) and (15) condition, detect the counter logic of tested fpga chip and export whether whether the electric current that powers on normal and tested fpga chip surpasses 2A, if the output of the counter logic of tested fpga chip is normal and the electric current that powers on of tested fpga chip does not surpass 2A, think that then the maximum of the tested fpga chip voltage slope that powers on is 10V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 10V/50ms, 0.2V/50ms successively decreases at every turn, until satisfy the condition that the counter logic output of the tested fpga chip electric current that powers on normal and tested fpga chip surpasses 2A, the maximum that the is tested fpga chip voltage slope that powers on;
Wherein, step (3) and (6) although described in the counter output error refer to counter work, mistake appears in count results; Counter function described in the step (9) lost efficacy and referred to that counter lost its tally function fully.
Surface temperature dynamic application verification step is as follows:
(T1) IO occupancy, resource utilization and three kinds of factors of frequency of operation of the tested fpga chip of consideration design three kinds of configuration files;
(T2) according to the configuration file in the step (T1), PC is one by one loading configuration file of tested fpga chip by tested FPGA dispensing unit;
(T3) the serviceability temperature data acquisition unit gathers the surface temperature of tested fpga chip, and record data;
(T4) draw relation curve between tested fpga chip surface temperature and its IO occupancy, resource utilization and the frequency of operation according to data;
Wherein, IO occupancy aspect is 50% in the resource utilization of tested fpga chip, and input clock frequency is under the condition of 40MHz, respectively the IO occupancy be 10%, 30%, 50%, 70% and 90% 5 kind of situation under design configuration file, to test; The resource utilization aspect, resource utilization take the utilization rate equivalence of the programmed logical module CLB of tested fpga chip inside as tested fpga chip, input clock frequency at tested fpga chip is 40MHz, the IO occupancy is under 10% the condition, respectively resource utilization be 10%, 30%, 50%, 70% and 90% 5 kind of situation under design configuration file, to test; The frequency of operation aspect, be 10% in the IO of tested fpga chip occupancy, resource utilization is to design configuration file under 50% the condition, is to test respectively in 40Mhz, 50Mhz, 60Mhz, 80Mhz, 100Mhz and six kinds of situations of 120Mhz at input clock frequency.
Dynamic power consumption application verification step is as follows:
(M1) IO occupancy, resource utilization and three kinds of factors of frequency of operation of the tested fpga chip of consideration design three kinds of configuration files;
(M2) according to the configuration file in the step (M1), PC is one by one loading configuration file of tested fpga chip by tested FPGA dispensing unit;
(M3) use voltage and current data collecting unit to gather the value of core voltage Vccint, kernel electric current I ccint, outputting drive voltage Vcco and the output driving current Icco of tested fpga chip, record data also calculate the total power consumption of tested fpga chip;
(M4) draw relation curve between tested fpga chip total power consumption and its IO occupancy, resource utilization and the frequency of operation according to data.
Wherein, in the checking of the setting of IO occupancy, three kinds of factors of resource utilization and frequency of operation and surface temperature dynamic application arrange identical.
Claims (3)
1. a SRAM type FPGA application verification system is characterized in that comprising PC, single-chip microcomputer, control FPGA, controlled clock unit, controllable electric power unit, temperature data samwpling unit, electric current and voltage data acquisition unit and tested FPGA dispensing unit;
PC is according to default tested FPGA configuration file, by tested FPGA dispensing unit tested fpga chip is configured, PC also sending controling instruction to single-chip microcomputer, send among the control FPGA after the process single-chip microcomputer format transformation, control FPGA adjusts the condition of work of tested fpga chip according to the steering order that receives, that is: control FPGA adjusts the clock input of tested fpga chip and control FPGA adjusts tested fpga chip by the controllable electric power unit supply voltage by controlled clock unit; Described tested fpga chip is SRAM type FPGA;
Control FPGA directly gathers the I/O output signal of tested fpga chip, temperature data samwpling unit gathers the surface temperature of tested fpga chip and exports to control FPGA, the electric current and voltage data acquisition unit gathers the outputting drive voltage of tested fpga chip, core voltage, output driving current and kernel electric current, and the result is outputed among the control FPGA I/O output of the control FPGA tested fpga chip that will collect, the surface temperature data, outputting drive voltage, core voltage, output driving current and kernel electric current send to PC by single-chip microcomputer and show.
2. a kind of SRAM type FPGA application verification according to claim 1 system, it is characterized in that comprising: described temperature data samwpling unit is the surface temperature that gathers tested fpga chip by thermopair.
3. SRAM type FPGA application verification method based on claim 1 is characterized in that: described SRAM type FPGA application verification method comprises basic function application verification, power adaptation application verification, the checking of surface temperature dynamic application and dynamic power consumption application verification;
Basic function application verification step is as follows:
(a) internal element of tested fpga chip arranged its configuration file, and estimate the I/O output of the tested fpga chip under this configuration file according to configuration file; Described internal element comprises input-output unit IOB, programmed logical module CLB, clock unit DLL and embedded functional module BRAM;
(b) PC is according to tested FPGA configuration file default in the step (a), by tested FPGA dispensing unit tested fpga chip is configured, described SRAM type FPGA application verification system tests tested fpga chip afterwards, gathers the I/O output of tested fpga chip and delivers in the PC;
(c) the I/O Output rusults that compares the actual measurement under each configuration file is estimated I/O output accordingly with it, if all identical, shows that then the basic function of tested fpga chip is normal, otherwise, show that the basic function of tested fpga chip has problems;
The step of power adaptation application verification is as follows:
(1) in the operating voltage range of tested fpga chip, chooses core voltage Vccint and outputting drive voltage Vcco, by the controllable electric power unit tested fpga chip is powered;
(2) PC is configured to counter logic by tested FPGA dispensing unit with tested fpga chip;
(3) keep tested fpga chip under running status, do not change the value of outputting drive voltage Vcco, core voltage Vccint is reduced 0.1V, until the core voltage electricity shortage causes the counter output error at every turn;
(4) magnitude of voltage of the last core voltage Vccint of record is the minimum core operating voltage of tested fpga chip;
(5) re-execute step (1) and (2);
(6) keep tested fpga chip under running status, do not change the value of outputting drive voltage Vcco, core voltage Vccint is increased 0.1V at every turn, the excessive counter output error that causes until core voltage is powered;
(7) magnitude of voltage of the last core voltage Vccint of record is the maximum core operational voltage of tested fpga chip;
(8) re-execute step (1) and (2);
(9) keep tested fpga chip under running status, do not change the value of outputting drive voltage Vcco, core voltage Vccint is reduced 0.1V at every turn, until counter function lost efficacy;
(10) magnitude of voltage of the core voltage Vccint of record last time, the minimum data that is tested fpga chip keeps voltage;
(11) counter logic described in the step (2) is written in the tested FPGA dispensing unit;
(12) in the operating voltage range of tested fpga chip, choose the value of core voltage Vccint and outputting drive voltage Vcco;
(13) make the slope that powers on of outputting drive voltage Vcco remain unchanged, the slope that powers on of core voltage Vccint is set to 0.1V/50ms;
(14) be supply voltage under tested fpga chip load step (12) and (13) condition, detect the counter logic of tested fpga chip and export whether whether the electric current that powers on normal and tested fpga chip surpasses 2A, if the output of the counter logic of tested fpga chip is normal and the electric current that powers on of tested fpga chip does not surpass 2A, think that then the minimum of the tested fpga chip voltage slope that powers on is 0.1V/50ms, otherwise, make that core voltage Vccint's power on slope on the basis of 0.1V/50ms, increase progressively 0.2V/50ms at every turn, until satisfy the condition that the counter logic output of the tested fpga chip electric current that powers on normal and tested fpga chip surpasses 2A, the minimum that the is tested fpga chip voltage slope that powers on;
(15) make the slope that powers on of outputting drive voltage Vcco remain unchanged, the slope that powers on of core voltage Vccint is set to 10V/50ms;
(16) be supply voltage under tested fpga chip load step (12) and (15) condition, detect the counter logic of tested fpga chip and export whether whether the electric current that powers on normal and tested fpga chip surpasses 2A, if the output of the counter logic of tested fpga chip is normal and the electric current that powers on of tested fpga chip does not surpass 2A, think that then the maximum of the tested fpga chip voltage slope that powers on is 10V/50ms, otherwise, modern core voltage Vccint powers on slope on the basis of 10V/50ms, 0.2V/50ms successively decreases at every turn, until satisfy the condition that the counter logic output of the tested fpga chip electric current that powers on normal and tested fpga chip surpasses 2A, the maximum that the is tested fpga chip voltage slope that powers on;
Surface temperature dynamic application verification step is as follows:
(T1) IO occupancy, resource utilization and three kinds of factors of frequency of operation of the tested fpga chip of consideration design three kinds of configuration files;
(T2) according to the configuration file in the step (T1), PC is one by one loading configuration file of tested fpga chip by tested FPGA dispensing unit;
(T3) the serviceability temperature data acquisition unit gathers the surface temperature of tested fpga chip, and record data;
(T4) draw relation curve between tested fpga chip surface temperature and its IO occupancy, resource utilization and the frequency of operation according to data;
Dynamic power consumption application verification step is as follows:
(M1) IO occupancy, resource utilization and three kinds of factors of frequency of operation of the tested fpga chip of consideration design three kinds of configuration files;
(M2) according to the configuration file in the step (M1), PC is one by one loading configuration file of tested fpga chip by tested FPGA dispensing unit;
(M3) use voltage and current data collecting unit to gather the value of core voltage Vccint, kernel electric current I ccint, outputting drive voltage Vcco and the output driving current Icco of tested fpga chip, record data also calculate the total power consumption of tested fpga chip;
(M4) draw relation curve between tested fpga chip total power consumption and its IO occupancy, resource utilization and the frequency of operation according to data.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030110430A1 (en) * | 2001-12-10 | 2003-06-12 | International Business Machines Corporation | Method and system for use of a field programmable gate array (FPGA) function within an application specific integrated circuit (ASIC) to enable creation of a debugger client within the ASIC |
| CN101169466A (en) * | 2007-10-12 | 2008-04-30 | 电子科技大学 | On-spot programmable gate array configurable logic block validation method and system |
| US20080116919A1 (en) * | 2006-11-21 | 2008-05-22 | Yu Li | Fpga and method and system for configuring and debugging a fpga |
| CN201638219U (en) * | 2010-03-23 | 2010-11-17 | 比亚迪股份有限公司 | Real-time FPGA verification system |
| CN102109572A (en) * | 2009-12-23 | 2011-06-29 | 中兴通讯股份有限公司 | Method for testing and method for testing and controlling transmission chip |
| CN102306131A (en) * | 2011-08-23 | 2012-01-04 | 北京亚科鸿禹电子有限公司 | Bus control device for field-programmable gate array (FPGA) prototype verification system |
| CN102306034A (en) * | 2011-08-23 | 2012-01-04 | 北京亚科鸿禹电子有限公司 | Field-programmable gate array (FPGA) prototype verification clock device |
-
2012
- 2012-09-21 CN CN201210355327.1A patent/CN102890234B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030110430A1 (en) * | 2001-12-10 | 2003-06-12 | International Business Machines Corporation | Method and system for use of a field programmable gate array (FPGA) function within an application specific integrated circuit (ASIC) to enable creation of a debugger client within the ASIC |
| US20080116919A1 (en) * | 2006-11-21 | 2008-05-22 | Yu Li | Fpga and method and system for configuring and debugging a fpga |
| CN101169466A (en) * | 2007-10-12 | 2008-04-30 | 电子科技大学 | On-spot programmable gate array configurable logic block validation method and system |
| CN102109572A (en) * | 2009-12-23 | 2011-06-29 | 中兴通讯股份有限公司 | Method for testing and method for testing and controlling transmission chip |
| CN201638219U (en) * | 2010-03-23 | 2010-11-17 | 比亚迪股份有限公司 | Real-time FPGA verification system |
| CN102306131A (en) * | 2011-08-23 | 2012-01-04 | 北京亚科鸿禹电子有限公司 | Bus control device for field-programmable gate array (FPGA) prototype verification system |
| CN102306034A (en) * | 2011-08-23 | 2012-01-04 | 北京亚科鸿禹电子有限公司 | Field-programmable gate array (FPGA) prototype verification clock device |
Non-Patent Citations (1)
| Title |
|---|
| 李小波等: "一类复杂芯片的FPGA验证", 《计算机工程》 * |
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| CN103218268B (en) * | 2013-03-12 | 2015-08-05 | 中国空间技术研究院 | A kind of SRAM type FPGA crosstalk verification method |
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| CN111176919B (en) * | 2019-12-29 | 2022-08-12 | 苏州浪潮智能科技有限公司 | FPGA test method, device and storage medium |
| CN113128156A (en) * | 2021-04-21 | 2021-07-16 | 北京时代民芯科技有限公司 | QDR SRAM application verification system and verification method thereof |
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