CN102891085A - Semiconductor component with metal gate and manufacturing method thereof - Google Patents
Semiconductor component with metal gate and manufacturing method thereof Download PDFInfo
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- CN102891085A CN102891085A CN2011102028027A CN201110202802A CN102891085A CN 102891085 A CN102891085 A CN 102891085A CN 2011102028027 A CN2011102028027 A CN 2011102028027A CN 201110202802 A CN201110202802 A CN 201110202802A CN 102891085 A CN102891085 A CN 102891085A
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Abstract
The invention discloses a semiconductor component with a metal gate and a manufacturing method of the semiconductor component. The semiconductor component comprises a substrate, at least one metal gate and at least one pair of auxiliary structures, wherein the substrate is provided with a plurality of shallow trench isolations; the at least one metal gate is arranged on the substrate; and the at least one pair of auxiliary structures are arranged at both sides of the metal gates.
Description
Technical field
The present invention relates to a kind of semiconductor element with metal gates and preparation method thereof, grid (gate last) technique has semiconductor element of metal gates and preparation method thereof after espespecially a kind of implement.
Background technology
In the known semiconductor industry, polysilicon is widely used in semiconductor element such as metal-oxide semiconductor (MOS) (metal-oxide-semiconductor, the MOS) transistor, selects as the grid material of standard.Yet, along with MOS transistor size micro constantly, the tradition polysilicon gate reduces because boron penetration (boron penetration) effect causes element efficiency, and the problem such as the consumption effect layer that is difficult to avoid (depletion effect), so that the gate dielectric layer thickness of equivalence increases, the grid capacitance value descends, and then cause the predicaments such as decline of element drives ability.Therefore, the semiconductor industry is further attempted new grid material, for example utilize the conductor with work function (work function) metal to replace traditional polysilicon gate, in order to the control electrode as coupling high-k (high-K) gate dielectric.
And the manufacture method of metal gate structure can roughly be divided into normal-gate (gate first) technique and rear grid (gate last) technique two large classes.Wherein normal-gate technique can begin to carry out the super shallow junctions activation tempering of source/drain and form the contour heat budget technique of metal silicide after forming metal gate structure, therefore so that the selection of material is faced more challenge with adjusting.Select for avoiding above-mentioned high heat budget environment and obtaining wider material, grid technology replaced the method for normal-gate technique after industry proposed.
Yet, though rear grid technology can be avoided the super shallow junctions activation tempering of source/drain and form the contour heat budget technique of metal silicide, select and have broad material, but for guaranteeing that metal gates has the conformability requirement that highly still faces complicated technology should be arranged.
Summary of the invention
Therefore, the invention provides a kind of guarantee metal gates have should have the height manufacture method and the semiconductor element with metal gates.
The invention provides a kind of manufacture method with semiconductor element of metal gates, this manufacture method at first provides substrate, and be formed with a plurality of shallow-channel insulations (shallow trench isolation is designated hereinafter simply as STI) in this substrate, then be formed with polysilicon layer in this substrate.This polysilicon layer of patterning, forming at least one nominal grid (dummy gate) and at least one pair of supplementary structure in this substrate, and these supplementary structures are arranged at respectively the both sides of this nominal grid, and are arranged at respectively on this STI.In this substrate, form subsequently at least one semiconductor element, and this semiconductor element comprises this nominal grid.Behind this semiconductor element to be formed, in this substrate, form dielectric layer structure, remove at last this nominal grid and these supplementary structure of this dielectric layer structure of part to expose this semiconductor element.
The present invention also provides a kind of semiconductor element with metal gates, this semiconductor element includes substrate with a plurality of STI, at least onely is arranged at this suprabasil metal gates and at least one pair of is arranged at the supplementary structure of these metal gates both sides, and these supplementary structures are arranged on this STI.
According to the manufacture method with semiconductor element of metal gates provided by the present invention, when forming nominal grid, form respectively supplementary structure in its both sides.Because the existence of supplementary structure, removing dielectric layer structure when exposing nominal grid, on the technique for consume, the especially nominal grid at nominal grid edge and the consume of dielectric layer structure boundary, be transferred to the edge of supplementary structure, especially supplementary structure and dielectric layer structure boundary.Therefore after exposing nominal grid, the height at nominal grid edge is identical with the height of nominal grid central authorities, and the follow-up gate trench that removes nominal grid formation can obtain the degree of depth identical with the nominal grid height.The more important thing is that the metal gates that is formed in the gate trench can obtain the height identical with nominal grid, and then the electrical performance that meets expectation can be provided.
Description of drawings
Fig. 1 and Fig. 2 are the schematic diagram of the metal gate structure manufacture method of grid technology after adopting.
Fig. 3 to Fig. 9 is the schematic diagram of the first preferred embodiment of the manufacture method of a kind of semiconductor element with metal gates provided by the present invention, and wherein Fig. 9 is vertical view, and Fig. 3 to Fig. 8 is the profile that obtains along A-A ' tangent line among Fig. 9.
Figure 10 is the vertical view of the second preferred embodiment of the manufacture method of a kind of semiconductor element with metal gates provided by the present invention.
Figure 11 has or not supplementary structure to be set for the comparison diagram of the impact of nominal grid height.
Description of reference numerals
100 substrates, 102 gate dielectrics
104 polysilicon layers, 106 lightly doped drains
108 clearance walls, 110 source/drains
112 metal silicides, 114 contact hole etching stopping layers
116 inner layer dielectric layers, 120 nominal grids
130 gate trenchs
h
1Script height h
2The loss height
200 substrates, 202 shallow isolating trough
202a active area 204 gate dielectrics
206 polysilicon layers, 208 hard mask
210 nominal grids, 212 supplementary structures
212a supplementary structure 214 supplementary structures
220 lightly doped drains, 222 first clearance walls
224 second clearance walls, 226 source/drains
228 metal silicides, 230 semiconductor elements
240 dielectric layer structures, 242 contact hole etching stopping layers
244 inner layer dielectric layers, 250 metal gates
252 workfunction layers 254 are filled metal level
The W width D
1The first spacing
D
2The second spacing H
1The first height
H
2The second height S live width
Embodiment
See also Fig. 1 and Fig. 2, Fig. 1 and Fig. 2 are the schematic diagram of the manufacture method of the semiconductor element with metal gates of grid technology after adopting.As shown in Figure 1, in the rear grid technology, in substrate 100, form first nominal grid (dummy gate) or replacement grid (replacement gate) 120 by the definition of hard mask (not shown), void put/replace grid 120 can comprise high-k (high dielectric constant is designated hereinafter simply as high-k) gate dielectric 102, as titanium nitride layer (not shown) and the polysilicon layer 104 of bottom barrier layer.Nominal grid 120 has height h
1, height h
1The rough thickness that equals polysilicon layer 104, and the height h of nominal grid 120
1Can be used as the degree of depth of subsequent gate groove and the height of metal gates.Subsequently, finish transistorized other elements of general n type and p-type such as lightly doped drain (lightly-doped drain, LDD) 106, clearance wall 108, source/drain 110, metal silicide (silicide) 112 etc. and contact hole etching stopping layer (contact etch stop layer, be designated hereinafter simply as CESL) 114 with internal layer dielectric (inter-layer dielectric, be designated hereinafter simply as ILD) after layer 116 the making, the polysilicon layer 104 of nominal grid 120 is removed.
Please continue to consult Fig. 1.When removing polysilicon layer 104, at first by flatening process such as chemico-mechanical polishing (chemical mechanical polishing, being designated hereinafter simply as CMP) grinding technics removes unnecessary ILD layer 116 and CESL 114, and expose the hard mask of nominal grid 120.Next utilize another CMP technique to remove ILD layer 116, CESL 114 and hard mask, and expose as shown in Figure 1 polysilicon layer 104.It should be noted that, when removing ILD layer 116, CESL 114 with hard mask, in theory should be by polysilicon layer 104 and the ILD layer 116 that comprises insulating material on every side, characteristic that CESL114 is different with the hard mask rate of etch, and so that CMP technique can stop at polysilicon layer 104.Yet polysilicon layer 104 edges of in fact but being everlasting, even be the edge that clearance wall 108 is bordered on hard mask especially, the phenomenon that polysilicon layer 104 and clearance wall 108 are removed occurs, so that polysilicon layer 104 central authorities after the CMP technique have difference in height with the edge.As shown in Figure 1, nominal grid 120 central authorities have originally height h
1But nominal grid 120 edges obtain another loss height h because of the CMP process loss
2, and script height h
1Obviously greater than consume height h
2
See also Fig. 2.Next remove the polysilicon layer 104 of nominal grid 120, and form gate trench 130.It should be noted that in order to emphasize the script height h of nominal grid 120
1, in Fig. 2, the script height h of the nominal grid 120 that is removed
1Show with dotted line.As shown in Figure 2, after removing polysilicon layer 104 formation gate trenchs 130, the degree of depth of gate trench 130 is not the script height h of script nominal grid 120
1, and the loss that equals to obtain because of CMP loss height h
2Therefore, insert the workfunction metal material and fill metal material when making the metal gate structure (not shown) in subsequent gate groove 130, the height of metal gates also is not equal to the script height h of nominal grid 120
1, but equal consume height h
2In other words, the height of metal gates far low originally expection or due height, and impair its electrical performance.In addition, the consume of gate height raises along with nominal grid 120 density and increases, consume height h
2With script height h
1Difference in addition can reach 400 dusts (angstrom) nearly, seriously affect the electrical performance of metal gates.
See also Fig. 3 to Fig. 9, Fig. 3 to Fig. 9 is the schematic diagram of the first preferred embodiment of the manufacture method of a kind of semiconductor element with metal gates provided by the present invention, wherein Fig. 9 is vertical view, and Fig. 3 to Fig. 8 is the profile that obtains along A-A ' tangent line among Fig. 9.As shown in Figure 3, this preferred embodiment at first provides substrate 200, for example silicon base, contain silicon base or silicon-coated insulated (silicon-on-insulator, SOI) substrate.Comprise a plurality of STI 202 in the substrate 200, in order to the electrical isolation between different elements to be provided, and define a plurality of active area 202a (being shown in Fig. 9); Then sequentially be formed with gate dielectric 204 and polysilicon layer 206 in the substrate 200.It should be noted that, the present invention can with first gate dielectric (high-k first) technique or with rear gate dielectric (high-l last) process integration: when this preferred embodiment and the first gate dielectric process integration, gate dielectric 204 comprises high-k (high dielectric constant, high-k) gate dielectric, it can be metal oxide layer, for example the rare-earth oxide layer.High-k gate dielectric 204 optional autoxidation hafnium (hafnium oxide, HfO
2), hafnium silicate oxygen compound (hafnium silicon oxide, HfSiO
4), hafnium silicate oxynitrides (hafnium silicon oxynitride, HfSiON), aluminium oxide (aluminum oxide, Al
2O
3), lanthana (lanthanum oxide, La
2O
3), tantalum oxide (tantalum oxide, Ta
2O
5), yittrium oxide (yttrium oxide, Y
2O
3), zirconia (zirconium oxide, ZrO
2), strontium titanates (strontium titanate oxide, SrTiO
3), zirconium silicate oxygen compound (zirconium silicon oxide, ZrSiO
4), zirconic acid hafnium (hafnium zirconium oxide, HfZrO
4), strontium bismuth tantalum pentoxide (strontium bismuth tantalate, SrBi
2Ta
2O
9, SBT), lead zirconate titanate (lead zirconate titanate, PbZr
xTi
1-xO
3, PZT) with barium strontium (barium strontium titanate, Ba
xSr
1-xTiO
3, the group that BST) forms.In addition, interface layer (interfacial layer) (not shown) preferably can be set between high-k gate dielectric 204 and substrate 200; And bottom barrier layer (bottom barrier layer) (not shown) can be set preferably between high-k gate dielectric 204 and polysilicon layer 206.Bottom barrier layer can comprise titanium nitride (titanium nitride, TiN), but is not limited to this.And when this preferred embodiment was integrated with rear gate dielectric, gate dielectric 204 can comprise first traditional silicon oxide layer.
See also Fig. 3 and Fig. 9.Next, carry out etch process, utilize hard mask 208 as etching mask etching polysilicon layer 206 and gate dielectric 204, and in substrate 200, form the nominal grid 210 of a plurality of active area 202a of at least one leap, and nominal grid 210 has the first height H
1As shown in Figure 3, nominal grid 210 from bottom to top comprises gate dielectric 204 and polysilicon layer 206.It should be noted that, when forming nominal grid 210, this preferred embodiment forms pair of parallel in the supplementary structure 212 of nominal grid 210 in the substrate 200 of nominal grid 210 both sides, and supplementary structure 212 as shown in Figure 3, be formed in the substrate 200 of nominal grid 210 both sides, and be only to be formed on the STI 202 of nominal grid 210 both sides, be no more than the scope of STI 202, so do not contact with active area 202a.Supplementary structure 212 has width W (being shown in Fig. 9), and this width W is between 0.03 micron (micrometer is designated hereinafter simply as μ m) and 0.1 μ m.Has the first space D between nominal grid 210 and the supplementary structure 212
1, and the first space D
1Between 0.1 μ m and 0.18 μ m.It should be noted that the first space D
1Relevant with the live width S of nominal grid 210, the first space D in this preferred embodiment between 0.1 μ m and 0.18 μ m
1Namely be to be the nominal grid 210 greater than 1 micron (micrometer, μ m) in order to auxiliary live width S.Yet, when the live width S of nominal grid 210 dwindles, the first space D that this preferred embodiment provides
1Also can dwindle, to guarantee the miscellaneous function of supplementary structure 212 thereupon.Should be noted, in this preferred embodiment, as the live width S of nominal grid 210 during greater than 1 μ m, namely need to form supplementary structure 212 in the both sides of nominal grid 210.In addition, in this preferred embodiment, supplementary structure 212 comprises the supplementary structure of single strip (single bar-like).
See also Fig. 4.After forming nominal grid 210 and supplementary structure 212, namely begin to make semiconductor element such as metal-oxide semiconductor (MOS) (metal oxide semiconductor, MOS) the required element (element) of element, at first carry out ion implantation technology, the substrate 200 interior lightly doped drains (lightly doped drain, LDD) 220 that form respectively in nominal grid 210 both sides.Next, in substrate 200, form insulating barrier or insulated compound layer (not shown), and form the first clearance wall 222 by etch back process in the sidewall of nominal grid 210.Even more noteworthy, carrying out when etch back process forms the first clearance wall 222 with the sidewall in nominal grid 210, this preferred embodiment also forms the second clearance wall 224 in the sidewall of supplementary structure 212, and the first clearance wall 222 comprises identical rete with the second clearance wall 224.
See also Fig. 5 and Fig. 9.After forming the first clearance wall 222 and the second clearance wall 224, carry out again ion implantation technology, with in nominal grid 210 both sides, especially the substrate 200 of clearance wall 222 both sides is interior forms respectively source/drain 226, and forms respectively metal silicide 228 on the surface of source/drain 226.In addition, this preferred embodiment also can be in conjunction with (the selective strain scheme of selective stress system, SSS) etc. technique for example utilizes selective epitaxial growth (selective epitaxial growth, SEG) method to make source/drain 226.SSS technique is in the substrate 200 interior groove (not shown) that form respectively first of the first clearance wall 222 both sides, and through after the suitable wet type groove cleaning, utilize the SEG method in groove, to form respectively and be applicable to the epitaxial loayer that includes SiGe (SiGe) of p-type semiconductor element, or be applicable to the epitaxial loayer that includes carborundum (SiC) of N-shaped semiconductor element.So far, can finish the making of semiconductor element 230, and semiconductor element 230 as shown in Figure 5, comprise nominal grid 210.The personage that the making step of said elements and material selection etc. are all this field knows, so neitherly give unnecessary details in this again.Need in addition note be, in order obviously to show the spatial relationship of supplementary structure 212 and nominal grid 210, do not show the elements such as LDD 220, the first clearance wall 222, the second clearance wall 224 and metal silicide 228 among Fig. 9, yet persons skilled in the art should be known these elements and not omit.In addition, as shown in Figure 9, share the semiconductor element 230 of same nominal grid 210 lines by the metal gates series connection of nominal grid 210 and follow-up formation, and the parallel to each other and electrical isolation of the nominal grid 210 of supplementary structure 212 and each semiconductor element 230.In other words, supplementary structure 212 not with the nominal grid 210 of any semiconductor element 230 or the metal gates of follow-up formation, and active area 202a is electrically connected.
See also Fig. 6.After the making of finishing semiconductor element 230, in substrate 200, form dielectric layer structure 240.Dielectric layer structure 240 is composite film, it comprises a contact hole etching stopping layer (contact etch stop layer at least, CESL) 242 with internal layer dielectric (inter-layer dielectric, ILD) layer 244, sequentially be stacked in the substrate 200 as shown in Figure 6.In addition, dielectric layer structure 240 fills up the slit between semiconductor element 230 and the supplementary structure 212.
See also Fig. 7.Next, sequentially carry out the twice flatening process, for example twice chemico-mechanical polishing (chemical mechanical polishing is designated hereinafter simply as CMP) technique.The one CMP technique and stops on the hard mask 208 in order to remove the dielectric layer structure 240 of part.The 2nd CMP technique then continues to grind dielectric layer structure 240 with hard mask 208 until expose the nominal grid 210 (being polysilicon layer 206) of semiconductor element 230 and the polysilicon layer 206 of supplementary structure 212.It should be noted that, because the existence of supplementary structure 212, removing dielectric layer structure 240 when exposing nominal grid 210, CMP technique is for the consume at nominal grid 210 edges, especially the consume of nominal grid 210 and dielectric layer structure 240 or the first clearance wall 222 boundarys, be transferred to the edge of supplementary structure 212, especially supplementary structure 212 and dielectric layer structure 240 or the second clearance wall 224 boundarys.Therefore after twice CMP technique finishes, the nominal grid 210 of semiconductor element 230, semiconductor element 230, and nominal grid 210 and supplementary structure 212 between dielectric layer structure 240 coplines.In other words, the first height H of nominal grid 210
1Be not subject to the impact of CMP technique and can keep originally the first height H
1And supplementary structure 212 edges, especially with respect to the edge of nominal grid 210 opposite sides, and consume in CMP technique with respect to 224 of the second clearance walls on the nominal grid 210 opposite side sidewalls, so its surface be lower than semiconductor element 230, semiconductor element 230 nominal grid 210, and nominal grid 210 and supplementary structure 212 between dielectric layer structure 240.
Should be noted, because the first space D of 210 of supplementary structure that this preferred embodiment provides 212 and nominal grids
1Between 0.1 μ m and 0.18 μ m, so supplementary structure 212 can be effective as the buffer structure of nominal grid 210, so that CMP technique is transferred to supplementary structure 212 to the consumption of nominal grid 210, to save the first height H of nominal grid 210 from damage
1Persons skilled in the art should know that other parts still might arrange because technique is required extra supplementary structure (not shown) in the substrate 200, in order to improve the uniformity of CMP technique.But because the spacing between these supplementary structures and the nominal grid 210 is excessive, namely greater than 0.18 μ m, therefore can't as the buffer structure of nominal grid 210 height in CMP technique, namely can't effectively keep the first height H of nominal grid 210
1
In addition, see also Figure 11, Figure 11 has or not supplementary structure to be set for the comparison diagram of the impact of nominal grid height.As shown in figure 11, according to this preferred embodiment, in the live width S of nominal grid 210 zone greater than 2 μ m, the setting of supplementary structure 212 can effectively improve the problem that nominal grid 210 highly consumes.
See also Fig. 8 and Fig. 9.After twice CMP technique, remove immediately the nominal grid 210 of semiconductor element 230, and in semiconductor element 230 interior formation gate trench (not shown).In addition, supplementary structure 212 also can together remove when removing nominal grid 210, and forms supplementary structure groove (not shown) in substrate 200.Next, in gate trench and supplementary structure groove, sequentially form workfunction layers 252 and fill metal level 254, and remove unnecessary rete by CMP technique again, and in gate trench and supplementary structure groove, form as shown in Figure 8 metal gates 250 and supplementary structure 214.In addition, between workfunction layers 252 and high-k gate dielectric 204, can form etching stopping layer (etch stop layer) (not shown) according to arts demand, and between workfunction layers 252 and filling metal level 254, preferably can form top barrier layer (top barrier layer) (not shown).Workfunction layers 252 can comprise according to the electrical requirement of semiconductor element 230 metal level that satisfies the requirement of N-shaped semiconductor element work function, namely has the work function between 3.9 electron-volts (eV) and 4.3eV.Perhaps, workfunction layers 252 can comprise the metal level that satisfies the requirement of p-type semiconductor element work function, namely has the work function between 4.8eV and 5.2eV.Etching stopping layer can comprise tantalum nitride (tantalum nitride, TaN); The top barrier layer then can comprise TiN, but neitherly is limited to this.Fill 254 of metal levels and can comprise having good filling capacity and metal or metal oxide than low resistance, aluminium (aluminum for example, Al), titanium aluminide (titanium aluminide, TiAl) or aluminium oxide titanium (titanium aluminum oxide, but be not limited to this TiAlO).
It should be noted that gate dielectric 204 can comprise traditional silicon oxide layer when this preferred embodiment and rear gate dielectric process integration, and after forming gate trench as interface layer.Afterwards, the side sequentially forms high-k gate dielectric (not shown), bottom barrier layer (not shown), etching stopping layer (not shown), workfunction layers 252, top barrier layer (not shown) and fills metal level 254 on interface layer 204, finish the making of metal gates 250.The more important thing is that no matter this preferred embodiment is to integrate normal-gate dielectric layer technique or rear gate dielectric layer process, metal gates 250 has the second height H
2, because the first height H of nominal grid 210
1(being represented by dotted lines among Fig. 8 hereby to compare) do not consume in CMP technique, so the degree of depth of gate trench and the second height H of being formed at the metal gates 250 in the gate trench
2The first height H with nominal grid 210
1Identical.In addition, present embodiment is again selective removal ILD layer 244 and CESL 242 etc. also, then again forms the dielectric layer structure that comprises CESL and ILD layer, with the electrical performance of effective lifting semiconductor element 230.
Please again consult Fig. 8.The manufacture method that provides according to this first preferred embodiment, can obtain to have the semiconductor element 230 of metal gates 250, each semiconductor element 230 also comprises at least one pair of supplementary structure 214, be arranged at respectively in the substrate 200 of metal gates 250 both sides, and supplementary structure 214 and metal gates 250 electrical isolation.
It should be noted that in addition these electric conducting materials are inserted aforesaid supplementary structure groove when inserting workfunction layers 252 or filling metal level 254, and form the supplementary structure that comprises electric conducting material 214 as shown in Figure 8.But owing to supplementary structure 214 is arranged on the STI 202, and all surrounded by dielectric layer structure 240 on every side, so the unlikely electrical performance that affects semiconductor element 230 of these kishs.
Next see also Figure 10, Figure 10 is the vertical view of the second preferred embodiment of the manufacture method of a kind of semiconductor element with metal gates provided by the present invention.Should be noted that at first the disclosed step of this second preferred embodiment is identical with the first preferred embodiment, therefore the explanation of identical component symbol can be continued to use the described person of the first preferred embodiment, and identical step repeats no more.In addition, for the spatial relationship of clear performance supplementary structure 212 with nominal grid 210, do not show the elements such as LDDs 220, the first clearance wall 222 and metal silicide 228 among Figure 10, right persons skilled in the art should know that these elements do not omit.
See also Figure 10.This second preferred embodiment and the first preferred embodiment difference are that the supplementary structure that this preferred embodiment provides comprises a plurality of strips (multiple bar-like) supplementary structure 212a.Each supplementary structure 212a has the width W identical with the first preferred embodiment, and it is between 0.03 μ m and 0.1 μ m.Also has the first space D between the supplementary structure 212a of the most close nominal grid 210 and the nominal grid 210
1, it is as described in the first preferred embodiment, between 0.1 μ m and 0.18 μ m.Has the second space D between each supplementary structure 212a
2, and the second space D
2Between 0.12 μ m and 0.23 μ m.As previously mentioned, as the live width S of nominal grid 210 during greater than 1 μ m, this preferred embodiment namely forms supplementary structure 212a in the both sides of nominal grid 210.Should be noted in addition, because the making step of supplementary structure 212a is as described in the first preferred embodiment, identical with the making step of semiconductor element 230, therefore when forming the first clearance wall 222 of semiconductor element 230, the sidewall in each supplementary structure 212a forms respectively the second clearance wall (not shown) simultaneously.
A plurality of strip supplementary structure 212a according to this second preferred embodiment provides can more promote the pooling feature of supplementary structure 212a in CMP technique, guarantee the first height H of nominal grid
1Be not affected.In addition, because supplementary structure 212a is a plurality of list structures, therefore between the adjacent nominal grid 210 one group of supplementary structure can only be set, namely adjacent nominal grid 210 can share a plurality of strip supplementary structure 212a that are formed at therebetween.Certainly, adjacent nominal grid 210 also can comprise respectively a plurality of strip supplementary structure 212a.
In sum, the manufacture method with semiconductor element of metal gates provided by the present invention forms respectively supplementary structure in its both sides when forming nominal grid.Because the existence of supplementary structure, removing dielectric layer structure when exposing nominal grid, on the technique for consume, the especially nominal grid at nominal grid edge and the consume of dielectric layer structure boundary, be transferred to the edge of supplementary structure, especially supplementary structure and dielectric layer structure boundary.That is supplementary structure is as the buffer structure of nominal grid, so that CMP technique is transferred to supplementary structure to the consumption of nominal grid, to save the height of nominal grid from damage.Therefore, after exposing nominal grid, the height at nominal grid edge is identical with the height of nominal grid central authorities, and the follow-up gate trench that removes nominal grid formation can obtain the degree of depth identical with the nominal grid height.The more important thing is that the metal gates that is formed in the gate trench can obtain the height identical with nominal grid, and then the electrical performance that meets expectation can be provided.
In addition, because supplementary structure is integrated in the technique of semiconductor element, therefore the manufacture method with semiconductor element of metal gates provided by the present invention does not increase process costs in addition.And, owing to the consume of gate height increases along with nominal grid density raises, therefore the manufacture method with semiconductor element of metal gates provided by the present invention more is of value to nominal grid density greater than 65%, i.e. the higher technological requirement of semiconductor element density.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (20)
1. manufacture method with semiconductor element of metal gates comprises:
Substrate is provided, is formed with a plurality of shallow isolating trough in this substrate, be formed with polysilicon layer in this substrate;
This polysilicon layer of patterning, to form at least one nominal grid and at least one pair of supplementary structure in this substrate, these a plurality of supplementary structures are arranged at respectively the both sides of this nominal grid, and are arranged at respectively on these a plurality of shallow isolating trough;
In this substrate, form at least one semiconductor element, and this semiconductor element comprises this nominal grid;
In this substrate, form dielectric layer structure; And
Remove this dielectric layer structure of part this nominal grid and these a plurality of supplementary structures to expose this semiconductor element.
2. manufacture method as claimed in claim 1 wherein has the first spacing between this nominal grid and this supplementary structure, and this first spacing is between 0.1 micron and 0.18 micron.
3. manufacture method as claimed in claim 1, wherein this supplementary structure has width, and this width is between 0.03 micron and 0.1 micron.
4. manufacture method as claimed in claim 1, wherein this nominal grid has live width, and this live width is greater than 1 micron.
5. manufacture method as claimed in claim 1, wherein these a plurality of supplementary structures comprise a plurality of strip supplementary structures.
6. manufacture method as claimed in claim 5 wherein has the second spacing between these a plurality of supplementary structures, and this second spacing is between 0.12 micron and 0.23 micron.
7. manufacture method as claimed in claim 1, the sidewall that the step that wherein forms this semiconductor element also is included in this nominal grid forms the first clearance wall, and forms respectively the second clearance wall in the sidewall of these a plurality of supplementary structures simultaneously.
8. manufacture method as claimed in claim 1, wherein this dielectric layer structure covers this semiconductor element and these a plurality of supplementary structures, and fills up the slit between this semiconductor element and this a plurality of supplementary structures.
9. manufacture method as claimed in claim 8, wherein remove this dielectric layer structure of part with after this nominal grid of exposing this semiconductor element and these a plurality of supplementary structures, this nominal grid of this semiconductor element, this semiconductor element, and this nominal grid and this a plurality of supplementary structures between this dielectric layer structure copline.
10. manufacture method as claimed in claim 1 also comprises this nominal grid that removes this semiconductor element, and the step that forms metal gates.
11. manufacture method as claimed in claim 10, wherein this nominal grid have first the height, this metal gates have second the height, and this second highly equal this first the height.
12. the semiconductor element with metal gates comprises:
Substrate is formed with a plurality of shallow isolating trough in this substrate;
At least one metal gates is arranged in this substrate; And
At least one pair of supplementary structure is arranged at the both sides of this metal gates, and on these a plurality of shallow isolating trough.
13. the semiconductor element with metal gates as claimed in claim 12, wherein these a plurality of supplementary structures and this metal gates electrical isolation.
14. the semiconductor element with metal gates as claimed in claim 12 wherein has the first spacing between these a plurality of supplementary structures and this metal gates, and this first spacing is between 0.1 micron and 0.18 micron.
15. the semiconductor element with metal gates as claimed in claim 12, wherein these a plurality of supplementary structures have width, and this width is between 0.03 micron and 0.1 micron.
16. the semiconductor element with metal gates as claimed in claim 12, wherein this metal gates has live width, and this live width is greater than 1 micron.
17. the semiconductor element with metal gates as claimed in claim 12, wherein these a plurality of supplementary structures comprise a plurality of strip supplementary structures.
18. the semiconductor element with metal gates as claimed in claim 17 wherein have the second spacing between these a plurality of strip supplementary structures, and this second spacing is between 0.12 micron and 0.23 micron.
19. the semiconductor element with metal gates as claimed in claim 12 also comprises:
Lightly doped drain is arranged at respectively in this substrate of these a plurality of metal gates both sides;
The first clearance wall is arranged at the sidewall of these a plurality of metal gates; And
Source/drain is arranged at respectively in this substrate of these a plurality of metal gates both sides.
20. the semiconductor element with metal gates as claimed in claim 12, wherein these a plurality of supplementary structures also comprise the second clearance wall, are arranged at the sidewall of these a plurality of supplementary structures.
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| US20050001267A1 (en) * | 2003-07-04 | 2005-01-06 | Semiconductor Leading Edge Technologies, Inc. | Semiconductor device having a damascene-type gate or a replacing-type gate and method of manufacturing the same |
| CN1825541A (en) * | 2005-01-10 | 2006-08-30 | 三星电子株式会社 | Self-aligned contact method |
| JP2008117845A (en) * | 2006-11-01 | 2008-05-22 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| US20080305627A1 (en) * | 2007-06-08 | 2008-12-11 | Elpida Memory, Inc | Method of forming a contact plug and method of forming a semiconductor device |
| US20090155991A1 (en) * | 2007-12-13 | 2009-06-18 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device |
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| US20050001267A1 (en) * | 2003-07-04 | 2005-01-06 | Semiconductor Leading Edge Technologies, Inc. | Semiconductor device having a damascene-type gate or a replacing-type gate and method of manufacturing the same |
| CN1825541A (en) * | 2005-01-10 | 2006-08-30 | 三星电子株式会社 | Self-aligned contact method |
| JP2008117845A (en) * | 2006-11-01 | 2008-05-22 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| US20080305627A1 (en) * | 2007-06-08 | 2008-12-11 | Elpida Memory, Inc | Method of forming a contact plug and method of forming a semiconductor device |
| US20090155991A1 (en) * | 2007-12-13 | 2009-06-18 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device |
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