CN102891100A - Shallow-trench isolation structure and formation method thereof - Google Patents
Shallow-trench isolation structure and formation method thereof Download PDFInfo
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- CN102891100A CN102891100A CN2011102078187A CN201110207818A CN102891100A CN 102891100 A CN102891100 A CN 102891100A CN 2011102078187 A CN2011102078187 A CN 2011102078187A CN 201110207818 A CN201110207818 A CN 201110207818A CN 102891100 A CN102891100 A CN 102891100A
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Abstract
The invention provides a shallow-trench isolation structure and a formation method thereof. The formation method comprises the following steps of: forming a corrosion barrier layer on a semiconductor substrate; etching the corrosion barrier layer and the semiconductor substrate to form a groove; and forming protective layers on the surface of the corrosion barrier layer, and the side wall and the bottom of the groove; filling medium materials in the groove with the protective layer to form medium layers; forming a molecular sieve on the medium layers; introducing reaction gas to the medium layers through the molecular sieve to move all the medium layers so as to form an air gap in the groove; and forming an insulating medium layer on the molecular sieve. A manufacturing method of the shallow-trench isolation structure disclosed by the technical scheme has a simple process and a lower cost.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly a kind of shallow groove isolation structure and forming method thereof.
Background technology
In process for fabrication of semiconductor device, device isolation is an important research topic.The shallow-trench isolation technology has been widely used in the following integrated circuit technology of 0.25 nanometer, and shallow groove isolation structure is compared the carrying out local oxide isolation structure, has to occupy the less advantage of silicon area, thereby has improved the integrated level of device on the unit silicon chip.
Usually the method that forms shallow groove isolation structure is as follows: form photoresist layer in the surface of silicon that is formed with successively oxide layer, polysilicon layer, silicon nitride layer, the pattern of described photoresist layer is corresponding with shallow trench; Take described photoresist layer as mask, etch silicon nitride layer, polysilicon layer, oxide layer and silicon substrate form groove in silicon substrate successively; Employing high-density plasma equipment is filled dielectric and is formed dielectric layer on described silicon nitride layer surface in described groove; With chemical mechanical polishing method (Chemical Mechanical Polishing, CMP) the described dielectric layer of planarization until expose the silicon nitride layer surface, thereby form shallow groove isolation structure.
But, in actual process, directly has certain difficulty by high-density plasma growth method (HDP) filling groove, common way is to form one deck polysilicon (Poly) layer so that groove shoals in groove first, and then forms oxide layer by the high-density plasma growth method at polysilicon layer.Further, also can directly in groove, form oxide layer by high-aspect-ratio growth method (HARP).
Also disclosing a kind of method by formation airspace in groove in the prior art and made shallow groove isolation structure, with reference to figure 1, is a kind of schematic flow sheet that forms the specific implementation method of shallow groove isolation structure in the prior art.Particularly, described technological process comprises the steps, step S1: Semiconductor substrate is provided, forms groove in Semiconductor substrate; Step S2: bottom and sidewall at semiconductor substrate surface and groove form the first oxide layer; Step S3: form dielectric layer in groove, the material of described dielectric layer is can grey formed material; Step S4: form the second oxide layer at dielectric layer; Etching the second oxide layer is to form side wall; Step S5: see through side wall and pass into reacting gas to remove dielectric layer; Step S6: around semiconductor substrate surface and side wall, form the 3rd oxide layer by non-conformal chemical vapour deposition technique.
But the technological process of said method is complicated, and along with constantly the reducing of dimensions of semiconductor devices, forms method very difficult control in actual process of side wall at dielectric layer.Simultaneously, in forming the oxide layer process, the residue on side wall falls in the groove, need to form oxide layer, complex manufacturing technology around semiconductor substrate surface and side wall by non-conformal chemical vapour deposition technique.
More can number be 200910196128.9 patent application document with reference to Chinese patent application about the technical scheme that forms shallow groove isolation structure.
Summary of the invention
The problem that the present invention solves provides a kind of simple process and forms shallow groove isolation structure.
For addressing the above problem, the invention provides a kind of formation method of shallow groove isolation structure, comprise the steps: to form corrosion barrier layer in Semiconductor substrate; The described corrosion barrier layer of etching and Semiconductor substrate form groove; Form protective layer on the surface of described corrosion barrier layer and sidewall, the bottom of groove; Filled media material in being formed with the described groove of protective layer forms dielectric layer; Form molecular sieve at described dielectric layer; See through described molecular sieve and pass into reacting gas to described dielectric layer, removing whole dielectric layers, thereby in described groove, form the airspace; Form insulating medium layer at described molecular sieve.
Alternatively, the method at described dielectric layer formation molecular sieve comprises: spin coating reaction material on described dielectric layer; Reaction material to described spin coating heats to separate out molecular sieve crystal; Clean the reaction material after the described heating, form molecular sieve.
Alternatively, described reaction material comprises silicon-containing compound, aluminum contained compound, alkali and water.
Alternatively, described dielectric material is one or more the dielectric material in carbon containing, nitrogen, the hydrogen.
Alternatively, the reacting gas that passes into to dielectric layer through molecular sieve is oxygen.
Alternatively, the material of described molecular sieve is silicate or the alumino-silicate of crystalline state.
Alternatively, the described corrosion barrier layer of described etching and Semiconductor substrate, the method that forms groove is dry etching.
Alternatively, the parameter of described dry etching is as follows: reacting gas comprises HBr, NF
3And O
2, wherein HBr and NF
3Ratio be that 1: 1, reaction pressure are that 50-100mTorr, power are 500W-1500W.
Alternatively, the material of described protective layer comprises oxygenatedchemicals.
Alternatively, the method at described molecular sieve formation insulating medium layer is chemical vapour deposition technique.
Alternatively, the material of described corrosion barrier layer is silicon nitride.
The present invention also provides a kind of shallow groove isolation structure, comprising: Semiconductor substrate; Be positioned at the corrosion barrier layer on the described Semiconductor substrate; Be positioned at the groove of described Semiconductor substrate and corrosion barrier layer, have the filling part groove in the described groove in groove, to form the molecular sieve of airspace; Be positioned at the insulating medium layer on the described molecular sieve.
Alternatively, the material of described molecular sieve is silicate or the alumino-silicate of crystalline state.
Alternatively, the material of described corrosion barrier layer is silicon nitride.
Alternatively, also be formed with protective layer on the surface of described corrosion barrier layer and sidewall, the bottom of described groove.
Compared with prior art, the technical program has the following advantages: at first form groove in Semiconductor substrate, then filled media material in described groove forms dielectric layer; Form molecular sieve at described dielectric layer; See through described molecular sieve and pass into reacting gas to described dielectric layer, remove whole dielectric layers, form the airspace; At last, form insulating medium layer at described molecular sieve.Form shallow groove isolation structure by technical scheme of the present invention, manufacture craft is simple, and is easier to control at the technique ratio of dielectric layer formation molecular sieve, and passes into reacting gas removal dielectric layer through molecular sieve, and the effect that forms the airspace in groove is better.
Further, employing has replaced the method that forms side wall in the prior art at dielectric layer in the method that dielectric layer forms molecular sieve, therefore, it is follow-up when molecular sieve forms insulating medium layer, only need just can realize by common chemical vapour deposition technique, and do not need to form oxide layer by non-conformal chemical vapour deposition technique, manufacture craft is simple.
Description of drawings
Fig. 1 is a kind of schematic flow sheet that forms the specific implementation method of shallow groove isolation structure in the prior art;
Fig. 2 is a kind of schematic flow sheet that forms the specific implementation method of shallow groove isolation structure provided by the invention;
Fig. 3 to Fig. 9 is the cross-sectional view that the present invention forms the specific embodiment of shallow groove isolation structure.
Embodiment
The inventor finds that in the prior art the technique that forms shallow groove isolation structure is complicated, and along with the size of semiconductor device constantly reduces, forms method very difficult control in actual process of side wall at dielectric layer.Simultaneously, in forming the oxide layer process, the residue on side wall falls in the groove, need to form oxide layer, complex manufacturing technology around semiconductor substrate surface and side wall by non-conformal chemical vapour deposition technique.For the problems referred to above, the inventor provides a kind of shallow groove isolation structure and forming method thereof through research, and its manufacture craft is simple.
For those skilled in the art be can better understand the present invention, describe shallow groove isolation structure of the present invention and forming method thereof in detail below in conjunction with accompanying drawing and specific embodiment.
Fig. 2 is a kind of schematic flow sheet that forms the specific implementation method of shallow groove isolation structure provided by the invention.With reference to figure 2, the method for the formation shallow groove isolation structure of the specific embodiment of the invention comprises:
Step S11: form corrosion barrier layer in Semiconductor substrate;
Step S12: the described corrosion barrier layer of etching and Semiconductor substrate form groove;
Step S13: form protective layer on the surface of described corrosion barrier layer and sidewall, the bottom of groove;
Step S14: filled media material in being formed with the described groove of protective layer forms dielectric layer;
Step S15: form molecular sieve at described dielectric layer;
Step S16: see through described molecular sieve and pass into reacting gas to described dielectric layer, removing whole dielectric layers, thereby in described groove, form the airspace;
Step S17: form insulating medium layer at described molecular sieve.
Further, be the cross-sectional view of the specific embodiment of formation shallow groove isolation structure of the present invention such as Fig. 3 to Fig. 9, in conjunction with the method that describes the formation shallow groove isolation structure of the specific embodiment of the invention with reference to figure 2 and Fig. 3 to Fig. 9 in detail.
In conjunction with referring to figs. 2 and 3, execution in step S11, form corrosion barrier layers 21 in Semiconductor substrate 20.In embodiments of the present invention, the material of described Semiconductor substrate 20 can be the III-V compounds of group such as monocrystalline silicon, germanium silicon, silicon-on-insulator or GaAs.The material of described corrosion barrier layer 21 is silicon nitrides, but is not limited to silicon nitride in the practical application.
Alternatively, the method that forms corrosion barrier layer 21 in Semiconductor substrate 20 is chemical vapour deposition technique or physical vaporous deposition, but is not limited to said method.The effect of described corrosion barrier layer 21 be in subsequent technique as etching stop layer, with the protection Semiconductor substrate 20 be not damaged.For example, when the protective layer of the follow-up formation of etching or insulating medium layer, can be with described corrosion barrier layer 21 as etching stop layer.
In conjunction with reference to figure 2 and Fig. 4, execution in step S12, the described corrosion barrier layer 21 of etching and Semiconductor substrate 20 form groove 22.In embodiments of the present invention, adopt the dry etching method that described corrosion barrier layer 21 and Semiconductor substrate 20 are carried out etching, form groove 22.Wherein, the parameter of described dry etching is as follows: reacting gas comprises HBr, NF
3And O
2, wherein HBr and NF
3Ratio be 1: 1, reaction pressure be 50-100mTorr (millitorr), power be 500-1500W (watt).
The concrete technology that forms groove 22 is as follows: apply the photoresist layer (not shown) at described corrosion barrier layer 21, through photoetching process, define groove figure at photoresist layer; Take described photoresist layer as mask, along the described corrosion barrier layer 21 of groove figure etching and Semiconductor substrate 20, form groove 22.Alternatively, the width of the described groove that forms is that 65nm (nanometer), the degree of depth are 1.8 μ m (micron), but be not limited to above-mentioned width and the degree of depth, according to different technological requirements, those skilled in the art can form by the technological parameter that changes dry etching the groove of different in width and the degree of depth.
In conjunction with referring to figs. 2 and 5, execution in step S13, form protective layer 23 in sidewall, the bottom of described corrosion barrier layer 21 surfaces and groove 22.In embodiments of the present invention, the effect of described protective layer 23 is that the reacting gas that passes into can not react with described Semiconductor substrate 20 so that follow-up in the process of described groove 22 interior formation airspaces.Alternatively, the material of described protective layer 23 comprises oxygenatedchemicals, but is not limited to above-mentioned material.
In conjunction with referring to figs. 2 and 6, execution in step S14, at described groove 22 interior filled media materials, form dielectric layer 24.Because described dielectric layer 24 needs all to be removed in subsequent step, usually select the material easily removed, in embodiments of the present invention, described dielectric material is one or more the dielectric material in carbon containing, nitrogen, the hydrogen.Particularly, for example, described dielectric layer 24 is amorphous carbon, diamond-like-carbon (Diamond-like carbon, DLC) etc., but is not limited to above-mentioned material.
The method that forms described dielectric layer 24 can be chemical vapour deposition technique or physical vaporous deposition, but is not limited to above-mentioned two kinds of methods in the actual process.
In conjunction with reference to figs. 2 and 7, execution in step S15, form molecular sieves 25 at described dielectric layer 24.In the present embodiment, described molecular sieve 25 be crystalline state silicate or alumino-silicate.
Particularly, the step that forms molecular sieve 25 comprises: at first, spin coating reaction material on described dielectric layer 24, described reaction material comprises: silicon-containing compound (waterglass, Ludox etc.), aluminum contained compound (hydrated alumina, aluminium salt etc.), alkali (NaOH, potassium hydroxide etc.) and water; Reaction material to described spin coating heats to separate out molecular sieve crystal, i.e. the silicate of crystalline state or alumino-silicate; Clean at last the reaction material after the described heating, other reactants of flush away form molecular sieve 25.Need to prove that in actual applications, the method that forms molecular sieve 25 is not limited to this.
In conjunction with reference to figure 2 and Fig. 8, execution in step S16 sees through described molecular sieve 25 and passes into reacting gas to described dielectric layer 24, removing whole dielectric layers 24, thereby in described groove 22 interior formation airspaces 24 '.In embodiments of the present invention, the reacting gas that passes into to dielectric layer 24 through molecular sieve 25 is oxygen.
Because the material of described dielectric layer 24 comprises one or more the dielectric material in carbon, nitrogen, the hydrogen, correspondingly, above-mentioned these materials and oxygen reaction can form gas (such as carbon dioxide, nitrogen dioxide, steam etc.), remove easily, thereby form airspace 24 in the space that described dielectric layer 24 occupies originally '.Particularly, because molecular sieve 25 has micropore usually, see through described molecular sieve 25 and pass into high-octane oxygen gas plasma to dielectric layer 24, described high-octane oxygen gas plasma is by the micropore in the molecular sieve 25, arrive described dielectric layer 24 place faces, and with 24 reactions of described dielectric layer, remove whole dielectric layers 24.Simultaneously, owing to be formed with protective layer 23 at bottom and the sidewall of groove, and oxygen gas plasma and described protective layer 23 do not react, like this script be positioned at the formation air gap 24, position of the dielectric layer 24 of groove '.
In conjunction with referring to figs. 2 and 9, execution in step S17, form insulating medium layers 26 at described molecular sieve 25.In embodiments of the present invention, the method that forms insulating medium layer 26 at described molecular sieve 25 is chemical vapour deposition technique.Compared with prior art, owing to replaced side wall by molecular sieve 25, therefore when described molecular sieve 25 forms insulating medium layer 26, only need to get final product by common chemical vapour deposition technique, manufacture craft is simple.Alternatively, the material of described insulating medium layer 26 comprises oxide, nitride, but is not limited to above-mentioned material.
Continuation is with reference to figure 9, formed a kind of shallow groove isolation structure of the embodiment of the invention according to above-mentioned process, comprising: Semiconductor substrate 20; Be positioned at the corrosion barrier layer 21 on the described Semiconductor substrate 20, the material of wherein said corrosion barrier layer 21 can be silicon nitride, but is not limited to described material; Be positioned at the groove of described Semiconductor substrate 20 and corrosion barrier layer 21, have in the described groove filling part groove with in groove, form airspace 24 ' molecular sieve 25, the material of wherein said molecular sieve 25 is silicate or alumino-silicates of crystalline state; Be positioned at the insulating medium layer 26 on the described molecular sieve 25.
Further, also be formed with protective layer 23 on the surface of described corrosion barrier layer 21 and sidewall, the bottom of groove.Alternatively, the material of described protective layer is oxygenatedchemicals, but is not limited to above-mentioned material.The effect of described protective layer 23 is to form 24 ' time of airspace in groove, prevents that the reacting gas and the Semiconductor substrate 20 that pass into groove from reacting.
The shallow groove isolation structure that the embodiment of the invention provides, manufacture craft is simple, and is easier to control at the technique ratio of dielectric layer formation molecular sieve, and passes into reacting gas removal dielectric layer through molecular sieve, and the effect that forms the airspace in groove is better.Simultaneously, replace existing side wall by using molecular sieve, therefore when molecular sieve forms insulating medium layer, only needed common chemical vapour deposition technique just can realize that manufacture craft is simple.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (16)
1. the formation method of a shallow groove isolation structure is characterized in that, comprises the steps:
Form corrosion barrier layer in Semiconductor substrate;
The described corrosion barrier layer of etching and Semiconductor substrate form groove;
Form protective layer on the surface of described corrosion barrier layer and sidewall, the bottom of groove;
Filled media material in being formed with the described groove of protective layer forms dielectric layer;
Form molecular sieve at described dielectric layer;
See through described molecular sieve and pass into reacting gas to described dielectric layer, removing whole dielectric layers, thereby in described groove, form the airspace;
Form insulating medium layer at described molecular sieve.
2. the formation method of shallow groove isolation structure according to claim 1 is characterized in that, the method that forms molecular sieve at described dielectric layer comprises:
Spin coating reaction material on described dielectric layer;
Reaction material to described spin coating heats to separate out molecular sieve crystal;
Clean the reaction material after the described heating, form molecular sieve.
3. the formation method of shallow groove isolation structure according to claim 2 is characterized in that, described reaction material comprises silicon-containing compound, aluminum contained compound, alkali and water.
4. the formation method of shallow groove isolation structure according to claim 1 is characterized in that, described dielectric material comprises one or more in carbon, nitrogen, the hydrogen.
5. the formation method of shallow groove isolation structure according to claim 1 is characterized in that, the reacting gas that passes into to dielectric layer through molecular sieve is oxygen.
6. the formation method of shallow groove isolation structure according to claim 1 is characterized in that, the material of described molecular sieve is silicate or the alumino-silicate of crystalline state.
7. the formation method of shallow groove isolation structure according to claim 1 is characterized in that, the described corrosion barrier layer of described etching and Semiconductor substrate, and the method that forms groove is dry etching.
8. the formation method of shallow groove isolation structure according to claim 7 is characterized in that, the parameter of described dry etching is as follows: reacting gas comprises HBr, NF
3And O
2, wherein HBr and NF
3Ratio be that 1: 1, reaction pressure are that 50-100mTorr, power are 500-1500W.
9. the formation method of shallow groove isolation structure according to claim 1 is characterized in that, the material of described protective layer comprises oxygenatedchemicals.
10. the formation method of shallow groove isolation structure according to claim 1 is characterized in that, the method that forms insulating medium layer at described molecular sieve is chemical vapour deposition technique.
11. the formation method of shallow groove isolation structure according to claim 1 is characterized in that the material of described corrosion barrier layer is silicon nitride.
12. a shallow groove isolation structure is characterized in that, comprising: Semiconductor substrate; Be positioned at the corrosion barrier layer on the described Semiconductor substrate; Be positioned at the groove of described Semiconductor substrate and corrosion barrier layer, have the filling part groove in the described groove in groove, to form the molecular sieve of airspace; Be positioned at the insulating medium layer on the described molecular sieve.
13. shallow groove isolation structure according to claim 12 is characterized in that, the material of described molecular sieve is silicate or the alumino-silicate of crystalline state.
14. shallow groove isolation structure according to claim 12 is characterized in that, the material of described corrosion barrier layer is silicon nitride.
15. shallow groove isolation structure according to claim 12 is characterized in that, also is formed with protective layer on the surface of described corrosion barrier layer and sidewall, the bottom of described groove.
16. shallow groove isolation structure according to claim 15 is characterized in that, the material of described protective layer is oxygenatedchemicals.
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| CN111009497A (en) * | 2019-12-31 | 2020-04-14 | 长春理工大学 | High-thermal-conductivity semiconductor substrate and preparation method and application thereof |
| CN112736026A (en) * | 2021-01-12 | 2021-04-30 | 度亘激光技术（苏州）有限公司 | Semiconductor structure forming method and semiconductor structure |
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| CN102891100B (en) | 2015-04-29 |
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