CN102931237A - Structure of perpendicular asymmetric ring gating metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method thereof - Google Patents
Structure of perpendicular asymmetric ring gating metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method thereof Download PDFInfo
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- CN102931237A CN102931237A CN2012103811659A CN201210381165A CN102931237A CN 102931237 A CN102931237 A CN 102931237A CN 2012103811659 A CN2012103811659 A CN 2012103811659A CN 201210381165 A CN201210381165 A CN 201210381165A CN 102931237 A CN102931237 A CN 102931237A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title abstract description 4
- 230000005669 field effect Effects 0.000 title abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 24
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 18
- 238000002513 implantation Methods 0.000 claims description 16
- 239000012190 activator Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000004151 rapid thermal annealing Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000005260 corrosion Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000003518 caustics Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 13
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 210000000746 body region Anatomy 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 31
- 230000005684 electric field Effects 0.000 description 5
- 239000002210 silicon-based material Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- 238000013517 stratification Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention provides a structure of a perpendicular asymmetric ring gating metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method thereof. The structure of the device comprises a bottom-layer n-type silicon wafer substrate 101, wherein a drain region 111 is positioned at the bottommost end of the device; a drain expansion region 106, a channel region 107 and a source region grow on the substrate 101 in an epitaxial manner; a grating oxidization layer 109 encircles the whole channel region 107; and polycrystalline silicon gratings 110 are deposited on the grating oxidization layer 109. The invention provides the structure of the perpendicular asymmetric ring gating MOSFET with a function of effectively suppressing a short channel effect and a manufacturing method of the perpendicular asymmetric ring gating MOSFET; and by the manufacturing method, the technical process can be simplified and the length of the grating and the thickness of a silicon body region can be flexibly controlled.
Description
Technical field
What the present invention relates to is a kind of semiconductor device, the present invention also relates to a kind of formation method of semiconductor device.Specifically a kind of structure of vertical asymmetric surrounding-gate MOSFET device and manufacture method thereof.
Background technology
In recent years, along with the develop rapidly of semicon industry, integrated circuit has developed into very large scale integration (ULSI) stage.The size of device also is reduced to nanoscale thereupon, and this has proposed very large challenge for developing new device structure and manufacture craft.In the past few decades, the size of MOSFET device is constantly reducing always, and the length of effective channel of now MOSFET device is less than 10 nanometers.For the driving force and the better short-channel effect that suppresses that improve constantly electric current, the MOSFET device develops into the multiple-grid three-dimension device from traditional single grid planar device.In all multiple-grid devices, ring grid (Gate-All-Around, GAA) device is best to the inhibitory action of short-channel effect compared to other multiple-grid device, and in the ring gate device, cross section is that the device performance of circle is superior.
The design that develops into integrated circuit of nanoscale electric device has brought very high complexity, and the cost of complicated etching system and costliness.Along with the characteristic size of device constantly reduces, the manufacture craft of conventional MOS FET device also is restricted, and the MOSFET device that has therefore worked out vertical stratification substitutes traditional devices.The sense of current vertically flows to source electrode from drain electrode in this device.It has not only simplified the photoetching technique of definition channel region, has also kept the compatibility with standard technology simultaneously.The more important thing is, because active area is positioned at the side of silicon body, it more easily forms double grid or gate-all-around structure than planar device.Therefore can suppress short-channel effect, strengthen current driving capability.
Yet when channel length is reduced to 50 nanometers when following, the MOSFET device of vertical stratification can face the problem of a sternness: in order to suppress short-channel effect, channel doping concentration must very highly (can reach 7.0 * 10
18Cm
-3), this can cause very large junction leakage, reduces the channel carrier mobility.Adopting traditional symmetrical LDD(Lightly Doped Drain) after the structure, although channel doping concentration can be reduced to 3.5 * 10
18Cm
-3, but this still cannot be accepted in less than the device of 50 nanometers in channel length.In order to address these problems, the MOSFET device of asymmetric LDD vertical stratification has been proposed.Asymmetric LDD structure is compared to have with symmetrical LDD structure and can be reduced cut-off leakage current, reduces near the electric field drain junction, suppresses short-channel effect and reduces the advantage such as source series resistance.Compatible mutually with planar CMOS technique on manufacture craft, be easy to realize.
The problem of bringing in order to solve device dimensions shrink has worked out the MOSFET device of gradual change channel doping.By the gradual change of channel region doping content, improved source tangent line electric field strength, therefore obtained very high carrier's rate, suppressed short-channel effect.But in traditional planar MOSFET device, in order to obtain asymmetrical channel doping, must use wide-angle to inject (large-angle-tilt implant) and complicated photoetching process.Therefore worked out the MOSFET device of the vertical stratification of gradual change channel doping, not only can be compatible mutually with the traditional cmos manufacture craft on manufacture craft, and good inhibition short-channel effect ability is arranged.The nanoscale devices structure that has nowadays proposed has a lot, with the similar device of the present invention vertical asymmetric double grid MOSFET component and perpendicular rings grid MOSFET component is arranged.Compare with the device architecture that the present invention proposes, above two kinds of devices have respectively grid-control scarce capacity and the excessive shortcoming of leakage current.
Summary of the invention
The object of the present invention is to provide a kind of vertical asymmetric surrounding-gate MOSFET structure of effect of establishment short-channel effect.The present invention also aims to provide a kind of can simplification of flowsheet, the flexible manufacture method of the vertical asymmetric surrounding-gate MOSFET of the long and silicon tagma thickness of control gate.
The object of the present invention is achieved like this:
The structure of vertical asymmetric surrounding-gate MOSFET device is: comprise bottom N-shaped silicon wafer substrate 101, drain region 111 is positioned at the least significant end of device; Expansion area 106 is leaked in epitaxial growth on N-shaped silicon wafer substrate 101, channel region 107, and source region 108, and gate oxide 109 surrounds whole channel region 107, depositing polysilicon grid 110 on gate oxide 109.
Mix for n-in described leakage expansion area 106; Described channel region 107 mixes for p-type; Mix for n+ in described source region 108, drain region 111, doping content is 1 * 10
18～1 * 10
19Cm
-3
Described channel region 107 channel lengths are 10～20nm.
107 one-tenth cylinders of described channel region, described polysilicon gate 110 is circular with 109 one-tenth of gate oxides.
The manufacture method of vertical asymmetric surrounding-gate MOSFET device may further comprise the steps:
Step 1, the preparation crystal orientation be＜100 N-shaped silicon wafer substrate 101;
Step 2, on N-shaped silicon wafer substrate 101 deposit one deck SiO successively
2 Layer 102, SiGe layer 103, and SiO
2 Layer 104;
The SiO of step 3, photoetching deposit growth
2Layer 102, SiGe layer 103, and SiO
2 Layer 104 makes the SiO of mid portion
2Layer 102, SiGe layer 103 and SiO
2 Layer 104 all is etched away, and forms window, take photoresist as masking layer, device is carried out Implantation form drain region 111, rapid thermal annealing activator impurity behind the Implantation;
Step 4, on N-shaped silicon wafer substrate 101 epitaxial growth silicon epitaxial layers 105, in epitaxial growth, carry out simultaneously the n-diffusing, doping;
Step 5, with SiO
2Layer 104 is stop-layer, and silicon epitaxial layers 105 is carried out chemico-mechanical polishing;
Step 6, device is at first carried out low energy ion inject, form the p-type tagma; Then carry out energetic ion and inject, form n+ type source region, carry out the rapid thermal annealing activator impurity behind the Implantation;
Form successively from top to bottom source region 108 in the silicon epitaxy layer zone behind step 7, the Implantation, channel region 107 and leakage expansion area 106 utilize SiGe and SiO
2Selection in corrosive agent is carried out selective corrosion, then thermal oxide growth one deck SiO on the zone that is corroded than different
2, as gate oxide 109;
Step 8, the SiO to not being corroded
2Layer carries out etching, then at the outside deposit one deck of gate oxide polysilicon gate 110, and polysilicon gate 110 is carried out the doping of n+ type inject the short annealing activator impurity.
The main feature of method of the present invention is as follows:
1) adopt gate-all-around structure, grid surrounds whole channel region; 2) adopt vertical channel structure, long by the flexible control gate of thickness that changes the SiGe layer; 3) adopt asymmetric LDD structure, reduce near the electric field of drain junction; 4) adopt rear grid technique, carry out first the autoregistration doping and form source region, channel region and drain region, then make gate electrode.Need a series of high temperature processing step owing to forming source region, channel region and drain region, such as Implantation and annealing, grid oxygen has avoided being subject to the impact of the extraneous factors such as temperature in the therefore rear grid technique, makes device performance more superior; 5) etching process by being easy to control is controlled silicon tagma thickness flexibly, makes it easily to reach entirely to exhaust, and strengthens the grid-control ability.
Description of drawings
The generalized section of Fig. 1 a kind of vertical asymmetric surrounding-gate MOSFET device disclosed by the invention;
Fig. 2 prepares the schematic diagram of Silicon Wafer;
Fig. 3 is successively deposit one deck SiO of Fig. 2 structure
2, SiGe, and SiO
2After sectional view;
Fig. 4 is that Fig. 3 structure is through the schematic diagram of over etching and Implantation;
Fig. 5 is the sectional view after Fig. 4 structure process epitaxial silicon material and n-mix;
Fig. 6 is that Fig. 5 structure is through the sectional view after the chemico-mechanical polishing;
Fig. 7 is the schematic diagram that Fig. 6 structure is carried out high low energy Implantation;
Fig. 8 is SiO in Fig. 7 structure
2With the process selective corrosion of SiGe layer and heat growth SiO
2After sectional view;
Fig. 9 is the SiO that Fig. 8 structure etching is not corroded
2SiO with the growth of polysilicon deposit heat
2After sectional view.
Embodiment
For example the present invention is done detailed description below in conjunction with accompanying drawing:
Specific embodiment one:
In conjunction with Fig. 2.Shown in the preparation crystal orientation be＜100 N-shaped silicon wafer substrate 101, thickness is 100nm.
In conjunction with Fig. 3.On N-shaped Silicon Wafer 101, deposit SiO in turn
2Layer 102, SiGe layer 103 and SiO
2Layer 104.SiO wherein
2 Layer 102, SiGe layer 103 and SiO
2The thickness of layer 104 is 20～50nm.
In conjunction with Fig. 4.Fig. 3 structure is carried out photoetching, make the SiO of mid portion
2Layer 102, SiGe layer 103 and SiO
2Layer 104 all is etched away, and forms window.Then with photoresist as the doping masking layer, silicon materials are carried out N-shaped mix to inject, rapid thermal annealing (RTA) activator impurity forms drain region 111.
In conjunction with Fig. 5.Silicon epitaxial layers 105 on silicon materials, and the thickness of silicon epitaxial layers 105 is 200～300nm, carry out the n-diffusing, doping simultaneously in epitaxial growth, form to leak expansion area LDD.
In conjunction with Fig. 6.With SiO
2Layer 104 is stop-layer, and silicon epitaxial layers 105 is carried out chemico-mechanical polishing (CMP).
In conjunction with Fig. 7.With SiO
2 Layer 104 is masking layer, at first carries out low energy boron Implantation, forms the p-type channel region; Then carry out the high energy arsenic ion and inject, form the n+ source region.Then carry out the rapid thermal annealing activator impurity.
In conjunction with Fig. 8.Form successively from top to bottom source region 108 behind the Implantation in the silicon epitaxy layer zone, channel region 107 and leak expansion area 106.Wherein, the doping type in source region 108 and drain region 111 is identical with concentration, is n+ and mixes, and concentration is 1 * 10
18～1 * 10
19Cm
-3Leaking expansion area 106 mixes for n-; Channel region 107 mixes for p-type.Because in certain corrosive agent, the corrosion rate of SiGe is far above SiO
2Corrosion rate, therefore utilize SiO
2With the selection of SiGe in this corrosive agent than different, to SiO
2 Layer 102, SiGe layer 103 and SiO
2 Layer 104 carries out selective corrosion, and the thin SiO of SiGe layer 103 place's thermal oxide growth that is eroding
2Layer 109 is as gate oxide.
In conjunction with Fig. 9.Etch away SiO
2 Layer 102 and SiO
2 Layer 104 is at gate oxide 109 outer outgrowth one deck polycrystalline silicon materials 110, as grid material.Polycrystalline silicon material is carried out the doping of n+ type inject the short annealing activator impurity.
The advantage of embodiment one is: 1) adopt gate-all-around structure, effective quantity of grid is maximum, so grid is the strongest to the electricity control of raceway groove, can farthest reduce short-channel effect; 2) adopt vertical channel structure, need not to define channel length by the means of photolithography of complexity, be not subjected to the restriction of lithographic accuracy, and working principle and characteristic and planar device are almost identical; 3) adopt asymmetric LDD structure, compare to have with symmetrical LDD structure and can reduce cut-off leakage current, reduce near the electric field drain junction, suppress short-channel effect and reduce the advantage such as source series resistance.Compatible mutually with planar CMOS technique on manufacture craft, be easy to realize; 4) adopt rear grid technique, carry out first the autoregistration doping and form source region, channel region and drain region, then make gate electrode.Need a series of high temperature processing step owing to forming source region, channel region and drain region, such as Implantation and annealing, grid oxygen has avoided being subject to the impact of the extraneous factors such as temperature in the therefore rear grid technique, makes device performance more superior; 5) etching process by being easy to control is controlled silicon tagma thickness flexibly, makes sacrificial oxide layer reach the excessive erosion state in the actual fabrication process as far as possible, channel region is easily reached entirely exhaust, and strengthens the grid-control ability.
Specific embodiment two:
Other described steps are with specific embodiment one.
In conjunction with Fig. 7.With SiO
2Layer 104 is masking layer, at first carries out low energy ion and injects, and Implantation Energy is 20keV, and dosage is 5 * 10
13Cm
-2The boron ion, to form the gradual change raceway groove; Then carry out energetic ion and inject, Implantation Energy is 20keV, and dosage is 2 * 10
15Cm
-2Arsenic ion, to form the source region.Then carry out the rapid thermal annealing activator impurity.The doping content of gradual change channel region 107 reduces from the source to the drain terminal gradually, is 2 * 10
18～8 * 10
17Cm
-3
Embodiment two has possessed all advantages of embodiment one, and channel region doping content gradual change, has improved source tangent line electric field strength, has therefore obtained very high carrier's rate, has suppressed short-channel effect.
Above-described two specific embodiments; to purpose of the present invention, technical scheme and beneficial effect through having gone further description; what it should be noted that is; the above only is specific embodiments of the invention; do not limit the present invention; within the spirit and principles in the present invention all, the modulation of doing and optimization all should be included within protection scope of the present invention.
Claims (5)
1. the structure of vertical asymmetric surrounding-gate MOSFET device is: comprise bottom N-shaped silicon wafer substrate (101), drain region (111) are positioned at the least significant end of device; It is characterized in that: leak expansion area (106) in the upper epitaxial growth of N-shaped silicon wafer substrate (101), channel region (107), and source region (108), gate oxide (109) surrounds whole channel region (107), at the upper depositing polysilicon grid (110) of gate oxide (109).
2. the method for the vertical asymmetric surrounding-gate MOSFET device of making according to claim 1 is characterized in that, mixes for n-in described leakage expansion area (106); Described channel region (107) mixes for p-type; Mix for n+ in described source region (108), drain region (111), doping content is 1 * 10
18～1 * 10
19Cm
-3
3. the method for the vertical asymmetric surrounding-gate MOSFET device of making according to claim 1 is characterized in that, described channel region (107) channel length is 10～20nm.
4. the method for the vertical asymmetric surrounding-gate MOSFET device of making according to claim 1 is characterized in that, described channel region (107) becomes cylinder, and described polysilicon gate (110) becomes circular with gate oxide (109).
5. the manufacture method of vertical asymmetric surrounding-gate MOSFET device is characterized in that may further comprise the steps:
Step 1, the preparation crystal orientation be＜100 N-shaped silicon wafer substrate (101);
Step 2, on N-shaped silicon wafer substrate (101) deposit one deck SiO successively
2Layer (102), SiGe layer (103), and SiO
2Layer (104);
The SiO of step 3, photoetching deposit growth
2Layer (102), SiGe layer (103), and SiO
2Layer (104) makes the SiO of mid portion
2Layer (102), SiGe layer (103) and SiO
2Layer (104) all is etched away, and forms window, take photoresist as masking layer, device is carried out Implantation form drain region (111), rapid thermal annealing activator impurity behind the Implantation;
Step 4, at the upper epitaxial growth silicon epitaxial layers (105) of N-shaped silicon wafer substrate (101), in epitaxial growth, carry out the n-diffusing, doping simultaneously;
Step 5, with SiO
2Layer (104) is stop-layer, and silicon epitaxial layers (105) is carried out chemico-mechanical polishing;
Step 6, device is at first carried out low energy ion inject, form the p-type tagma; Then carry out energetic ion and inject, form n+ type source region, carry out the rapid thermal annealing activator impurity behind the Implantation;
Form successively from top to bottom source region (108) in the silicon epitaxy layer zone behind step 7, the Implantation, channel region (107) and leakage expansion area (106) utilize SiGe and SiO
2Selection in corrosive agent is carried out selective corrosion, then thermal oxide growth one deck SiO on the zone that is corroded than different
2, as gate oxide (109);
Step 8, the SiO to not being corroded
2Layer carries out etching, then at gate oxide (109) outside deposit one deck polysilicon gate (110), and polysilicon gate (110) is carried out the doping of n+ type inject the short annealing activator impurity.
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|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108461517A (en) * | 2017-02-22 | 2018-08-28 | 中电海康集团有限公司 | random access memory and preparation method thereof |
| CN114242790A (en) * | 2019-12-18 | 2022-03-25 | 电子科技大学 | Novel digital gate integrated circuit structure |
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Cited By (2)
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| CN114242790A (en) * | 2019-12-18 | 2022-03-25 | 电子科技大学 | Novel digital gate integrated circuit structure |
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| CN102931237B (en) | 2015-07-22 |
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