CN102931237B - Structure of perpendicular asymmetric ring gating metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method thereof - Google Patents
Structure of perpendicular asymmetric ring gating metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method thereof Download PDFInfo
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- CN102931237B CN102931237B CN201210381165.9A CN201210381165A CN102931237B CN 102931237 B CN102931237 B CN 102931237B CN 201210381165 A CN201210381165 A CN 201210381165A CN 102931237 B CN102931237 B CN 102931237B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title abstract description 4
- 230000005669 field effect Effects 0.000 title abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 25
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000012190 activator Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 10
- 238000004151 rapid thermal annealing Methods 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000005260 corrosion Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000003518 caustics Substances 0.000 claims description 4
- 238000010884 ion-beam technique Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 13
- 230000008569 process Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 210000000746 body region Anatomy 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 31
- 239000000203 mixture Substances 0.000 description 9
- 230000008859 change Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 239000002210 silicon-based material Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000013517 stratification Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention provides a structure of a perpendicular asymmetric ring gating metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method thereof. The structure of the device comprises a bottom-layer n-type silicon wafer substrate 101, wherein a drain region 111 is positioned at the bottommost end of the device; a drain expansion region 106, a channel region 107 and a source region grow on the substrate 101 in an epitaxial manner; a grating oxidization layer 109 encircles the whole channel region 107; and polycrystalline silicon gratings 110 are deposited on the grating oxidization layer 109. The invention provides the structure of the perpendicular asymmetric ring gating MOSFET with a function of effectively suppressing a short channel effect and a manufacturing method of the perpendicular asymmetric ring gating MOSFET; and by the manufacturing method, the technical process can be simplified and the length of the grating and the thickness of a silicon body region can be flexibly controlled.
Description
Technical field
What the present invention relates to is a kind of semiconductor device, the present invention also relates to a kind of formation method of semiconductor device.A kind of structure of vertical asymmetric surrounding-gate MOSFET device and manufacture method thereof specifically.
Background technology
In recent years, along with the develop rapidly of semicon industry, integrated circuit has developed into very large scale integration (ULSI) stage.The size of device is also reduced to nanoscale thereupon, and this is that exploitation new device structure and manufacture craft propose very large challenge.In the past few decades, the size of MOSFET element is always in continuous reduction, and the length of effective channel of now MOSFET element has been less than 10 nanometers.In order to improve constantly the driving force of electric current and better suppress short-channel effect, MOSFET element develops into multiple-grid three-dimension device from traditional single grid planar device.In all multi-gate device, ring grid (Gate-All-Around, GAA) device is best compared to the inhibitory action of other multi-gate device to short-channel effect, and in ring gate device, and cross section is that circular device performance is superior.
The design developing into integrated circuit of nanoscale electronics brings very high complexity, and the cost of the etching system of complexity and costliness.Along with the characteristic size of device constantly reduces, the manufacture craft of conventional MOSFET device is also restricted, and the MOSFET element that therefore investigated vertical stratification carrys out alternative traditional devices.In this device, the sense of current vertically flows to source electrode from drain electrode.It not only simplify the photoetching technique of definition channel region, also maintains the compatibility with standard technology simultaneously.The more important thing is, because active area is positioned at the side of silicon body, its formation double grid easier than planar device or gate-all-around structure.Therefore can suppress short-channel effect, strengthen current driving capability.
But when channel length is reduced to below 50 nanometers, the MOSFET element of vertical stratification can face a severe problem: in order to suppress short-channel effect, channel dopant concentration very highly (must can reach 7.0 × 10
18cm
-3), this can cause very large junction leakage, reduces channel carrier mobility.At employing conventional symmetrical LDD(Lightly Doped Drain) after structure, although channel dopant concentration can be reduced to 3.5 × 10
18cm
-3, but this is less than in the device of 50 nanometers in channel length and still cannot be accepted.In order to address these problems, propose the MOSFET element of asymmetric LDD vertical stratification.Asymmetric LDD structure has and can reduce cut-off leakage current compared with asymmetric LDD structure, reduces electric field near drain junction, suppresses short-channel effect and reduces the advantages such as source series resistance.Mutually compatible with planar CMOS process in manufacture craft, be easy to realize.
In order to solve the problem that device dimensions shrink is brought, investigated the MOSFET element of gradual change channel doping.By the gradual change of channel region doping content, improve source tangent line electric field strength, therefore obtain very high carrier's rate, inhibit short-channel effect.But in traditional planar MOSFET devices, in order to obtain asymmetrical channel doping, wide-angle must be used to inject (large-angle-tilt implant) and complicated photoetching process.Therefore investigated the MOSFET element of the vertical stratification of gradual change channel doping, not only can be mutually compatible with traditional cmos manufacture craft in manufacture craft, and have well suppression short-channel effect ability.Nowadays the nanoscale devices structure proposed has a lot, and the device similar with the present invention has vertical asymmetric double grid MOSFET component and perpendicular rings grid MOSFET component.Compared with the device architecture proposed with the present invention, above two kinds of devices have grid-control scarce capacity and the excessive shortcoming of leakage current respectively.
Summary of the invention
The object of the present invention is to provide a kind of vertical asymmetric surrounding-gate MOSFET structure of effect of effective suppression short-channel effect.The present invention also aims to provide one can simplification of flowsheet, the long manufacture method with the vertical asymmetric surrounding-gate MOSFET of silicon tagma thickness of flexible control gate.
The object of the present invention is achieved like this:
The structure of vertical asymmetric surrounding-gate MOSFET device is: comprise underlying n-type silicon wafer substrate 101, drain region 111 is positioned at the least significant end of device; Leak expansion area 106 at N-shaped silicon wafer substrate 101 Epitaxial growth, channel region 107, and source region 108, gate oxide 109 surrounds whole channel region 107, depositing polysilicon grid 110 on gate oxide 109.
Described leakage expansion area 106 is n-doping; Described channel region 107 is p-type doping; Described source region 108, drain region 111 are n+ doping, and doping content is 1 × 10
18~ 1 × 10
19cm
-3.
Described channel region 107 channel length is 10 ~ 20nm.
Described 107 one-tenth, channel region cylinder, described polysilicon gate 110 is circular with gate oxide 109 one-tenth.
The manufacture method of vertical asymmetric surrounding-gate MOSFET device comprises the following steps:
Step 1, preparation crystal orientation are the N-shaped silicon wafer substrate 101 of <100>;
Step 2, in N-shaped silicon wafer substrate 101 deposit one deck SiO successively
2layer 102, SiGe layer 103, and SiO
2layer 104;
The SiO of step 3, photoetching deposit growth
2layer 102, SiGe layer 103, and SiO
2layer 104, makes the SiO of mid portion
2layer 102, SiGe layer 103 and SiO
2layer 104 is all etched away, and forming window, take photoresist as masking layer, carries out ion implantation form drain region 111, rapid thermal annealing activator impurity after ion implantation to device;
Step 4, at N-shaped silicon wafer substrate 101 Epitaxial growth silicon epitaxial layers 105, simultaneously in epitaxial growth, carry out n-diffusing, doping;
Step 5, with SiO
2layer 104 is stop-layer, carries out chemico-mechanical polishing to silicon epitaxial layers 105;
Step 6, first low energy ion beam implantation is carried out to device, form p-type body district; Then carry out energetic ion injection, form n+ type source region, after ion implantation, carry out rapid thermal annealing activator impurity;
Form source region 108 successively from top to bottom in silicon epitaxy layer region after step 7, ion implantation, channel region 107 and leakage expansion area 106, utilize SiGe and SiO
2selection radio in corrosive agent is different, carries out selective corrosion, then thermal oxide growth one deck SiO on the region be corroded
2, as gate oxide 109;
Step 8, to the SiO be not corroded
2layer etches, and then at gate oxide outside deposit one deck polysilicon gate 110, and carries out n+ type doping injection to polysilicon gate 110, short annealing activator impurity.
The main feature of method of the present invention is as follows:
1) gate-all-around structure is adopted, the whole channel region of gate wraps; 2) vertical channel structure is adopted, long by the flexible control gate of thickness changing SiGe layer; 3) adopt asymmetric LDD structure, reduce electric field near drain junction; 4) grid technique after adopting, first carries out autoregistration doping and forms source region, channel region and drain region, then make gate electrode.Owing to forming source region, channel region and drain region need a series of high temperature processing step, such as ion implantation and annealing, because grid oxygen in after this grid technique avoids the impact being subject to the extraneous factors such as temperature, makes device performance more superior; 5) by being easy to the etching process controlled, controlling silicon tagma thickness flexibly, making it easily to reach fully-depleted, strengthen grid-control ability.
Accompanying drawing explanation
The generalized section of Fig. 1 a kind of vertical asymmetric surrounding-gate MOSFET device disclosed by the invention;
Fig. 2 prepares the schematic diagram of Silicon Wafer;
Fig. 3 is Fig. 2 structure deposit one deck SiO successively
2, SiGe, and SiO
2after sectional view;
Fig. 4 is Fig. 3 structure through the schematic diagram of over etching and ion implantation;
Fig. 5 is the sectional view of Fig. 4 structure after epitaxial silicon material and n-doping;
Fig. 6 is the sectional view of Fig. 5 structure after chemico-mechanical polishing;
Fig. 7 is the schematic diagram that Fig. 6 structure carries out high low energy ion beam implantation;
Fig. 8 is SiO in Fig. 7 structure
2with SiGe layer through selective corrosion and heat growth SiO
2after sectional view;
Fig. 9 is that Fig. 8 structure etches the SiO be not corroded
2with the SiO of polysilicon deposition heat growth
2after sectional view.
Embodiment
Below in conjunction with accompanying drawing citing, the present invention is described in detail:
Specific embodiment one:
Composition graphs 2.Shown preparation crystal orientation is the N-shaped silicon wafer substrate 101 of <100>, and thickness is 100nm.
Composition graphs 3.On N-shaped Silicon Wafer 101, deposit SiO in turn
2layer 102, SiGe layer 103 and SiO
2layer 104.Wherein SiO
2layer 102, SiGe layer 103 and SiO
2the thickness of layer 104 is 20 ~ 50nm.
Composition graphs 4.Photoetching is carried out to Fig. 3 structure, makes the SiO of mid portion
2layer 102, SiGe layer 103 and SiO
2layer 104 is all etched away, and forms window.Then using photoresist as doping masking layer, carry out N-shaped doping to silicon materials and inject, rapid thermal annealing (RTA) activator impurity, forms drain region 111.
Composition graphs 5.Silicon epitaxial layers 105 on silicon materials, the thickness of silicon epitaxial layers 105 is 200 ~ 300nm, carries out n-diffusing, doping in epitaxial growth simultaneously, is formed and leaks expansion area LDD.
Composition graphs 6.With SiO
2layer 104 is stop-layer, carries out chemico-mechanical polishing (CMP) to silicon epitaxial layers 105.
Composition graphs 7.With SiO
2layer 104 is masking layer, first carries out low energy boron ion implantation, forms p-type channel region; Then carry out the injection of high energy arsenic ion, form n+ source region.Then rapid thermal annealing activator impurity is carried out.
Composition graphs 8.Source region 108 is formed successively from top to bottom in silicon epitaxy layer region, channel region 107 and leakage expansion area 106 after ion implantation.Wherein, source region 108 is identical with concentration with the doping type in drain region 111, and be n+ doping, concentration is 1 × 10
18~ 1 × 10
19cm
-3; Leak expansion area 106 for n-doping; Channel region 107 is p-type doping.Due in certain corrosive agent, the corrosion rate of SiGe is far above SiO
2corrosion rate, therefore utilize SiO
2different with the Selection radio of SiGe in this corrosive agent, to SiO
2layer 102, SiGe layer 103 and SiO
2layer 104 carries out selective corrosion, and the thin SiO of SiGe layer 103 place thermal oxide growth eroded
2layer 109, as gate oxide.
Composition graphs 9.Etch away SiO
2layer 102 and SiO
2layer 104, at gate oxide 109 outer outgrowth one deck polycrystalline silicon material 110, as grid material.Carry out the doping of n+ type to polycrystalline silicon material to inject, short annealing activator impurity.
The advantage of embodiment one is: 1) adopt gate-all-around structure, and the effective quantity of grid is maximum, and therefore grid is the strongest to the electricity control of raceway groove, farthest can reduce short-channel effect; 2) adopt vertical channel structure, define channel length without the need to the means of photolithography by complexity, not by the restriction of lithographic accuracy, and working principle and characteristic is almost identical with planar device; 3) adopt asymmetric LDD structure, have compared with asymmetric LDD structure and can reduce cut-off leakage current, reduce electric field near drain junction, suppress short-channel effect and reduce the advantages such as source series resistance.Mutually compatible with planar CMOS process in manufacture craft, be easy to realize; 4) grid technique after adopting, first carries out autoregistration doping and forms source region, channel region and drain region, then make gate electrode.Owing to forming source region, channel region and drain region need a series of high temperature processing step, such as ion implantation and annealing, because grid oxygen in after this grid technique avoids the impact being subject to the extraneous factors such as temperature, makes device performance more superior; 5) by being easy to the etching process controlled, controlling silicon tagma thickness flexibly, making sacrificial oxide layer reach excessive erosion state in actual fabrication process as far as possible, make channel region easily reach fully-depleted, strengthen grid-control ability.
Specific embodiment two:
Step described in other is with specific embodiment one.
Composition graphs 7.With SiO
2layer 104 is masking layer, and first carry out low energy ion beam implantation, Implantation Energy is 20keV, and dosage is 5 × 10
13cm
-2boron ion, to form gradual change raceway groove; Then carry out energetic ion injection, Implantation Energy is 20keV, and dosage is 2 × 10
15cm
-2arsenic ion, to form source region.Then rapid thermal annealing activator impurity is carried out.The doping content of gradual change channel region 107 reduces gradually from source to drain terminal, is 2 × 10
18~ 8 × 10
17cm
-3.
Embodiment two has possessed all advantages of embodiment one, and channel region doping content gradual change, improve source tangent line electric field strength, therefore obtain very high carrier's rate, inhibit short-channel effect.
Above-described two specific embodiments; to object of the present invention, technical scheme and beneficial effect through having gone further description; it should be noted that; the foregoing is only specific embodiments of the invention; do not limit the present invention; within the spirit and principles in the present invention all, the modulation done and optimization, all should be included within protection scope of the present invention.
Claims (1)
1. the manufacture method of vertical asymmetric surrounding-gate MOSFET device, is characterized in that comprising the following steps:
Step 1, preparation crystal orientation are the N-shaped silicon wafer substrate (101) of <100>;
Step 2, in N-shaped silicon wafer substrate (101) deposit one deck SiO successively
2layer (102), SiGe layer (103), and SiO
2layer (104);
The SiO of step 3, photoetching deposit growth
2layer (102), SiGe layer (103), and SiO
2layer (104), makes the SiO of mid portion
2layer (102), SiGe layer (103) and SiO
2layer (104) is all etched away, and forming window, take photoresist as masking layer, carries out ion implantation form drain region (111), rapid thermal annealing activator impurity after ion implantation to device;
Step 4, at N-shaped silicon wafer substrate (101) Epitaxial growth silicon epitaxial layers (105), simultaneously in epitaxial growth, carry out n-diffusing, doping;
Step 5, with SiO
2layer (104) is stop-layer, carries out chemico-mechanical polishing to silicon epitaxial layers (105);
Step 6, first low energy ion beam implantation is carried out to device, form p-type body district; Then carry out energetic ion injection, form n+ type source region, after ion implantation, carry out rapid thermal annealing activator impurity;
Form source region (108) from top to bottom successively in silicon epitaxy layer region after step 7, ion implantation, channel region (107) and leakage expansion area (106), utilize SiGe and SiO
2selection radio in corrosive agent is different, carries out selective corrosion, then thermal oxide growth one deck SiO on the region be corroded
2, as gate oxide (109);
Step 8, to the SiO be not corroded
2layer etches, then at gate oxide (109) outside deposit one deck polysilicon gate (110), and n+ type doping injection is carried out to polysilicon gate (110), short annealing activator impurity, finally obtains vertical asymmetric surrounding-gate MOSFET device.
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| US6027975A (en) * | 1998-08-28 | 2000-02-22 | Lucent Technologies Inc. | Process for fabricating vertical transistors |
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| CN1501503A (en) * | 2002-11-15 | 2004-06-02 | ���ǵ�����ʽ���� | Nonvolatile memory device utilizing a vertical nanotube |
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|---|---|---|---|---|
| US4530149A (en) * | 1982-06-24 | 1985-07-23 | Rca Corporation | Method for fabricating a self-aligned vertical IGFET |
| US5252849A (en) * | 1992-03-02 | 1993-10-12 | Motorola, Inc. | Transistor useful for further vertical integration and method of formation |
| US5414289A (en) * | 1992-03-02 | 1995-05-09 | Motorola, Inc. | Dynamic memory device having a vertical transistor |
| US6027975A (en) * | 1998-08-28 | 2000-02-22 | Lucent Technologies Inc. | Process for fabricating vertical transistors |
| CN1400669A (en) * | 2001-06-26 | 2003-03-05 | 因芬尼昂技术股份公司 | Longitudinal transistor, memory device and longitudinal transistor making process |
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Effective date of registration: 20201201 Address after: Area A129, 4th floor, building 4, Baitai Industrial Park, Yazhou Bay science and Technology City, Yazhou District, Sanya City, Hainan Province, 572024 Patentee after: Nanhai innovation and development base of Sanya Harbin Engineering University Address before: 150001 Heilongjiang, Nangang District, Nantong street,, Harbin Engineering University, Department of Intellectual Property Office Patentee before: HARBIN ENGINEERING University |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150722 Termination date: 20211010 |