CN102945302A - Method for dividing high-filling-rate redundant graph - Google Patents
Method for dividing high-filling-rate redundant graph Download PDFInfo
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- CN102945302A CN102945302A CN2012104324053A CN201210432405A CN102945302A CN 102945302 A CN102945302 A CN 102945302A CN 2012104324053 A CN2012104324053 A CN 2012104324053A CN 201210432405 A CN201210432405 A CN 201210432405A CN 102945302 A CN102945302 A CN 102945302A
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Abstract
The invention provides a method for dividing a high-filling-rate redundant graph, which comprises the following steps of marking out a blank area to be filled with the redundant graph, determining an edge line of the blank area, marking out an edge line of the redundant graph keeping a certain distance away from the inner side of the edge line of the blank area, and obtaining a graph formed by the side edge lines of the redundant graph as the redundant graph, wherein each side edge line of the redundant graph keeps a d distance from the edge line of the corresponding blank area. The method for dividing the high-filling-rate redundant graph can form the redundant graph with a high filling rate, so that the overall graph density uniformity of a map can be improved, the graph density gradient difference of all parts of the map can be reduced, and the uniformity of a silicon wafer subjected to chemical and mechanical grinding and etching can be improved finally.
Description
Technical field
The present invention relates to integrated circuit (IC) design manufacturing technology field, relate in particular to a kind of method of dividing the high fill-ratio redundant pattern.
Background technology
In integrated circuit fabrication process, in order to improve the homogeneity of cmp and etching technics, usually can in needing the layer of cmp or etching, add redundant pattern, and traditional redundant pattern be rectangle or the polygon of fixed measure.
Chinese patent CN102468134A has disclosed a kind of method of utilizing redundant pattern to fill to adjust graphics chip density, but comprises the steps: to obtain the fill area of certain figure layer in the chip preparation; The pattern filling that a default block graphics density does not wait; Be divided into a plurality of pockets, be set in the pattern density of figure layer after filling, the maximum pattern density difference between the minimum figure density value of pocket, maximum pattern density value and adjacent two pockets; Calculate the initial pattern density value of above-mentioned each pocket; The pattern density value of the pocket behind the pattern filling of the pattern density maximum that calculating is inserted; The method that adopts virtual pattern to fill is adjusted the pattern density of each pocket; But the fill area in each pocket is filled, make the pattern density value of filling rear pocket and the pattern density value that step (6) adjusts the most approaching.
This redundant pattern maybe can't be filled in that the white space filling rate of reduced size is very low, thereby causes the pattern density of domain regional area or gradient not to reach target setting, finally causes the homogeneity of silicon chip after cmp and etching to be affected.
Summary of the invention
The present invention is directed to the deficiencies in the prior art part, a kind of method of dividing the high fill-ratio redundant pattern is provided, the redundant pattern of determining by the method has relatively high filling rate, help to improve the pattern density homogeneity of domain integral body, reduce domain pattern density gradient difference everywhere, finally improve the homogeneity of silicon chip after cmp and etching.
To achieve these goals, the invention provides a kind of method of dividing the high fill-ratio redundant pattern, comprise following sequential steps:
At first, mark the white space that needs to fill redundant pattern, determine the sideline of white space; Afterwards, the sideline of marking redundant pattern in the place of the inboard certain distance at a distance of the white space sideline, keeping numerical value between each bar side line of wherein said redundant pattern and the corresponding white space sideline is the distance of d, and last, the figure that is comprised of each bar redundant pattern side line is redundant pattern.
In the preferred embodiment provided by the invention, wherein be defined as a between the relative side in the redundant pattern, the numerical range of described a is 1 ~ 20000 nm.
In the preferred embodiment provided by the invention, the numerical range of wherein said d is 1 ~ 50000nm.
In the preferred embodiment provided by the invention, the numerical value of wherein said a is not less than the minimum main graphic size of main graphic designing requirement in the layer of white space place.
In the preferred embodiment provided by the invention, the numerical value of wherein said d is not less than the minimum main graphic spacing of main graphic designing requirement in the layer of white space place.
The method of division high fill-ratio redundant pattern provided by the invention can form has the high fill-ratio redundant pattern, help to improve the pattern density homogeneity of domain integral body, reduce domain pattern density gradient difference everywhere, finally improve the homogeneity of silicon chip after cmp and etching.
Description of drawings
Fig. 1 is the synoptic diagram that the present invention divides the high fill-ratio redundant pattern.
Fig. 2 is redundant pattern filling effect figure among the present invention.
Embodiment
The invention provides the method for dividing the high fill-ratio redundant pattern, help to improve the pattern density homogeneity of domain integral body, reduce domain pattern density gradient difference everywhere, finally improve the homogeneity of silicon chip after cmp and etching.
By the following examples method provided by the invention is described in further detail, in order to better understand the content of the invention, but the content of embodiment does not limit the scope of innovation and creation protection.
The method of dividing the high fill-ratio redundant pattern comprises following sequential steps:
As shown in Figure 1, at first at main graphic 21,22 layers of white space that marks needs filling redundant pattern, and the sideline of definite white space.Afterwards, in the sideline that redundant pattern 5 is marked in the place of the inboard certain distance at a distance of the white space sideline, maintenance numerical value is the distance of d between wherein said redundant pattern 5 each bar side line and the corresponding white space sideline, and the numerical range of described d is 1 ~ 50000nm.Generally, the numerical value of described d is not less than the minimum main graphic spacing of main graphic designing requirement in the layer of white space place.The numerical value of preferred d is 500,1000,1500 etc.
At last, the figure that will be comprised of each bar redundant pattern side line namely is defined as redundant pattern.Be defined as a in the redundant pattern between the relative side, the numerical range of described a is 1 ~ 20000 nm.The numerical value of described a is not less than the minimum main graphic size of main graphic designing requirement in the layer of white space place.
Redundant pattern filling effect figure as shown in Figure 2, black part is divided into main graphic, oblique line frame and partly is redundant pattern among the figure.Local pattern density reaches 54% after filling, and compares traditional redundant pattern filling effect and improves a lot.The redundant pattern of this high fill-ratio improves the pattern density homogeneity of domain integral body, reduces domain pattern density gradient difference everywhere, finally improves the homogeneity of silicon chip after cmp and etching.
More than specific embodiments of the invention are described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and substituting also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of doing under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (5)
1. a method of dividing the high fill-ratio redundant pattern is characterized in that, comprises following sequential steps:
At first, mark the white space that needs to fill redundant pattern, determine the sideline of white space;
Afterwards, in the sideline that redundant pattern is marked in the place of the inboard certain distance at a distance of the white space sideline, maintenance numerical value is the distance of d between each bar side line of wherein said redundant pattern and the corresponding white space sideline,
At last, the figure that is comprised of each bar redundant pattern side line is redundant pattern.
2. redundant pattern according to claim 1 is characterized in that, is defined as a in the redundant pattern between the relative side, and the numerical range of described a is 1 ~ 20000 nm.
3. redundant pattern according to claim 1 is characterized in that, the numerical range of described d is 1 ~ 50000nm.
4. redundant pattern according to claim 1 is characterized in that, the numerical value of described a is not less than the minimum main graphic size of main graphic designing requirement in the layer of white space place.
5. redundant pattern according to claim 1 is characterized in that, the numerical value of described d is not less than the minimum main graphic spacing of main graphic designing requirement in the layer of white space place.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012104324053A CN102945302A (en) | 2012-11-02 | 2012-11-02 | Method for dividing high-filling-rate redundant graph |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012104324053A CN102945302A (en) | 2012-11-02 | 2012-11-02 | Method for dividing high-filling-rate redundant graph |
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| CN102945302A true CN102945302A (en) | 2013-02-27 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103400014A (en) * | 2013-08-14 | 2013-11-20 | 上海华力微电子有限公司 | Method for improving filling rate of redundant figures in long and narrow zone |
| CN104409445A (en) * | 2014-11-26 | 2015-03-11 | 上海华力微电子有限公司 | Silicon wafer redundant graph filling method and product |
| CN104766785A (en) * | 2015-03-31 | 2015-07-08 | 上海华力微电子有限公司 | Polycrystalline silicon surface deposition area adjusting method |
| CN106096087A (en) * | 2016-05-31 | 2016-11-09 | 上海华虹宏力半导体制造有限公司 | Capture filling graph method |
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| US20070256039A1 (en) * | 2002-06-07 | 2007-11-01 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
| US20100287520A1 (en) * | 2008-09-25 | 2010-11-11 | Fujitsu Limited | Dummy rule generating apparatus |
| CN102446756A (en) * | 2011-11-02 | 2012-05-09 | 上海华力微电子有限公司 | Method for improving homogeneity of figure density of metal layer of silicon chip |
| CN102468134A (en) * | 2010-11-16 | 2012-05-23 | 上海华虹Nec电子有限公司 | Method for adjusting chip graph density using redundancy graph insertion, |
| CN102543853A (en) * | 2011-12-31 | 2012-07-04 | 中国科学院微电子研究所 | Dummy metal filling method and integrated circuit layout structure |
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2012
- 2012-11-02 CN CN2012104324053A patent/CN102945302A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070256039A1 (en) * | 2002-06-07 | 2007-11-01 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
| US20100287520A1 (en) * | 2008-09-25 | 2010-11-11 | Fujitsu Limited | Dummy rule generating apparatus |
| CN102468134A (en) * | 2010-11-16 | 2012-05-23 | 上海华虹Nec电子有限公司 | Method for adjusting chip graph density using redundancy graph insertion, |
| CN102446756A (en) * | 2011-11-02 | 2012-05-09 | 上海华力微电子有限公司 | Method for improving homogeneity of figure density of metal layer of silicon chip |
| CN102543853A (en) * | 2011-12-31 | 2012-07-04 | 中国科学院微电子研究所 | Dummy metal filling method and integrated circuit layout structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103400014A (en) * | 2013-08-14 | 2013-11-20 | 上海华力微电子有限公司 | Method for improving filling rate of redundant figures in long and narrow zone |
| CN104409445A (en) * | 2014-11-26 | 2015-03-11 | 上海华力微电子有限公司 | Silicon wafer redundant graph filling method and product |
| CN104766785A (en) * | 2015-03-31 | 2015-07-08 | 上海华力微电子有限公司 | Polycrystalline silicon surface deposition area adjusting method |
| CN106096087A (en) * | 2016-05-31 | 2016-11-09 | 上海华虹宏力半导体制造有限公司 | Capture filling graph method |
| CN106096087B (en) * | 2016-05-31 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | Capture filling graph method |
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Application publication date: 20130227 |