CN102969272A - Semiconductor device and production method thereof - Google Patents
Semiconductor device and production method thereof Download PDFInfo
- Publication number
- CN102969272A CN102969272A CN201110255990XA CN201110255990A CN102969272A CN 102969272 A CN102969272 A CN 102969272A CN 201110255990X A CN201110255990X A CN 201110255990XA CN 201110255990 A CN201110255990 A CN 201110255990A CN 102969272 A CN102969272 A CN 102969272A
- Authority
- CN
- China
- Prior art keywords
- metal
- hard mask
- dielectric layer
- redundancy metal
- metallic channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a semiconductor device and a production method thereof. The method comprises steps of providing a semiconductor substrate; forming a dielectric layer and a hard mask layer on the semiconductor substrate; removing the hard mask layer on a non-redundant metal area; etching the dielectric layer and the residual hard mask layer so as to form a redundant metal slot and a metal wire slot, wherein the depth of the redundant metal slot is less than that of the metal wire slot; depositing metal layers in the redundant metal slot and the metal wire slot and on the dielectric layer; and conducting the chemical mechanical polishing process till the surface of the dielectric layer is exposed and forming redundant metal and a metal wire, wherein the height of the redundant metal is less than that of the metal wire. By the aid of the method, the depth of the redundant metal slot is less than that of the metal wire slot. Compared with the prior art, the thickness (height) of the redundant metal is reduced, and coupling capacitance in metal layers and among metal layers, which is introduced through the filling of the redundant metal, is reduced effectively.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of semiconductor device and preparation method thereof.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled thereupon.After entering into 130 nm technology node, be subject to the restriction of the high-ohmic of aluminium, copper-connection gradually substitution of Al interconnection becomes metal interconnected main flow.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper interconnecting line can not obtain by etching sheet metal that as aluminum interconnecting the manufacture method of the copper interconnecting line that extensively adopts now is the embedding technique that is called Damascus technics.This Damascus technics comprises single Damascus technics of only making plain conductor and makes simultaneously the dual damascene process of through hole (also claiming contact hole) and plain conductor.Specifically, single damascene structure (also claiming single inlay structure) only is that the production method of single-layer metal wire is changed into mosaic mode (dielectric layer etching+metal filled) by traditional mode (metal etch+dielectric layer is filled), dual-damascene structure then is that through hole and plain conductor are combined, and so only needs together metal filled step.The common method of making dual-damascene structure generally has following several: all-pass hole precedence method (Full VIA First), half through hole precedence method (Partial VIA First), plain conductor precedence method (Full Trench First) and self aligned approach (Self-alignment method).
As shown in Figure 1, existing a kind of plain conductor manufacture craft comprises the steps: at first, metallization medium layer 110 at first on Semiconductor substrate 100; Then in dielectric layer 110, form metallic channel by photoetching and etching technics; Depositing metal layers subsequently, described metal level are filled in the metallic channel and on described dielectric layer 110 surfaces and have also deposited metal; Then, carry out cmp (CMP) technique and remove metal on the described dielectric layer 110, thereby in described metallic channel, made plain conductor 140.
As mentioned above, in Damascus technics, need to utilize chemical mechanical milling tech, be embedded in plain conductor 140 in the dielectric layer 110 with final formation.Yet, because the removal rate of metal and dielectric layer material is generally not identical, therefore can causes the depression (dishing) of not expecting and corrode (erosion) phenomenon the selectivity of grinding.Depression often occurs in metal and goes down to the plane of contiguous dielectric layer or exceed more than the plane of contiguous dielectric layer, and corroding then is that the part of dielectric layer is excessively thin.Depression and erosion are subject to the structure of figure and the Effects of Density of figure.Therefore, in order to reach uniform grinding effect, require the metallic pattern density on the Semiconductor substrate even as far as possible, and the metallic pattern density of product design usually can not satisfy the requirement of the cmp uniformity.At present, solution is to fill the pattern density homogenizing that the redundancy metal pattern makes domain at the white space of domain, thereby also forms redundancy metal (dummy metal) 150 when forming plain conductor 140 in dielectric layer 110, as shown in Figure 2.But, although redundancy metal has improved the uniformity of pattern density, but introduced inevitably in the extra metal level and the coupling capacitance of metal interlevel.
Summary of the invention
The invention provides a kind of semiconductor device and preparation method thereof, fill in the metal level of introducing and the coupling capacitance of metal interlevel effectively to reduce redundancy metal.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of semiconductor device, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Form dielectric layer and hard mask layer in described Semiconductor substrate;
Remove the hard mask layer on the described nonredundancy metal area;
The described dielectric layer of etching and remaining hard mask layer are to form redundancy metal groove and metallic channel, and the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer; And
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
Optionally, in the manufacture method of described semiconductor device, utilize the mode of photoetching and etching to remove hard mask layer on the described nonredundancy metal area.
Optionally, in the manufacture method of described semiconductor device, the described dielectric layer of etching and remaining hard mask layer comprise with the step that forms redundancy metal groove and metallic channel: dielectric layer and the remaining hard mask layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form simultaneously redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
Optionally, in the manufacture method of described semiconductor device, the described dielectric layer of etching and remaining hard mask layer comprise with the step that forms redundancy metal groove and metallic channel: the dielectric layer on the described nonredundancy metal area of etching forms through hole; Dielectric layer and the remaining hard mask layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form simultaneously redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
Optionally, in the manufacture method of described semiconductor device, the material of described hard mask layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide, and described dielectric layer is the low k dielectric layer.
The present invention also provides the manufacture method of another kind of semiconductor device, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Form dielectric layer and hard mask layer in described Semiconductor substrate;
The described hard mask layer of etching is to form hard mask metallic channel and hard mask redundancy metal groove, and the degree of depth of described hard mask redundancy metal groove is less than the degree of depth of described hard mask metallic channel;
Dielectric layer on the etching nonredundancy metal area forms through hole with the position at hard mask metallic channel;
Dielectric layer and the remaining hard mask layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
Depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer; And
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
Optionally, in the manufacture method of described semiconductor device, form first described hard mask metallic channel, form again described hard mask redundancy metal groove.
Optionally, in the manufacture method of described semiconductor device, form first described hard mask redundancy metal groove, form again described hard mask metallic channel.
Optionally, in the manufacture method of described semiconductor device, the material of described hard mask layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide, and described dielectric layer is the low k dielectric layer.
The present invention also provides a kind of semiconductor device, comprising: Semiconductor substrate; Be formed at the dielectric layer on the described Semiconductor substrate; Be formed at redundancy metal and plain conductor in the described dielectric layer, the height of described redundancy metal is less than the height of described plain conductor.
The present invention is after metallization medium layer, first form hard mask layer at described dielectric layer, make the degree of depth of redundancy metal groove of formation less than the degree of depth of metallic channel, therefore the height of the final redundancy metal that forms is less than the height of plain conductor, compared with prior art reduced the thickness (highly) of redundancy metal, can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Description of drawings
Fig. 1 is the structural representation of existing a kind of semiconductor device;
Fig. 2 is the structural representation of existing another kind of semiconductor device;
Fig. 3 is the schematic flow sheet of manufacture method of the semiconductor device of the embodiment of the invention one;
Fig. 4 A～4E is the cross-sectional view of device corresponding to each step in the manufacture method of semiconductor device of the embodiment of the invention one;
Fig. 5 A～5F is the cross-sectional view of device corresponding to each step in the manufacture method of semiconductor device of the embodiment of the invention two;
Fig. 6 A～6F is the cross-sectional view of device corresponding to each step in the manufacture method of semiconductor device of the embodiment of the invention three.
Embodiment
Mention that in background technology although redundancy metal has improved the uniformity of pattern density, but introduced in the extra metal level and the coupling capacitance of metal interlevel, electric capacity can be calculated by following formula:
Wherein, ε
0Be permittivity of vacuum; ε
rBe the medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.This shows, reduce the relative area of metal and increase intermetallic apart from reducing electric capacity.That is to say that the volume that reduces redundancy metal can reduce the extra intermetallic coupling capacitance introduced owing to adding redundancy metal.
For this reason, the present invention makes the degree of depth of redundancy metal groove less than the degree of depth of metallic channel, therefore the height of the final redundancy metal that forms is less than the height of plain conductor, compared with prior art reduced the thickness (highly) of redundancy metal, can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
The present invention also provides a kind of semiconductor device, comprising: Semiconductor substrate; Be formed at the dielectric layer on the Semiconductor substrate; And be formed at redundancy metal and plain conductor in the dielectric layer, the height of described redundancy metal is less than the height of described plain conductor, compared with prior art reduced the thickness of redundancy metal, can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Embodiment one
Please refer to Fig. 3, it is the schematic flow sheet of the manufacture method of semiconductor device of the present invention.As shown in Figure 3, the manufacture method of described semiconductor device comprises the steps:
Step S310: Semiconductor substrate is provided, and Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Step S320: form dielectric layer and hard mask layer in described Semiconductor substrate;
Step S330: remove the hard mask layer on the described nonredundancy metal area;
Step S340: the described dielectric layer of etching and remaining hard mask layer are to form redundancy metal groove and metallic channel, and the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Step S350: depositing metal layers in redundancy metal groove and metallic channel and on the dielectric layer;
Step S360: carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
Do further to describe in detail below in conjunction with the manufacturing method of semiconductor device that generalized section proposes present embodiment respectively.
Shown in Fig. 4 A, at first, shown in step S310, Semiconductor substrate 400 is provided, this Semiconductor substrate 400 comprises redundancy metal district 402 and nonredundancy metal area 401, described redundancy metal district 402 is in order to form redundancy metal, and the semiconductor substrate region outside the described redundancy metal district 402 is nonredundancy metal area 401.Wherein, be formed with metal line in the described Semiconductor substrate 400, because the present invention relates generally to the manufacture craft of metal damascene structure, thus will not introduce the process that in Semiconductor substrate 400, forms metal line, but those skilled in the art are still this and know.
Then, form dielectric layer 410 in Semiconductor substrate 400, described dielectric layer 410 is preferably low-k (K) dielectric layer, postpones with the resistance capacitance that reduces its parasitic capacitance and metallic copper, satisfies the requirement of Quick conductive.Better, it is black diamond (black diamond that described dielectric layer 410 adopts the trade mark of Material Used (Applied Materials) company, BD) silicon oxide carbide, perhaps adopt the Coral material of Novellus company, again or adopt and to utilize spin coating process to make the Silk advanced low-k materials of Dow Corning Corporation etc.
In other embodiments of the invention, before described Semiconductor substrate 400 forms dielectric layer 410, also can form first etching stop layer (not shown), described etching stop layer can be used for preventing that the metal in the metal line is diffused in the dielectric layer 410, and described etching stop layer can prevent that also the metal line in the Semiconductor substrate 400 is etched in follow-up etching process of carrying out in addition.The material of described etching stop layer for example is silicon nitride, and the dielectric layer of itself and follow-up formation has preferably adhesiveness.
Continue with reference to figure 4A, then, form hard mask layer 430 at described dielectric layer 410, the material of described hard mask layer 430 can be a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide, and described hard mask layer 430 can utilize physical vapour deposition (PVD) (PVD) or chemical vapour deposition (CVD) (CVD) technology to form.Wherein, the thickness of described hard mask layer 430 metallic channel 412 that is follow-up formation and redundancy metal groove 411 degree of depth (highly) is poor.
Shown in Fig. 4 B, thereafter, utilize photoetching and etching technics to remove hard mask layer on the described nonredundancy metal area 401, and only keep the hard mask layer in the redundancy metal district 402.
Shown in Fig. 4 C, utilize photoetching process to form the mask layer with metallic channel pattern and redundancy metal groove pattern at dielectric layer 410, and take described mask layer as mask, the described dielectric layer 410 of etching and remaining hard mask layer, form metallic channel 412 and redundancy metal groove 411, owing to be coated with hard mask layer in the described redundancy metal district, therefore although be in this step etching simultaneously, but the degree of depth of the final redundancy metal groove 411 that forms will be less than the degree of depth of metallic channel 412, the difference of described metallic channel 412 and redundancy metal groove 411 degree of depth (highly) is the thickness of hard mask layer, then removes described mask layer.The height of described redundancy metal groove 412 can change accordingly according to concrete technology, and the present invention also will not limit this.
Shown in Fig. 4 D, subsequently, to described redundancy metal groove 411 and metallic channel 412 interior depositing metal layers 420, because the characteristic of depositing operation also can deposit metal on this process medium layer 410, the material of wherein said metal level 420 is copper.
Shown in Fig. 4 E, subsequently, carry out cmp (CMP) technique until expose the surface of dielectric layer 410, with at redundancy metal groove 411 interior formation redundancy metals 421, and at metallic channel 412 interior plain conductors 422, the height of described redundancy metal 421 is less than the height of plain conductor 422.Owing to make the degree of depth of redundancy metal groove 411 less than the degree of depth of metallic channel 412, therefore the height of the final redundancy metal 421 that forms is less than the height of plain conductor 422, compared with prior art reduced the height (thickness) of redundancy metal 421, filled in the metal level of introducing and the coupling capacitance of metal interlevel thereby reduced redundancy metal.
Embodiment two
Shown in Fig. 5 A, at first, provide Semiconductor substrate 500, this Semiconductor substrate 500 comprises redundancy metal district 502 and nonredundancy metal area 501, forms dielectric layer 510 in Semiconductor substrate 500 subsequently.Then, form hard mask layer 530 at described dielectric layer 510.
Shown in Fig. 5 B, thereafter, utilize photoetching and etching technics to remove hard mask layer on the described nonredundancy metal area 501, and only keep the hard mask layer in the redundancy metal district 502.
Shown in Fig. 5 C, utilize photoetching process to form the first mask layer with through-hole pattern at dielectric layer 510, and take described the first mask layer as mask, dielectric layer on the described nonredundancy metal area 501 of etching, thereby form through hole 513 at the nonredundancy metal area, and then remove described the first mask layer.
Shown in Fig. 5 D, subsequently, form the second mask layer with metallic channel pattern and redundancy metal groove pattern at described dielectric layer 510, and take described the second mask layer as mask, dielectric layer and the remaining hard mask layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form redundancy metal groove 511, and at through hole 513 correspondence positions formation metallic channel 512, owing to be coated with hard mask layer in the described redundancy metal district 502, therefore the degree of depth of the final redundancy metal groove 511 that forms is less than the degree of depth of metallic channel 512.
Shown in Fig. 5 E, subsequently, to described redundancy metal groove 511 and metallic channel 512 interior depositing metal layers 520, because the characteristic of depositing operation also can deposit metal on this process medium layer 510.
Shown in Fig. 5 F, subsequently, carry out chemical mechanical milling tech until expose the surface of dielectric layer 510, with at redundancy metal groove 511 interior formation redundancy metals 521, and at metallic channel 512 interior plain conductors 522, the height of described redundancy metal 521 is less than the height of plain conductor 522, therefore the height of the final redundancy metal 521 that forms is less than the height of plain conductor 522, namely compared with prior art reduced the height of redundancy metal 521, effectively reduced redundancy metal and filled in the metal level of introducing and the coupling capacitance of metal interlevel.
Embodiment three
As shown in Figure 6A, at first, provide Semiconductor substrate 600, this Semiconductor substrate 600 comprises redundancy metal district 602 and nonredundancy metal area 601, forms dielectric layer 610 in Semiconductor substrate 600 subsequently, and forms hard mask layer 630 at dielectric layer 610.
Shown in Fig. 6 B, subsequently, the described hard mask layer 630 of etching, to form hard mask metallic channel 632 and hard mask redundancy metal groove 631, the degree of depth of described hard mask redundancy metal groove 631 is less than the degree of depth of described hard mask metallic channel 632.In the present embodiment, utilize first photoetching and etching technics to form hard mask metallic channel 632, and then utilize photoetching and etching technics to form hard mask redundancy metal groove 631.In other specific embodiment of the present invention, can also form first hard mask redundancy metal groove 631, and then form hard mask metallic channel 632.
Shown in Fig. 6 C, thereafter, etching dielectric layer 610 forms through hole 613 with the position at hard mask metallic channel 632, and described hard mask metallic channel 632 has played the effect of autoregistration (Self-alignment).
Shown in Fig. 6 D, then, dielectric layer and the remaining hard mask layer on etching described redundancy metal district 602 and the nonredundancy metal area 601 simultaneously, form metallic channel 612 with the position at through hole 613, and at redundancy metal district formation redundancy metal groove 611, because the degree of depth of described hard mask redundancy metal groove 631 is less than the degree of depth of described hard mask metallic channel 632, therefore the degree of depth of the final described redundancy metal groove 611 that forms is less than the degree of depth of metallic channel 612.
Shown in Fig. 6 E, subsequently, to redundancy metal groove 611 and metallic channel 612 interior depositing metal layers 620, because the characteristic of depositing operation also can deposit metal on this process medium layer 610.
Shown in Fig. 6 F, subsequently, carry out chemical mechanical milling tech until expose the surface of described dielectric layer 610, with at redundancy metal groove 611 interior formation redundancy metals 621, and at metallic channel 612 interior plain conductors 622, the height of described redundancy metal 621 is less than the height of described plain conductor 622, because the height of the final redundancy metal 621 that forms is less than the height of plain conductor 622, namely compared with prior art reduced the height (thickness) of redundancy metal 621, therefore can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Need to prove that each embodiment adopts the mode of going forward one by one to describe in this specification, each embodiment stresses is difference with other embodiment, the mutually reference of relevant part.And accompanying drawing all adopts the form of simplifying very much and all uses non-accurately ratio, only is used for purpose convenient, each embodiment of lucidly aid illustration the present invention.
In addition, although below describe the present invention in detail as an example of the dual damascene metal interconnect structure (referring to embodiment three) of the dual damascene metal interconnect structure (referring to embodiment two) of single Damascus metal interconnect structure (referring to embodiment one), through hole elder generation etching and the first etching of the hard mask groove of self-alignment type example respectively, those skilled in the art can also carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (12)
1. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Form dielectric layer and hard mask layer in described Semiconductor substrate;
Remove the hard mask layer on the described nonredundancy metal area;
The described dielectric layer of etching and remaining hard mask layer are to form redundancy metal groove and metallic channel, and the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer; And
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, utilizes the mode of photoetching and etching to remove hard mask layer on the described nonredundancy metal area.
3. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the described dielectric layer of etching and remaining hard mask layer comprise with the step that forms redundancy metal groove and metallic channel:
Dielectric layer and the remaining hard mask layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form simultaneously redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the described dielectric layer of etching and remaining hard mask layer comprise with the step that forms redundancy metal groove and metallic channel:
Dielectric layer on the described nonredundancy metal area of etching forms through hole;
Dielectric layer and the remaining hard mask layer on etching described redundancy metal district and the nonredundancy metal area simultaneously, to form simultaneously redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel.
5. such as the manufacture method of the described semiconductor device of any one in the claim 1 to 4, it is characterized in that the material of described hard mask layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.
6. such as the manufacture method of the described semiconductor device of any one in the claim 1 to 4, it is characterized in that described dielectric layer is the low k dielectric layer.
7. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Form dielectric layer and hard mask layer in described Semiconductor substrate;
The described hard mask layer of etching is to form hard mask metallic channel and hard mask redundancy metal groove, and the degree of depth of described hard mask redundancy metal groove is less than the degree of depth of described hard mask metallic channel;
Dielectric layer on the etching nonredundancy metal area forms through hole with the position at hard mask metallic channel;
Dielectric layer and the remaining hard mask layer on etching redundancy metal district and the nonredundancy metal area simultaneously, to form redundancy metal groove and metallic channel, the degree of depth of described redundancy metal groove is less than the degree of depth of metallic channel;
Depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
8. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, forms first described hard mask metallic channel, forms described hard mask redundancy metal groove again.
9. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, forms first described hard mask redundancy metal groove, forms described hard mask metallic channel again.
10. such as the manufacture method of the described semiconductor device of any one in the claim 7 to 9, it is characterized in that the material of described hard mask layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.
11. the manufacture method such as the described semiconductor device of any one in the claim 7 to 9 is characterized in that, described dielectric layer is the low k dielectric layer.
12. a semiconductor device that utilizes claim 1 or 7 described methods to form is characterized in that, comprising: Semiconductor substrate; Be formed at the dielectric layer on the described Semiconductor substrate; And being formed at redundancy metal and plain conductor in the described dielectric layer, the height of described redundancy metal is less than the height of described plain conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110255990XA CN102969272A (en) | 2011-08-31 | 2011-08-31 | Semiconductor device and production method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110255990XA CN102969272A (en) | 2011-08-31 | 2011-08-31 | Semiconductor device and production method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102969272A true CN102969272A (en) | 2013-03-13 |
Family
ID=47799329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110255990XA Pending CN102969272A (en) | 2011-08-31 | 2011-08-31 | Semiconductor device and production method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102969272A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112447514A (en) * | 2019-08-28 | 2021-03-05 | 芯恩（青岛）集成电路有限公司 | Metal hard mask, multilayer interconnection structure and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030092260A1 (en) * | 2001-11-15 | 2003-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a dual damascene aperture while employing a peripherally localized intermediate etch stop layer |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
-
2011
- 2011-08-31 CN CN201110255990XA patent/CN102969272A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030092260A1 (en) * | 2001-11-15 | 2003-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a dual damascene aperture while employing a peripherally localized intermediate etch stop layer |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112447514A (en) * | 2019-08-28 | 2021-03-05 | 芯恩（青岛）集成电路有限公司 | Metal hard mask, multilayer interconnection structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2003168738A (en) | Semiconductor element and method of manufacturing it | |
| CN102446827A (en) | Manufacture process of removing redundant metal filling of metal layer | |
| JP2002289691A (en) | Method of forming dual-damascene interconnection and structure using the method | |
| CN102779782A (en) | Preparation process of dual damascene shallow dummy metal | |
| US7041574B2 (en) | Composite intermetal dielectric structure including low-k dielectric material | |
| CN102339790A (en) | Manufacture method of semiconductor device | |
| CN102324399B (en) | Semiconductor device and manufacturing method thereof | |
| TWI707401B (en) | Fully aligned via in ground rule region | |
| CN102969270A (en) | Semiconductor device and production method thereof | |
| CN102522367A (en) | Manufacturing method of integrated circuit with ultra-thick top-layer metal and integrated circuit | |
| CN102969271A (en) | Semiconductor device and production method thereof | |
| CN102339791B (en) | Manufacture method of semiconductor device | |
| CN102354682B (en) | Method for manufacturing semiconductor device | |
| CN102339792A (en) | Manufacture method of semiconductor device | |
| CN102969272A (en) | Semiconductor device and production method thereof | |
| CN102339793A (en) | Manufacture method of semiconductor device | |
| CN102693935A (en) | Manufacturing method of interconnection structure | |
| CN104022070A (en) | Forming method of interconnection structure | |
| CN102361019A (en) | Method for manufacturing semiconductor device | |
| CN103474387B (en) | The method of airspace is formed between groove | |
| CN102969269A (en) | Semiconductor device and production method thereof | |
| CN102412198B (en) | Semiconductor device fabrication method | |
| KR100905828B1 (en) | Metal line of semiconductor device and forming method thereof | |
| CN102420181A (en) | Production method of semiconductor device | |
| CN102347273B (en) | Semiconductor device producing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130313 |