CN102969274A - Method for forming copper Damascus structure - Google Patents
Method for forming copper Damascus structure Download PDFInfo
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- CN102969274A CN102969274A CN2012104309068A CN201210430906A CN102969274A CN 102969274 A CN102969274 A CN 102969274A CN 2012104309068 A CN2012104309068 A CN 2012104309068A CN 201210430906 A CN201210430906 A CN 201210430906A CN 102969274 A CN102969274 A CN 102969274A
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- interlayer dielectric
- sacrifice layer
- copper
- tantalum
- titanium
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Abstract
The invention provides a method for forming a copper Damascus structure. The method comprises steps of depositing an interlayer dielectric and a sacrifice layer on a substrate, and graphing photosensitive resist; regarding the graphed photosensitive resist as a mask, etching the interlayer dielectric and the sacrifice layer and forming a metal interconnection line groove; depositing a barrier layer and a metal interconnection line in the groove sequentially; and removing excess copper, the sacrifice layer and the barrier layer through the chemical mechanical planarization process and finally forming the copper Damascus structure. Therefore, by the aid of the method, the sacrifice layer is deposited on the interlayer dielectric, a prior dielectric anti-reflection coating is replaced, the standing wave effect of the photosensitive resist is reduced, and the lithographic performance is improved. The sacrifice layer serves as a sacrifice layer of the etching process, the loss of the interlayer dielectric in the copper Damascus structure is reduced, the thickness of the metal interconnection line is increased, is stable and can be controlled, and the controllability and the stability of wafer electrical properties can be improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, relate in particular to a kind of formation method of copper damascene structure.
Background technology
Along with constantly reducing of semiconductor integrated circuit size, for signal cross-talk and the RC that reduces integrated circuit postpones, in the semiconductor chip manufacturing, often come substitution of Al as metal interconnecting wires with the less copper of resistivity.But because copper interconnecting line can not use the dry etching technology, so, usually adopt chemical-mechanical planarization (Chemical Mechanical Planarization is called for short CMP) method to remove unnecessary copper, to form copper interconnecting line.
At present, in the process by CMP technique planarization copper, often adopt a kind of lapping liquid of removing simultaneously barrier layer and dielectric medium antireflecting coating.Yet, in the removal process, because inhomogeneity difference and barrier layer lapping liquid commonly used can not have good selection ratio to interlayer dielectric and dielectric medium antireflecting coating in the sheet of wafer, can cause the interlayer dielectric of copper damascene structure lower floor to be crossed and grind, cause dielectric loss.
The formation method of copper damascene structure in the prior art is by making first substrate.Then, in interlayer dielectric, form metal interconnected line trenches.Afterwards, by the modes such as deposit, plating from bottom to top successively barrier layer and copper metal on metal interconnected line trenches and substrate.At last, remove unnecessary copper metal and barrier layer by chemical-mechanical planarization technique, just obtain the copper metal interconnecting wires.Its concrete steps are as follows:
Step 1, as shown in Figure 1, on substrate 102, by plasma enhanced CVD technique, from bottom to top successively deposit one deck interlayer dielectric 202 and dielectric medium antireflecting coating 203.Usually, dielectric medium antireflecting coating 303 is that the form with thin layer is deposited on the interlayer dielectric layer 202, can be 600A-1200A according to technological requirement thickness.Wherein, the material of interlayer dielectric 202 is Si oxides, and the material of dielectric medium antireflecting coating 203 is silicon nitrogen oxide, and further, the material of described dielectric medium antireflecting coating 203 can be SiON, TEOS.Then, on dielectric medium antireflecting coating 203, form photoresist 204 by coating method, and adopt photoetching technique above photoresist 204, to form figure.
In the formation method of prior art copper damascene structure, often adopt a kind of lapping liquid that can remove simultaneously barrier layer and dielectric medium antireflecting coating.Yet the barrier polishing solution of cmp polishes the selection ratio preferably to interlayer dielectric and dielectric medium antireflecting coating.So in CMP (Chemical Mechanical Polishing) process, can cause interlayer dielectric loss 207, as shown in Figure 7.Because the loss of interlayer dielectric causes that the copper metal interconnecting wires thickness in the interlayer dielectric reduces, and causes the resistivity of wafer higher, the electrical defects such as electric leakage poor performance.
Therefore, in CMP (Chemical Mechanical Polishing) process, how reducing the interlayer dielectric loss in the copper damascene structure, to improve controllability and the stability of wafer electric property, is present industry urgent problem.
Summary of the invention
Main purpose of the present invention is, for the problems referred to above, a kind of formation method of copper damascene structure has been proposed, the method replaces original dielectric medium antireflecting coating by deposit one deck sacrifice layer on interlayer dielectric, thereby can reduce the loss of the interlayer dielectric in the copper damascene structure, improve controllability and the stability of wafer electric property.
For reaching above-mentioned purpose, the invention provides a kind of formation method of copper damascene structure, described method comprises the steps:
Step S1: on substrate, sequentially form interlayer dielectric, sacrifice layer and photoresist, and graphical described photoresist, wherein, the material of described sacrifice layer is the combination of one or more materials in silicon nitride or silicon nitride and tantalum, tantalum nitride, titanium, the titanium nitride;
Step S2: take patterned photoresist as mask, the sequentially described sacrifice layer of etching and interlayer dielectric are to form metal interconnected line trenches in described interlayer dielectric;
Step S3: barrier layer in described metal interconnected line trenches, fill the copper metal, to form metal interconnecting wires;
Step S4: by chemical-mechanical planarization technique, remove unnecessary copper, barrier layer and sacrifice layer, finally form the copper damascene structure.
Preferably, described interlayer dielectric forms by chemical vapor deposition method, and wherein, the material of described interlayer dielectric is Si oxide.
Preferably, described sacrifice layer forms by the physics and chemistry vapor deposition process.
Preferably, in the described sacrifice layer in tantalum, tantalum nitride, titanium, the titanium nitride thickness of one or more materials be 200 dusts-400 dusts.
Preferably, the thickness of silicon nitride is 150 dusts-200 dusts in the described sacrifice layer.
Preferably, described graphical described photoresist is realized by photoetching.
Preferably, described etching sacrificial layer and interlayer dielectric are carried out etching by plasma etching industrial.
Preferably, described barrier layer forms by physical gas-phase deposition, and wherein, the material on described barrier layer is tantalum/tantalum nitride or titanium/titanium nitride; Described metal interconnecting wires forms by Cu electroplating technique.
Preferably, the removal of described barrier layer and sacrifice layer is to adopt Si oxide removal selection is polished than large barrier polishing solution.
Can find out from technique scheme, the formation method of a kind of copper damascene structure of the present invention, deposit one deck sacrifice layer replaces original dielectric medium antireflecting coating on interlayer dielectric.Can reduce the standing wave effect of photoresist, improve lithography performance; Again can be as the sacrifice layer in the etch process, reduce the loss of the interlayer dielectric in the copper damascene structure, so that the thickness of metal interconnecting wires increases and stablizes is controlled, improved controllability and the stability of wafer electric property.
Description of drawings
Fig. 1 ~ 7 are the concrete steps schematic diagram of the formation method of copper damascene structure in the prior art;
Fig. 8 is the schematic flow sheet of a preferred embodiment of the formation method of copper damascene structure of the present invention;
Fig. 9 ~ 15 are the concrete steps schematic diagram of the formation method of copper damascene structure of the present invention.
Embodiment
Some exemplary embodiments that embody feature ﹠ benefits of the present invention will be described in detail in the explanation of back segment.Be understood that the present invention can have in different examples various variations, its neither departing from the scope of the present invention, and explanation wherein and be shown in the usefulness that ought explain in essence, but not in order to limit the present invention.
Above-mentioned and other technical characterictic and beneficial effect are elaborated to the formation method of copper damascene structure of the present invention in connection with embodiment and accompanying drawing 8-15.
Now 8-15 by reference to the accompanying drawings progressively describes in detail by the formation method of a specific embodiment to copper damascene structure of the present invention.
Fig. 8 is the schematic flow sheet of a preferred embodiment of the formation method of copper damascene structure of the present invention.In the present embodiment, the formation method of copper damascene structure comprises step S1 ~ S4, and step S1 ~ S4 passes through respectively accompanying drawing 9 ~ 15, formed structure during with the described formation method of explanation Fig. 8 of the present invention concrete steps.
See also Fig. 8, as shown in the figure, in this embodiment of the present invention, the formation method of copper damascene structure comprises the steps:
Step S1: see also Fig. 9, on substrate 102, by chemical vapor deposition method deposit one deck interlayer dielectric 202, in the present embodiment, the material of interlayer dielectric 202 is Si oxides; This substrate 102 can be through-hole interconnection part in the copper damascene structure, also can be the lower metal interconnection layer, and it comprises medium between metal interconnecting wires and metal interconnecting wires.
Then, on interlayer dielectric 202, form sacrifice layer 212 by the physics and chemistry vapor deposition process, further, the material of sacrifice layer 212 is silicon nitride or silicon nitride and tantalum, tantalum nitride, titanium, the combination of one or more materials in the titanium nitride, concrete, the material of sacrifice layer 212 can be silicon nitride, perhaps tantalum and silicon nitride, perhaps tantalum nitride and silicon nitride, perhaps titanium and silicon nitride, perhaps titanium nitride and silicon nitride, perhaps tantalum, tantalum nitride and silicon nitride, perhaps tantalum, titanium and silicon nitride, perhaps tantalum, titanium nitride and silicon nitride, perhaps tantalum nitride, titanium and silicon nitride, perhaps tantalum nitride, titanium nitride and silicon nitride, perhaps titanium, titanium nitride and silicon nitride, perhaps tantalum, tantalum nitride, titanium and silicon nitride, perhaps tantalum, tantalum nitride, titanium nitride and silicon nitride, perhaps tantalum nitride, titanium, titanium nitride and silicon nitride, perhaps tantalum, tantalum nitride, titanium, titanium nitride and silicon nitride etc.Preferably, in described sacrifice layer 212, described silicon nitride is arranged on described tantalum, tantalum nitride, titanium, one or more materials of titanium nitride.In the present embodiment, one or more materials form by physical gas-phase deposition in tantalum in these sacrifice layer 212 materials, tantalum nitride, titanium, the titanium nitride, preferably, in this sacrifice layer 212 in tantalum, tantalum nitride, titanium, the titanium nitride gross thickness of one or more materials be 200 dusts-400 dusts; Silicon nitride in these sacrifice layer 212 materials forms by chemical vapor deposition method, and preferably, the thickness of silicon nitride is 150 dusts-200 dusts in this sacrifice layer 212.
Afterwards, on sacrifice layer 212, form photoresist 204 by coating method, further, photoresist 204 is covered in sacrifice layer 212 surfaces fully, and has patterned photoresist 204 by photoetching technique formation.Wherein, sacrifice layer 212 can reduce the standing wave effect of photoresist 204, improves lithography performance.
Step S2: see also Figure 10 and 11, as shown in figure 10, take patterned photoresist 204 as mask, by plasma etching industrial sacrifice layer 212 and interlayer dielectric 202 are carried out dry etching, definition figure out on the photoresist 204 is transferred on the interlayer dielectric 202, formed the metal interconnected line trenches that is arranged in inter-level dielectric 202.By degumming process unnecessary photoresist 204 is removed again, obtained structure as shown in figure 11 after cleaning.
Step S3: see also Figure 12 and 13, as shown in figure 12, on the metal interconnected line trenches and sacrifice layer 212 in interlayer dielectric 202, by physical vapor deposition process deposited barrier layer 205, so that barrier layer 205 is covered in the interior wall of metal interconnected line trenches in the interlayer dielectric 202 fully, diffuse in the interlayer dielectric 202 to stop metallic copper.Further, the material on barrier layer 205 is tantalum/tantalum nitride or titanium/titanium nitride.
Then, as shown in figure 13, by Cu electroplating technique copper is plated in 205 surfaces, barrier layer, make in the metal interconnected line trenches in the interlayer dielectric 202 and fill the copper metal fully, formation is positioned at the metal interconnecting wires 206 on the barrier layer 205, so that the copper damascene structure carries out the conducting of circuit by metal interconnecting wires.
Step S4: see also Figure 14 and 15, as shown in figure 14, by the copper glossing in the cmp, with barrier layer 205 lip-deep unnecessary copper metal removals, the copper metal that is about to 205 surfaces, barrier layer of interlayer dielectric 202 tops is removed, stop when further, making the copper glossing proceed to 205 surface, barrier layer.
Then, as shown in figure 15, by chemical mechanical milling tech barrier layer 205 is polished, wherein, also comprise the removal of the part copper metal that is arranged in the metal interconnected line trenches of interlayer dielectric.Further, in the chemical mechanical milling tech, employing be that Si oxide remove is selected to polish than large barrier polishing solution.Afterwards, sacrifice layer 212 is carried out chemical mechanical milling tech, wherein, also comprise the part copper metal that is arranged in interlayer dielectric 202 metal interconnected line trenches and the removal on sub-fraction barrier layer 205.Further, selected barrier polishing solution in the chemical mechanical milling tech, can remove the sacrifice layer 212 on the interlayer dielectric 202 fully, and the polishing speed of interlayer dielectric 202 is almost 0, therefore substantially can not cause the loss of interlayer dielectric 202 in CMP (Chemical Mechanical Polishing) process, so that in the interlayer dielectric 202 thickness of metal interconnecting wires 206 increase and stablize controlled, thereby improved controllability and the stability of wafer electric property.Finally, formed the copper damascene structure.
In sum, by method of the present invention, deposit one deck sacrifice layer replaces original dielectric medium antireflecting coating on interlayer dielectric, can reduce the standing wave effect of photoresist, improves lithography performance; Again can be as the sacrifice layer in the etch process, reduce the loss of interlayer dielectric medium in the copper damascene structure, so that the thickness of metal interconnecting wires increases and stablizes is controlled, improved controllability and the stability of wafer electric property.
Above-described only is embodiments of the invention; described embodiment limits scope of patent protection of the present invention; therefore the equivalent structure done of every utilization specification of the present invention and accompanying drawing content changes, and in like manner all should be included in protection scope of the present invention.
Claims (9)
1. the formation method of a copper damascene structure is characterized in that, described method comprises the steps:
Step S1: on substrate, sequentially form interlayer dielectric, sacrifice layer and photoresist, and graphical described photoresist, wherein, the material of described sacrifice layer is the combination of one or more materials in silicon nitride or silicon nitride and tantalum, tantalum nitride, titanium, the titanium nitride;
Step S2: take patterned photoresist as mask, the sequentially described sacrifice layer of etching and interlayer dielectric are to form metal interconnected line trenches in described interlayer dielectric;
Step S3: barrier layer in described metal interconnected line trenches, fill the copper metal, to form metal interconnecting wires;
Step S4: by chemical-mechanical planarization technique, remove unnecessary copper, barrier layer and sacrifice layer, finally form the copper damascene structure.
2. method according to claim 1 is characterized in that, described interlayer dielectric forms by chemical vapor deposition method, and wherein, the material of described interlayer dielectric is Si oxide.
3. method according to claim 1 is characterized in that, described sacrifice layer forms by the physics and chemistry vapor deposition process.
4. method according to claim 1 is characterized in that, in the described sacrifice layer in tantalum, tantalum nitride, titanium, the titanium nitride gross thickness of one or more materials be 200 dusts-400 dusts.
5. method according to claim 1 is characterized in that, the thickness of silicon nitride is 150 dusts-200 dusts in the described sacrifice layer.
6. method according to claim 1 is characterized in that, described graphical described photoresist is realized by photoetching.
7. method according to claim 1 is characterized in that, described etching sacrificial layer and interlayer dielectric are carried out etching by plasma etching industrial.
8. method according to claim 1 is characterized in that, described barrier layer forms by physical gas-phase deposition, and wherein, the material on described barrier layer is tantalum/tantalum nitride or titanium/titanium nitride; Described metal interconnecting wires forms by Cu electroplating technique.
9. method according to claim 1 is characterized in that, the removal of described barrier layer and sacrifice layer is to adopt Si oxide removal selection is polished than large barrier polishing solution.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111105990A (en) * | 2018-10-29 | 2020-05-05 | 株洲中车时代电气股份有限公司 | Thin film structure suitable for copper metallized semiconductor device and preparation method thereof |
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| US6153511A (en) * | 1998-10-14 | 2000-11-28 | Fujitsu Limited | Semiconductor device having a multilayered interconnection structure |
| US20020102834A1 (en) * | 2001-01-29 | 2002-08-01 | Tien-Chu Yang | Method of forming dual damascene structure |
| CN101123215A (en) * | 2006-08-11 | 2008-02-13 | 联华电子股份有限公司 | Copper enchasing technology |
| CN101577245A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Chemical and mechanical grinding method for interlaminar dielectric layer |
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| CN111105990A (en) * | 2018-10-29 | 2020-05-05 | 株洲中车时代电气股份有限公司 | Thin film structure suitable for copper metallized semiconductor device and preparation method thereof |
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