CN103001489A - Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump - Google Patents
Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump Download PDFInfo
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Abstract
The invention provides a switch power inverter and a circuit for improving a charging and discharging current matching degree of a charge pump. The circuit includes: a first current mirror array, which mirrors a reference current into N units first mirror currents equal to the reference current; a first current circulation switch array, which circularly switches the N units first mirror currents; a second current circulation switch array, which circularly switches two first mirror currents output by output ends of two circulating currents of the first current circulation switch array; a second current mirror array; a third current circulation switch array, which circularly switches a first current source and a second current source of the second current mirror, and enables the first current source and the second current source to alternately act as a reference source and an output source of current mirrors; and a charging and discharging switch, wherein an output end of the charging and discharging switch is connected to an external electric capacity, so that the charging and discharging switch can charge and discharge the external electric capacity. The switch power inverter and the circuit for improving the charging and discharging current matching degree of the charge pump can solve the problem that a charge current and a discharge current are mismatched caused by deviation among transistors.
Description
Technical field
The present invention relates to charge pumping technique, relate in particular to the circuit of a kind of switch power converter and raising charge pump charging and discharging currents matching degree.
Background technology
At present, in the switch power converter circuit, extensively control constant current output by the proportionate relationship of the charging of control charge pump, discharging current.
Fig. 1 is a kind of CMOS charge pump charging of the prior art, discharge circuit, and this circuit is formed by connecting by the transistor of a plurality of cascades.Wherein, reference current I0 is mirrored and is charging reference current I1 and discharging current Idisch, and charging reference current I1 again mirror image is charging current Ich.Because the matching degree of cmos device is relatively poor, there is larger mismatch between charging current Ich, discharging current Idisch and the reference current Iin.
Fig. 2 is a kind of cyclic switching CMOS charge pump charging of the prior art, discharge circuit, and this circuit is formed by connecting by the transistor of a plurality of cascades.Reference current I0 is mirrored and is the charging reference current I1 that equates with this reference current I0 and M discharge reference current, wherein M is the integer greater than 1, M discharge reference current circulates through the first current cycle switching array 201 and selects a discharge reference current as discharging current Idisch, charging reference current I1 mirror image is N the mirror image charging reference current that equates with described charging reference current I1, wherein N is the integer greater than 1, and N mirror image charging reference current charges reference current as charging current Ich through mirror image of the second current cycle switching array 202 circulation selections.
The first current cycle switching array 201 comprises M image current input and a current cycle array output end, the second current cycle array 202 comprises N image current input and a current cycle array output end, and a control switch is arranged between each image current input and the current cycle array output end.By selecting a discharging current Idisch from the circulation of M discharge reference current and selecting a charging current Ich from the circulation of N mirror image charging reference current, be equivalent to M discharge reference current and N mirror image charging reference current are averaged respectively, so that mismatch descends to some extent, but still there is larger error from reference current I0 mirror image for the process of the charging reference current I1 that equates with described reference current I0.
Summary of the invention
The technical problem to be solved in the present invention provides the circuit of a kind of switch power converter and raising charge pump charging and discharging currents matching degree, can solve charging current that the deviation between the transistor causes and the problem of discharging current mismatch.
For solving the problems of the technologies described above, the invention provides a kind of circuit that improves charge pump charging and discharging currents matching degree, comprising:
The first current lens array, being used for the reference current mirror image is N first mirror image current that equates with this reference current, wherein N is the integer greater than 1;
The first current cycle switching array, have N current input terminal and 2 circulating current outputs, the N of described the first a current cycle switching array current input terminal receives respectively N first mirror image current of described the first current lens array output, described the first current cycle switching array carries out cyclic switching to described N first mirror image current, from wherein selecting 2 first mirror image currents and exporting via described 2 circulating current outputs respectively;
The second current cycle switching array, have 2 current input terminals, 2 circulating current outputs, 2 current input terminals of described the second current cycle switching array connect respectively 2 circulating current outputs of described the first current cycle switching array, described the second current cycle switching array carries out cyclic switching to 2 first mirror image currents of 2 circulating current output outputs of described the first current cycle switching array, makes the two alternate conduction to 2 circulating current outputs of described the second current cycle switching array;
The second current mirror comprises the first current source and the second current source, is the second image current that equates with this reference current with described reference current mirror image;
The 3rd current cycle switching array, has 1 current input terminal, 1 circulating current output and 2 cyclic switching ends, the current input terminal of described the 3rd current cycle switching array connects in 2 circulating current outputs of described the second current cycle switching array, 2 cyclic switching ends of described the 3rd current cycle switching array connect respectively the output of described the first current source and the second current source, described the 3rd current cycle switching array carries out cyclic switching to described the first current source and the second current source, make the two alternately as reference source and the output source of current mirror, wherein reference source receives the first mirror image current of the current input terminal transmission of described the 3rd current cycle switching array, and output source transfers to described the second image current the circulating current output of described the 3rd current cycle switching array;
The charging and discharging switch, have 2 inputs and 1 output, these 2 inputs are connected respectively to the circulating current output of another and described the 3rd current cycle switching array in 2 circulating current outputs of described the second current cycle switching array, and this output is connected to external capacitive so that it is carried out charge or discharge.
According to one embodiment of present invention, described the first current cycle switching array comprises N switch, the first end of this N switch receives respectively N first mirror image current of described the first current lens array output, the second end of this N one of them switch of switch connects a circulating current output of described the first current cycle switching array, in addition the second end of N-1 switch in this N switch connects another circulating current output of described the first current cycle switching array, described in a clock cycle in office have and only have a conducting in N-1 switch in addition, and described other N-1 each conducting of switch be once within N-1 clock cycle.
According to one embodiment of present invention, described the second current cycle switching array comprises:
The first switch, its first end connect in 2 circulating current outputs of described the first current cycle switching array;
Second switch, its first end connect another in 2 circulating current outputs of described the first current cycle switching array, and its second end connects the second end of described the first switch and as a circulating current output of described the second current cycle switching array;
The 3rd switch, its first end connects the first end of described second switch;
The 4th switch, its first end connects the first end of described the first switch, and its second end connects the second end of described the 3rd switch and as another circulating current output of described the second current cycle switching array;
Wherein, the control end of described the first switch and the 3rd switch receives same control signal, and the control end of described second switch and the 4th switch receives the inversion signal of described control signal.
According to one embodiment of present invention, described the 3rd current cycle switching array comprises:
The 5th switch, its first end connects the control end of described first, second current source, and its second end connects the output of described the first current source and as the current input terminal of described the 3rd cyclic switching array;
The 6th switch, its first end connects the first end of described the 5th switch, and its second end connects the output of described the second current source;
Minion is closed, and its first end is as the circulating current output of described the 3rd cyclic switching array, and its second end connects the output of described the second current source;
The 8th switch, its first end connect the first end that described minion is closed, and its second end connects the second end of described the 5th switch;
Wherein, the control end that described the 5th switch and minion are closed receives same control signal, and the control end of described the 6th switch and the 8th switch receives the inversion signal of described control signal.
According to one embodiment of present invention, described charging and discharging switch comprises:
The 9th switch, its first end connect the circulating current output of described the 3rd current cycle switching array, and its second end connects described external capacitive;
The tenth switch, its first end connect another in 2 circulating current outputs of described the second current cycle switching array, and its second end connects described external capacitive;
Wherein, the control signal that receives of the control end of described the 9th switch and the tenth switch is mutually anti-phase.
The present invention also provides a kind of switch power converter, comprises the circuit of above each described raising charge pump charging and discharging currents matching degree.
Compared with prior art, the present invention has the following advantages:
In the circuit of the raising charge pump charging and discharging currents matching degree of the embodiment of the invention, current mirror input, output current are switched to eliminate the impact on charge pump charging, discharging current matching degree that the process deviation between transistor causes through loop cycle, except the current source that reference current is flowed through, all pass through cyclic switching with charging, current source that discharging current is relevant, thereby greatly eliminated the error that charging, discharging current matching degree difference band come.
Description of drawings
Fig. 1 is a kind of charge pump charging of the prior art, discharge circuit;
Fig. 2 is another kind of charge pump charging of the prior art, discharge circuit;
Fig. 3 shows the circuit block diagram of the raising charge pump charging and discharging currents matching degree of the embodiment of the invention;
Fig. 4 shows the detailed circuit diagram of the circuit that improves charge pump charging and discharging currents matching degree in the first embodiment of the invention;
Fig. 5 shows the detailed circuit diagram of the circuit that improves charge pump charging and discharging currents matching degree in the second embodiment of the invention.
Embodiment
The invention will be further described below in conjunction with specific embodiments and the drawings, but should not limit protection scope of the present invention with this.
With reference to figure 3, the circuit of the raising charge pump charging and discharging currents matching degree of the present embodiment comprises: the first current lens array 1, the first current cycle switching array 2, the second current cycle switching array 3, charging and discharging switch 4, the 3rd current cycle switching array 5, the second current lens array 6 and reference current source 7.
Wherein, reference current source 7 output reference electric currents, it can adopt any one suitable reference current source structure in the prior art.
The reference current mirror image that the first current lens array 1 is used for reference current source 7 outputs is N first mirror image current that equates with this reference current, and wherein N is the integer greater than 1.The first current lens array 1 can adopt the mode of a plurality of current mirrors to realize.
The first current cycle switching array 2 has N current input terminal and 2 circulating current outputs.More specifically, this N current input terminal comprises 1 current input terminal 20 and N-1 current input terminal 21, and these 2 circulating current outputs comprise circulating current output 22 and circulating current output 23.Wherein, current input terminal 20 an and N-1 current input terminal 21 links to each other with N output of the first current lens array 1 respectively, is used for receiving N first mirror image current of the first current lens array 1 output.2 couples of these N of the first current cycle switching array first mirror image current carries out cyclic switching, from wherein selecting 2 first mirror image currents and exporting via circulating current output 22 and circulating current output 23 respectively.
Furthermore, be serially connected with a switch between image current input 20 and the circulating current output 22, the constant conducting of this switch; All be serially connected with a switch between in N-1 image current input 21 each and the circulating current output 23, a clock in office is in the cycle, have and only have a conducting in N-1 the switch, and within N-1 clock cycle, each each conducting in N-1 switch once.Behind the cyclic switching by the first current cycle switching array 2, circulating current output 23 output currents are the mean value of the first mirror image current of N-1 image current input 21 inputs, thereby are conducive to eliminate because the electric current of circulating current output 23 outputs that transistor variation causes and the unmatched problem of reference current of reference current source 7.
The second current cycle switching array 3 has 2 current input terminals 30,31 and 2 circulating current outputs 32,33.Wherein current input terminal 30 connects the circulating current output 22 of the first current cycle switching array 2, and current input terminal 31 connects the circulating current output 23 of the first current cycle switching array 2.2 first mirror image currents of 3 pairs of circulating current outputs 22 of the second current cycle switching array and 23 outputs of circulating current output carry out cyclic switching, so that 2 circulating current outputs 32,33 of the two alternate conduction to the second current cycle switching array 3.
Furthermore, image current input 30,31 and circulating current output 32,33 between all be connected to switch, totally 4 on switch, behind the cyclic switching by the 3rd current cycle switching array 3, circulating current output 32,33 output currents are the mean value of the first mirror image current of two image current inputs 30,31 inputs, thereby play the circulating current output 32 of eliminating transistor variation and causing, the mismatch problem between 33 electric currents of exporting.
The second current lens array 6 (for example comprises the first current source and the second current source, the first current source adopts the first MOS transistor to realize, the second current source adopts the second MOS transistor to realize, certainly those skilled in the art are to be understood that, the first current source and the second current source can also adopt other implementations, such as current source of cascade structure etc.), be the second image current that equates with this reference current with the reference current mirror image.When the first current lens array 1 was used as external capacitive 8 charging, 6 of the second current lens array were used as discharge; Otherwise when the first current lens array 1 was used as external capacitive 8 discharge, the second current lens array 6 had been used as charging.
The 3rd current cycle switching array 5 has 1 current input terminal 52,1 circulating current output 53 and 2 cyclic switching ends 51, the current input terminal 52 of the 3rd current cycle switching array 5 connects the circulating current output 32 of the second current cycle switching array 3,2 cyclic switching ends 51 of the 3rd current cycle switching array 5 connect respectively the first current source and the second current source in the second current lens array 6,5 pairs of the first current sources of the 3rd current cycle switching array and the second current source carry out cyclic switching, make the two alternately as reference source and the output source of current mirror, wherein reference source receives the first mirror image current of current input terminal 52 transmission of the 3rd current cycle switching array 5, and output source will be exported the circulating current output 53 of the second image current to the three current cycle switching arrays 5.
Furthermore, behind the cyclic switching by the 3rd current cycle switching array 5, the first MOS transistor and the second MOS transistor are alternately as reference pipe and efferent duct in the second current lens array 6, the electric current of circulating current output 53 output is the mean value of the image current of the first MOS transistor and the output of the second MOS transistor, thereby plays the electric current of circulating current output 53 outputs that the deviation of eliminating the first MOS transistor and the second MOS transistor causes and the unmatched problem of reference current of reference current source 7.
Charging and discharging switch 4 has 2 inputs and 1 output, these 2 inputs are connected respectively to the circulating current output 33 of the second current cycle switching array 3 and the circulating current output 53 of the 3rd current cycle switching array 5, and the output of charging and discharging switch 4 is connected to external capacitive 8 so that it is carried out charge or discharge.
Furthermore, within the same clock cycle, the output of charging and discharging switch 4 only with one of them input conducting, and within two clock cycle, 2 each conductings of input of the output of charging and discharging switch 4 and charging and discharging switch 4 are once.
Wherein the first current lens array 1 can adopt a plurality of nmos pass transistor interconnection to realize, this moment second, current lens array 6 adopted 2 PMOS transistor interconnection to realize; Otherwise when the first current lens array 1 adopted the PMOS transistor to realize, the second current lens array 6 adopted nmos pass transistor to realize.
The working method that improves the circuit of charge pump charging, discharging current matching degree in the present embodiment is summarized as follows: the first current lens array 1 becomes N first mirror image current that equates with the reference current of reference current source 7 with the reference current mirror image of reference current source 7, and the first mirror image current is input to the first current cycle switching array 2; The electric current of circulating current output 22 outputs is the electric current of image current input 20 inputs, and the first current cycle switching array 2 process cyclic switchings are so that the electric current that circulating current output 23 is exported within N-1 clock cycle is the mean value of the first mirror image current of N-1 image current input 21 inputs; The electric currents of circulating current output 22,23 outputs send into the second current cycle switching array 3, the second current cycle switching arrays 3 through cyclic switchings so that within two clock cycle the electric currents of circulating current output 32,33 outputs be the mean value of the electric currents of two current input terminals 30,31 inputs; N first mirror image current passes through the cyclic switching of the first current cycle switching array 2 and the second current cycle switching array 3, so that the electric currents of circulating current output 32,33 outputs are the first mirror image current of N-1 current input terminal 21 inputs and the mean value of the first mirror image current that current input terminal 20 is inputted within 2 * (N-1) individual clock cycle; The second current lens array 6 has two current sources, and replaces reference source and output source as current mirror under the cyclic switching of the 3rd current cycle switching array 5; The 3rd current cycle switching array 5 process cyclic switchings are so that the electric current that circulating current output 53 is exported within two clock cycle is the mean value of the image current of two current sources outputs; The electric current of circulating current output 32 outputs is as the reference source electric current of the second current lens array 6, the electric current that receives with current input terminal 52 is same electric current, so that the electric current of the electric current of circulating current output 53 output and 33 outputs of circulating current output is the mean value of the first mirror image current of the mean value of first mirror image current of N-1 current input terminal 21 inputs and current input terminal 20 inputs within 2 * 2 * (N-1) individual clock cycle, namely so that during 2 * 2 * (N-1) individual clock cycle the charging current of charge pump and discharging current be the mean value of the first mirror image current that N-1 current input terminal 21 input and the mean value of the first mirror image current that current input terminal 20 is inputted.
Circuit shown in Figure 3 can be used for switch power converter, and this switch power converter can be the various switch power converters of controlling constant current output by charge pump charging, discharging current proportionate relationship in the prior art.
With reference to figure 4, Fig. 4 shows the detailed circuit diagram of the first embodiment, and wherein N equals 3.The below is described in detail.
In the first embodiment, the first current lens array 1 comprises nmos pass transistor B0 to B3, and wherein, the grid of nmos pass transistor B1, B2 and B3 is connected to the grid of nmos pass transistor B0, the source ground of nmos pass transistor B0 to B3, the first mirror image current is exported respectively in the drain electrode of nmos pass transistor B0 to B3.
The first current cycle switching array 2 comprises 3 switch J0, J1 and J2, the first end of the drain electrode connecting valve J0 of nmos pass transistor B1, and the drain electrode of nmos pass transistor B2 is connected to the first end of switch J1, and the drain electrode of nmos pass transistor B3 is connected to the first end of switch J2.The second end of switch J1 and switch J2 links together.A clock in office has and only has 1 conducting in the cycle among switch J1 and the switch J2, and within 2 clock cycle, switch J1 and each conducting of switch J2 are once.
The second current cycle switching array 3 comprises: the first switch Q0, second switch Q2, the 3rd switch Q3 and the 4th switch Q4.Wherein, the second end of switch J0 connects the first end of the first switch Q0 and the first end of the 4th switch Q3, switch J1 is connected the second end and is jointly connected the first end of second switch Q1 and the first end of the 3rd switch Q2 with switch J2, the second end of the first switch Q0 and the second end of second switch Q1 link together (particularly, be connected to the grid of PMOS transistor A1), the second end of the 3rd switch Q2 and the 4th switch Q3 link together (first end that particularly, is connected to the tenth K switch 1).Wherein, the control end of the first switch Q0 and second switch Q1 receives same control signal, and the control end of second switch Q1 and the 4th switch Q3 receives the inversion signal of this control signal.
The 3rd cyclic switching array 5 comprises: the 5th switch P 0, the 6th switch P 1, minion are closed P2 and the 8th switch P3.Wherein, the first end of the first end of the 5th switch P 0 and the 6th switch P 1 is connected to the grid of PMOS transistor A1 jointly, and the grid of PMOS transistor A2 is connected to the grid of PMOS transistor A1, and the source electrode of PMOS transistor A1 and PMOS transistor A2 is connected to power supply.The first end that minion is closed the first end of P2 and the 8th switch P3 links together and as the circulating current output of the 3rd cyclic switching array 5, and the second end that minion is closed P2 connects the drain electrode of PMOS transistor A2; The second end of the second end of the 8th switch P3 and the 5th switch P 0 is connected to the drain electrode of PMOS transistor A1 jointly.Wherein the control end of the 5th switch P 0 and minion pass P2 receives same control signal, and the control end of the 6th switch P 1 and the 8th switch P3 receives the inversion signal of this control signal.
Charging and discharging switch 4 comprises the 9th K switch 0 and the tenth K switch 1.Wherein, the first end of the 9th K switch 0 connects the first end that minion is closed P2 and the 8th switch P3, and the second end of the 9th K switch 0 connects the end of external capacitive C0; The first end of the tenth K switch 1 connects the second end of the 3rd switch Q2 and the 4th switch Q4, and the second end of the tenth K switch 1 connects the end of external capacitive C0 and the second end of the 9th K switch 0, the other end ground connection of external capacitive C0.Wherein, the control signal that receives of the control end of the 9th K switch 0 and the tenth K switch 1 is mutually anti-phase.
As a nonrestrictive example, the control end of the first switch Q0 and the 3rd switch Q2 is subjected to same clock signal C 0 control, and the control end of second switch Q1 and the 4th switch Q3 is controlled by the inversion signal C1 of same clock signal C 0.The control end suspension control signal C2 control of the 9th K switch 0, the inversion signal C3 control of the control end suspension control signal C2 of the tenth K switch 1.The control end that the 5th switch P 0 and minion are closed P2 is subjected to same clock signal C 4 controls, and the control end of the 6th switch P 1 and the 8th switch P3 is controlled by the inversion signal C5 of same clock signal C 4.The constant conducting of switch J0, switch J1 subject clock signal C6 control, the inversion signal C7 control of switch J2 subject clock signal C6.
Clock signal C 0, clock signal C 4 and clock signal C 6 consist of 8 unit period clocks, and clock signal C 0, C4, C6 cover 000,001,010,011,100,101,110,111 these 8 kinds of states.Control signal C2 for example is the square wave of 50% duty ratio.Suppose
For be mirrored to the transmission error of nmos pass transistor B1 from nmos pass transistor B0, the electric current of the nmos pass transistor B1 that flows through can be used
Expression, wherein I
0The current value of expression reference current, similarly, the electric current of the transmission error between other MOS transistor and each MOS transistor of flowing through also can adopt such as upper type and explain, then per 8 unit period clock charging current I
ChargingWith discharging current I
DischargeRatio is:
Suppose
Be 0.7, substitution can get:
This shows, adopt this scheme, charge pump charging, discharging current matching degree are significantly improved.
With reference to figure 5, Fig. 5 shows the detailed circuit diagram of the second embodiment, wherein N equals 2, in the case, 2 switches in the first current cycle switching array all are in permanent conducting state, thereby the first cyclic switching array can be saved and direct termination, other structures and aforementioned the first embodiment are similar, and the below is described in detail.
The grid of nmos pass transistor B0 and drain electrode short circuit, source ground.The grid of nmos pass transistor B1 and NNMOS transistor B2 is connected to the grid of nmos pass transistor B0, source ground.The drain electrode of nmos pass transistor B1 is connected to the end of switch Q0 and Q3, and the drain electrode of nmos pass transistor B2 is connected to the end of switch Q1 and Q2.The other end of switch Q0 and Q1 is connected to the grid of PMOS transistor A1, and the other end of switch Q2 and Q3 is connected to an end of K switch 1.The end of switch P 0 and P1 is connected to the grid of PMOS transistor A1, and the grid of PMOS transistor A2 is connected to the grid of PMOS transistor A1, and the source electrode of PMOS transistor A1, A2 is connected to power supply.The other end of K switch 1 is connected to an end of external capacitive C0 and K switch 0, the other end ground connection of capacitor C 0.The other end of switch P 0 and P3 is connected to the drain electrode of PMOS transistor A1.The other end of switch P 1 and P2 is connected to the drain electrode of PMOS transistor A2.
Switch Q0 and Q2 are subjected to same clock signal C 0 control, and switch Q1 and Q3 are controlled by the inversion signal C1 of same clock signal C 0.K switch 0 suspension control signal C2 control, the inversion signal C3 control of K switch 1 suspension control signal C2.Switch P 0 and P2 are subjected to same clock signal C 4 controls, and switch P 1 and P3 are controlled by the inversion signal C5 of same clock signal C 4.
Clock signal C 0, clock signal C 4 consist of 4 unit period clocks, and C0, C4 cover 00,01,10,11 these 4 kinds of states.Control signal C2 can be the square wave of 50% duty ratio.
Suppose
For be mirrored to the transmission error of nmos pass transistor B1 from nmos pass transistor B0, the electric current of the nmos pass transistor B1 that flows through can be used
Expression, wherein I
0The current value of expression reference current, similarly, the electric current of the transmission error between other MOS transistor and each MOS transistor of flowing through also can adopt such as upper type and explain, and then per 4 unit period clock charging currents and discharging current ratio are:
Suppose
Be 0.7, substitution can get
This shows, adopt this scheme, charge pump charging, discharging current matching degree are significantly improved.
In sum, the invention provides a kind of circuit that charge pump charging, discharging current is switched to eliminate the impact that the process deviation between the transistor causes matching degree through loop cycle, the circuit for eliminating of above raising charge pump charging, discharging current matching degree in the prior art because the impact that the deviation between the transistor causes matching precision.
Above-described embodiment is just to explanation of the present invention; rather than limitation of the present invention; any innovation and creation that do not exceed in the connotation scope of the present invention; include but not limited to charging circuit and discharge circuit structure are exchanged; change the clock signal sequential; to the change of the local structure of circuit (as utilize those skilled in the art thinkable technical method replace current source structure among the present invention; electric capacity is replaced to electric capacity with being connected to be connected to power supply etc.); replacement (as the PMOS pipe being replaced with NMOS pipe etc.) to type or the model of components and parts; and the replacement of other unsubstantialities or modification, all fall within the protection range of the present invention.
Claims (6)
1. a circuit that improves charge pump charging and discharging currents matching degree is characterized in that, comprising:
The first current lens array, being used for the reference current mirror image is N first mirror image current that equates with this reference current, wherein N is the integer greater than 1;
The first current cycle switching array, have N current input terminal and 2 circulating current outputs, the N of described the first a current cycle switching array current input terminal receives respectively N first mirror image current of described the first current lens array output, described the first current cycle switching array carries out cyclic switching to described N first mirror image current, from wherein selecting 2 first mirror image currents and exporting via described 2 circulating current outputs respectively;
The second current cycle switching array, have 2 current input terminals, 2 circulating current outputs, 2 current input terminals of described the second current cycle switching array connect respectively 2 circulating current outputs of described the first current cycle switching array, described the second current cycle switching array carries out cyclic switching to 2 first mirror image currents of 2 circulating current output outputs of described the first current cycle switching array, makes the two alternate conduction to 2 circulating current outputs of described the second current cycle switching array;
The second current lens array comprises the first current source and the second current source, is the second image current that equates with this reference current with described reference current mirror image;
The 3rd current cycle switching array, has 1 current input terminal, 1 circulating current output and 2 cyclic switching ends, the current input terminal of described the 3rd current cycle switching array connects in 2 circulating current outputs of described the second current cycle switching array, 2 cyclic switching ends of described the 3rd current cycle switching array connect respectively the output of described the first current source and the second current source, described the 3rd current cycle switching array carries out cyclic switching to described the first current source and the second current source, make the two alternately as reference source and the output source of current mirror, wherein reference source receives the first mirror image current of the current input terminal transmission of described the 3rd current cycle switching array, and output source transfers to described the second image current the circulating current output of described the 3rd current cycle switching array;
The charging and discharging switch, have 2 inputs and 1 output, these 2 inputs are connected respectively to the circulating current output of another and described the 3rd current cycle switching array in 2 circulating current outputs of described the second current cycle switching array, and this output is connected to external capacitive so that it is carried out charge or discharge.
2. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1, it is characterized in that, described the first current cycle switching array comprises N switch, the first end of this N switch receives respectively N first mirror image current of described the first current lens array output, the second end of this N one of them switch of switch connects a circulating current output of described the first current cycle switching array, in addition the second end of N-1 switch in this N switch connects another circulating current output of described the first current cycle switching array, described in a clock cycle in office have and only have a conducting in N-1 switch in addition, and described other N-1 each conducting of switch be once within N-1 clock cycle.
3. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1 is characterized in that, described the second current cycle switching array comprises:
The first switch, its first end connect in 2 circulating current outputs of described the first current cycle switching array;
Second switch, its first end connect another in 2 circulating current outputs of described the first current cycle switching array, and its second end connects the second end of described the first switch and as a circulating current output of described the second current cycle switching array;
The 3rd switch, its first end connects the first end of described second switch;
The 4th switch, its first end connects the first end of described the first switch, and its second end connects the second end of described the 3rd switch and as another circulating current output of described the second current cycle switching array;
Wherein, the control end of described the first switch and the 3rd switch receives same control signal, and the control end of described second switch and the 4th switch receives the inversion signal of described control signal.
4. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1 is characterized in that, described the 3rd current cycle switching array comprises:
The 5th switch, its first end connects the control end of described first, second current source, and its second end connects the output of described the first current source and as the current input terminal of described the 3rd cyclic switching array;
The 6th switch, its first end connects the first end of described the 5th switch, and its second end connects the output of described the second current source;
Minion is closed, and its first end is as the circulating current output of described the 3rd cyclic switching array, and its second end connects the output of described the second current source;
The 8th switch, its first end connect the first end that described minion is closed, and its second end connects the second end of described the 5th switch;
Wherein, the control end that described the 5th switch and minion are closed receives same control signal, and the control end of described the 6th switch and the 8th switch receives the inversion signal of described control signal.
5. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1 is characterized in that, described charging and discharging switch comprises:
The 9th switch, its first end connect the circulating current output of described the 3rd current cycle switching array, and its second end connects described external capacitive;
The tenth switch, its first end connect another in 2 circulating current outputs of described the second current cycle switching array, and its second end connects described external capacitive;
Wherein, the control signal that receives of the control end of described the 9th switch and the tenth switch is mutually anti-phase.
6. a switch power converter is characterized in that, comprises the circuit of each described raising charge pump charging and discharging currents matching degree in the claim 1 to 5.
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| US6124741A (en) * | 1999-03-08 | 2000-09-26 | Pericom Semiconductor Corp. | Accurate PLL charge pump with matched up/down currents from Vds-compensated common-gate switches |
| US7385429B1 (en) * | 2005-05-31 | 2008-06-10 | Altera Corporation | Charge pump with reduced current mismatch |
| CN101888178A (en) * | 2010-06-13 | 2010-11-17 | 浙江大学 | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop |
| CN201754557U (en) * | 2010-07-30 | 2011-03-02 | 苏州科山微电子科技有限公司 | Charge pump capable of solving problems of charge distribution and current mismatch |
| CN102255498A (en) * | 2011-06-28 | 2011-11-23 | 上海宏力半导体制造有限公司 | Charge pump circuit |
| CN203014674U (en) * | 2012-12-31 | 2013-06-19 | 杭州士兰微电子股份有限公司 | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6124741A (en) * | 1999-03-08 | 2000-09-26 | Pericom Semiconductor Corp. | Accurate PLL charge pump with matched up/down currents from Vds-compensated common-gate switches |
| US7385429B1 (en) * | 2005-05-31 | 2008-06-10 | Altera Corporation | Charge pump with reduced current mismatch |
| CN101888178A (en) * | 2010-06-13 | 2010-11-17 | 浙江大学 | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop |
| CN201754557U (en) * | 2010-07-30 | 2011-03-02 | 苏州科山微电子科技有限公司 | Charge pump capable of solving problems of charge distribution and current mismatch |
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| CN103001489B (en) | 2015-01-07 |
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