CN103001489B - Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump - Google Patents
Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump Download PDFInfo
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- CN103001489B CN103001489B CN201210595125.4A CN201210595125A CN103001489B CN 103001489 B CN103001489 B CN 103001489B CN 201210595125 A CN201210595125 A CN 201210595125A CN 103001489 B CN103001489 B CN 103001489B
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Abstract
The invention provides a switch power inverter and a circuit for improving a charging and discharging current matching degree of a charge pump. The circuit includes: a first current mirror array, which mirrors a reference current into N units first mirror currents equal to the reference current; a first current circulation switch array, which circularly switches the N units first mirror currents; a second current circulation switch array, which circularly switches two first mirror currents output by output ends of two circulating currents of the first current circulation switch array; a second current mirror array; a third current circulation switch array, which circularly switches a first current source and a second current source of the second current mirror, and enables the first current source and the second current source to alternately act as a reference source and an output source of current mirrors; and a charging and discharging switch, wherein an output end of the charging and discharging switch is connected to an external electric capacity, so that the charging and discharging switch can charge and discharge the external electric capacity. The switch power inverter and the circuit for improving the charging and discharging current matching degree of the charge pump can solve the problem that a charge current and a discharge current are mismatched caused by deviation among transistors.
Description
Technical field
The present invention relates to charge pumping technique, particularly relate to the circuit of a kind of switch power converter and raising charge pump charging and discharging currents matching degree.
Background technology
At present, in switch power converter circuit, extensively by controlling, charge pump charges, the proportionate relationship of discharging current controls constant current output.
Fig. 1 is a kind of CMOS charge pump charging of the prior art, discharge circuit, and this circuit is formed by connecting by the transistor of multiple cascade.Wherein, reference current I0 is mirrored as charging reference current I1 and discharging current Idisch, and charging reference current I1 again mirror image is charging current Ich.Because the matching degree of cmos device is poor, charging current Ich, between discharging current Idisch and reference current Iin, there is larger mismatch.
Fig. 2 is a kind of cyclic switching CMOS charge pump charging of the prior art, discharge circuit, and this circuit is formed by connecting by the transistor of multiple cascade.Reference current I0 is mirrored as the charging reference current I1 and M equal with this reference current I0 discharges reference current, wherein M be greater than 1 integer, M electric discharge reference current circulates selection one electric discharge reference current as discharging current Idisch through the first current cycle switching array 201, charging reference current I1 mirror image is that the N number of mirror image equal with described charging reference current I1 charges reference current, wherein N be greater than 1 integer, N number of mirror image charging reference current circulates selection mirror image charging reference current as charging current Ich through the second current cycle switching array 202.
First current cycle switching array 201 comprises M image current input and a current cycle array output end, second current cycle array 202 comprises N number of image current input and a current cycle array output end, has a control switch between each image current input and current cycle array output end.By selecting a discharging current Idisch from the circulation of M electric discharge reference current and selecting a charging current Ich from the circulation of N number of mirror image charging reference current, M electric discharge reference current and N number of mirror image charging reference current is equivalent to average respectively, mismatch is declined to some extent, but still there is comparatively big error from the process that reference current I0 mirror image is the charging reference current I1 equal with described reference current I0.
Summary of the invention
The technical problem to be solved in the present invention is to provide the circuit of a kind of switch power converter and raising charge pump charging and discharging currents matching degree, can solve the problem of charging current that the deviation between transistor causes and discharging current mismatch.
For solving the problems of the technologies described above, the invention provides a kind of circuit improving charge pump charging and discharging currents matching degree, comprising:
First current lens array, for by reference current mirror image being N number of first image current equal with this reference current, wherein N be greater than 1 integer;
First current cycle switching array, there are N number of current input terminal and 2 circulating current outputs, N number of current input terminal of described first current cycle switching array receives N number of first image current of described first current lens array output respectively, described first current cycle switching array carries out cyclic switching to described N number of first image current, from wherein selecting 2 the first image currents and exporting via described 2 circulating current outputs respectively;
Second current cycle switching array, there are 2 current input terminals, 2 circulating current outputs, 2 current input terminals of described second current cycle switching array connect 2 circulating current outputs of described first current cycle switching array respectively, 2 the first image currents that 2 the circulating current outputs of described second current cycle switching array to described first current cycle switching array export carry out cyclic switching, make the two alternate conduction to 2 circulating current outputs of described second current cycle switching array;
Second current mirror, comprises the first current source and the second current source, is second image current equal with this reference current by described reference current mirror image;
3rd current cycle switching array, there is 1 current input terminal, 1 circulating current output and 2 cyclic switching ends, the current input terminal of described 3rd current cycle switching array connects one in 2 circulating current outputs of described second current cycle switching array, 2 cyclic switching ends of described 3rd current cycle switching array connect the output of described first current source and the second current source respectively, described 3rd current cycle switching array carries out cyclic switching to described first current source and the second current source, make the two alternately as reference source and the output source of current mirror, wherein reference source receives the first image current of the current input terminal transmission of described 3rd current cycle switching array, described second image current is transferred to the circulating current output of described 3rd current cycle switching array by output source,
Charging and discharging switch, there is 2 inputs and 1 output, these 2 inputs are connected respectively to the circulating current output of another and described 3rd current cycle switching array in 2 circulating current outputs of described second current cycle switching array, and this output is connected to external capacitive to carry out charge or discharge to it.
According to one embodiment of present invention, described first current cycle switching array comprises N number of switch, the first end of this N number of switch receives N number of first image current of described first current lens array output respectively, second end of this N number of one of them switch of switch connects a circulating current output of described first current cycle switching array, second end of another N-1 switch in this N number of switch connects another circulating current output of described first current cycle switching array, have in a described another N-1 switch in the clock cycle in office and only have a conducting, and each conducting of a described another N-1 switch is once within N-1 clock cycle.
According to one embodiment of present invention, described second current cycle switching array comprises:
First switch, its first end connects one in 2 circulating current outputs of described first current cycle switching array;
Second switch, its first end connect in 2 circulating current outputs of described first current cycle switching array another, its second end connect described first switch the second end and as a circulating current output of described second current cycle switching array;
3rd switch, its first end connects the first end of described second switch;
4th switch, its first end connects the first end of described first switch, its second end connect described 3rd switch the second end and as another circulating current output of described second current cycle switching array;
Wherein, the control end of described first switch and the 3rd switch receives same control signal, and the control end of described second switch and the 4th switch receives the inversion signal of described control signal.
According to one embodiment of present invention, described 3rd current cycle switching array comprises:
5th switch, its first end connects the control end of first, second current source described, its second end connect described first current source output and as the current input terminal of described 3rd cyclic switching array;
6th switch, its first end connects the first end of described 5th switch, and its second end connects the output of described second current source;
7th switch, its first end is as the circulating current output of described 3rd cyclic switching array, and its second end connects the output of described second current source;
8th switch, its first end connects the first end of described 7th switch, and its second end connects the second end of described 5th switch;
Wherein, the control end of described 5th switch and the 7th switch receives same control signal, and the control end of described 6th switch and the 8th switch receives the inversion signal of described control signal.
According to one embodiment of present invention, described charging and discharging switch comprises:
9th switch, its first end connects the circulating current output of described 3rd current cycle switching array, and its second end connects described external capacitive;
Tenth switch, its first end connect described second current cycle switching array 2 circulating current outputs in another, its second end connects described external capacitive;
Wherein, the control signal that receives of the control end of described 9th switch and the tenth switch is mutually anti-phase.
Present invention also offers a kind of switch power converter, comprise the circuit of the raising charge pump charging and discharging currents matching degree described in above any one.
Compared with prior art, the present invention has the following advantages:
In the circuit of the raising charge pump charging and discharging currents matching degree of the embodiment of the present invention, current mirror input, output current are switched the impact on charge pump charging, discharging current matching degree caused with the process deviation eliminated between transistor through loop cycle, except the current source that reference current flows through, to charging, the relevant current source of discharging current all through cyclic switching, thus greatly eliminate the error of charging, discharging current matching degree difference band.
Accompanying drawing explanation
Fig. 1 is a kind of charge pump charging of the prior art, discharge circuit;
Fig. 2 is another kind of charge pump charging of the prior art, discharge circuit;
Fig. 3 shows the circuit block diagram of the raising charge pump charging and discharging currents matching degree of the embodiment of the present invention;
Fig. 4 shows in first embodiment of the invention the detailed circuit diagram of the circuit improving charge pump charging and discharging currents matching degree;
Fig. 5 shows in second embodiment of the invention the detailed circuit diagram of the circuit improving charge pump charging and discharging currents matching degree.
Embodiment
Below in conjunction with specific embodiments and the drawings, the invention will be further described, but should not limit the scope of the invention with this.
With reference to figure 3, the circuit of the raising charge pump charging and discharging currents matching degree of the present embodiment comprises: the first current lens array 1, first current cycle switching array 2, second current cycle switching array 3, charging and discharging switch 4, the 3rd current cycle switching array 5, second current lens array 6 and reference current source 7.
Wherein, reference current source 7 output reference electric current, it can adopt any one suitable reference current source structure in prior art.
First current lens array 1 is N number of first image current equal with this reference current for the reference current mirror image exported by reference current source 7, wherein N be greater than 1 integer.First current lens array 1 can adopt the mode of multiple current mirror to realize.
First current cycle switching array 2 has N number of current input terminal and 2 circulating current outputs.More specifically, this N number of current input terminal comprises 1 current input terminal 20 and N-1 current input terminal 21, and these 2 circulating current outputs comprise circulating current output 22 and circulating current output 23.Wherein, N number of output of current input terminal 20 and N-1 current input terminal 21 respectively with the first current lens array 1 is connected, for receiving N number of first image current that the first current lens array 1 exports.First current cycle switching array 2 carries out cyclic switching to this N number of first image current, from wherein selecting 2 the first image currents and exporting via circulating current output 22 and circulating current output 23 respectively.
Furthermore, between image current input 20 and circulating current output 22, be serially connected with a switch, this switched constant conducting; A switch is all serially connected with between each and circulating current output 23 in N-1 image current input 21, in the clock cycle in office, have in N-1 switch and only have a conducting, and within N-1 clock cycle, each each conducting in N-1 switch once.After cyclic switching by the first current cycle switching array 2, circulating current output 23 output current is the mean value of the first image current that N-1 image current input 21 inputs, thus is conducive to eliminating the electric current of circulating current output 23 output because transistor variation causes and the unmatched problem of reference current of reference current source 7.
Second current cycle switching array 3 has 2 current input terminals, 30,31 and 2 circulating current outputs 32,33.Wherein current input terminal 30 connects the circulating current output 22 of the first current cycle switching array 2, and current input terminal 31 connects the circulating current output 23 of the first current cycle switching array 2.2 the first image currents that second current cycle switching array 3 pairs circulating current output 22 and circulating current output 23 export carry out cyclic switching, make 2 circulating current outputs 32,33 of the two alternate conduction to the second current cycle switching array 3.
Furthermore, all switch is connected between image current input 30,31 and circulating current output 32,33, totally 4, switch, after cyclic switching by the 3rd current cycle switching array 3, circulating current output 32,33 output current is the mean value of the first image current that two image current inputs 30,31 input, thus plays the mismatch problem between the electric current eliminating circulating current output 32,33 output that transistor variation causes.
Second current lens array 6 comprises the first current source and the second current source (such as, first current source adopts the first MOS transistor to realize, second current source adopts the second MOS transistor to realize, certain those skilled in the art are to be understood that, first current source and the second current source can also adopt other implementations, the current source etc. of such as cascade structure), be second image current equal with this reference current by reference current mirror image.When the first current lens array 1 is used as to charge to external capacitive 8, the second current lens array 6 is used as electric discharge; Otherwise when the first current lens array 1 is used as to discharge to external capacitive 8, the second current lens array 6 is being used as charging.
3rd current cycle switching array 5 has 1 current input terminal 52, 1 circulating current output 53 and 2 cyclic switching ends 51, the current input terminal 52 of the 3rd current cycle switching array 5 connects the circulating current output 32 of the second current cycle switching array 3, 2 cyclic switching ends 51 of the 3rd current cycle switching array 5 connect the first current source in the second current lens array 6 and the second current source respectively, 3rd current cycle switching array 5 carries out cyclic switching to the first current source and the second current source, make the two alternately as reference source and the output source of current mirror, the first image current that the current input terminal 52 that wherein reference source receives the 3rd current cycle switching array 5 transmits, output source by output second image current to the circulating current output 53 of the 3rd current cycle switching array 5.
Furthermore, after cyclic switching by the 3rd current cycle switching array 5, in second current lens array 6, the first MOS transistor and the second MOS transistor are alternately as reference pipe and efferent duct, the electric current that circulating current output 53 exports is the mean value of the image current that the first MOS transistor and the second MOS transistor export, thus the unmatched problem of reference current of the electric current that exports of the circulating current output 53 that the deviation playing elimination first MOS transistor and the second MOS transistor causes and reference current source 7.
Charging and discharging switch 4 has 2 inputs and 1 output, these 2 inputs are connected respectively to the circulating current output 33 of the second current cycle switching array 3 and the circulating current output 53 of the 3rd current cycle switching array 5, and the output of charging and discharging switch 4 is connected to external capacitive 8 to carry out charge or discharge to it.
Furthermore, within the same clock cycle, the output of charging and discharging switch 4 only with one of them input conducting, and within two clock cycle, the output of charging and discharging switch 4 and 2 each conductings of input of charging and discharging switch 4 are once.
Wherein the first current lens array 1 can adopt the interconnection of multiple nmos pass transistor to realize, and now the second current lens array 6 adopts 2 PMOS transistor interconnection to realize; Otherwise when the first current lens array 1 adopts PMOS transistor to realize, the second current lens array 6 adopts nmos pass transistor to realize.
Improve charge pump charging in the present embodiment, the working method of circuit of discharging current matching degree is summarized as follows: the reference current mirror image of reference current source 7 is become N number of first image current equal with the reference current of reference current source 7 by the first current lens array 1, and the first image current is input to the first current cycle switching array 2, the electric current that circulating current output 22 exports is the electric current that image current input 20 inputs, and the first current cycle switching array 2 makes the electric current exported at N-1 clock cycle Inner eycle current output terminal 23 be the mean value of the first image current of N-1 image current input 21 input through cyclic switching, the electric current that circulating current output 22,23 exports is sent into the second current cycle switching array 3, second current cycle switching array 3 and is made the electric current exported at two clock cycle Inner eycle current output terminals 32,33 be the mean value of the electric current that two current input terminals 30,31 input through cyclic switching, N number of first image current passes through the cyclic switching of the first current cycle switching array 2 and the second current cycle switching array 3, makes the electric current exported at 2 × (N-1) Inner eycle current output terminals of individual clock cycle 32,33 be the mean value of the first image current of N-1 current input terminal 21 input and the first image current of current input terminal 20 input, second current lens array 6 has two current sources, and reference source and the output source alternately as current mirror under the cyclic switching of the 3rd current cycle switching array 5, 3rd current cycle switching array 5 makes the electric current exported at two clock cycle Inner eycle current output terminals 53 be the mean value of the image current that two current sources export through cyclic switching, the electric current that circulating current output 32 exports is used as the reference source electric current of the second current lens array 6, with current input terminal 52 receive electric current be same electric current, the electric current of electric current and circulating current output 33 output exported at 2 × 2 × (N-1) Inner eycle current output terminals 53 of individual clock cycle is made to be the mean value of the mean value of the first image current that N-1 current input terminal 21 inputs and the first image current of current input terminal 20 input, the charging current of charge pump within 2 × 2 × (N-1) individual clock cycle and discharging current is namely made to be the mean value of the mean value of the first image current that N-1 current input terminal 21 inputs and the first image current of current input terminal 20 input.
Circuit shown in Fig. 3 may be used for switch power converter, and this switch power converter can be the various switch power converter being controlled constant current output by charge pump charging, discharging current proportionate relationship in prior art.
Show the detailed circuit diagram of the first embodiment with reference to figure 4, Fig. 4, wherein N equals 3.Be described in detail below.
In a first embodiment, first current lens array 1 comprises nmos pass transistor B0 to B3, and wherein, the grid of nmos pass transistor B1, B2 and B3 is connected to the grid of nmos pass transistor B0, the source ground of nmos pass transistor B0 to B3, the drain electrode of nmos pass transistor B0 to B3 exports the first image current respectively.
First current cycle switching array 2 comprises 3 switches J0, J1 and J2, the first end of the drain electrode connecting valve J0 of nmos pass transistor B1, and the drain electrode of nmos pass transistor B2 is connected to the first end of switch J1, and the drain electrode of nmos pass transistor B3 is connected to the first end of switch J2.Second end of switch J1 and switch J2 links together.In the clock cycle in office, have in switch J1 and switch J2 and only have 1 conducting, and within 2 clock cycle, switch J1 and each conducting of switch J2 are once.
Second current cycle switching array 3 comprises: the first switch Q0, second switch Q2, the 3rd switch Q3 and the 4th switch Q4.Wherein, second end of switch J0 connects the first end of the first switch Q0 and the first end of the 4th switch Q3, switch J1 and second end of switch J2 are connected the first end of second switch Q1 and the first end of the 3rd switch Q2 jointly, second end of the first switch Q0 and second end of second switch Q1 link together (specifically, be connected to the grid of PMOS transistor A1), second end of the 3rd switch Q2 and the 4th switch Q3 links together (first end specifically, being connected to the tenth K switch 1).Wherein, the control end of the first switch Q0 and second switch Q1 receives same control signal, and the control end of second switch Q1 and the 4th switch Q3 receives the inversion signal of this control signal.
3rd cyclic switching array 5 comprises: the 5th switch P 0, the 6th switch P 1, the 7th switch P 2 and the 8th switch P 3.Wherein, the first end of the 5th switch P 0 and the first end of the 6th switch P 1 are connected to the grid of PMOS transistor A1 jointly, and the grid of PMOS transistor A2 is connected to the grid of PMOS transistor A1, and the source electrode of PMOS transistor A1 and PMOS transistor A2 is connected to power supply.The first end of the 7th switch P 2 and the first end of the 8th switch P 3 link together and as the circulating current output of the 3rd cyclic switching array 5, the second end of the 7th switch P 2 connects the drain electrode of PMOS transistor A2; Second end of the 8th switch P 3 and the second end of the 5th switch P 0 are connected to the drain electrode of PMOS transistor A1 jointly.Wherein the control end of the 5th switch P 0 and the 7th switch P 2 receives same control signal, and the control end of the 6th switch P 1 and the 8th switch P 3 receives the inversion signal of this control signal.
Charging and discharging switch 4 comprises the 9th K switch 0 and the tenth K switch 1.Wherein, the first end of the 9th K switch 0 connects the first end of the 7th switch P 2 and the 8th switch P 3, and the second end of the 9th K switch 0 connects one end of external capacitive C0; The first end of the tenth K switch 1 connects second end of the 3rd switch Q2 and the 4th switch Q4, and the second end of the tenth K switch 1 connects one end of external capacitive C0 and the second end of the 9th K switch 0, the other end ground connection of external capacitive C0.Wherein, the control signal that receives of the control end of the 9th K switch 0 and the tenth K switch 1 is mutually anti-phase.
As a nonrestrictive example, the control end of the first switch Q0 and the 3rd switch Q2 controls by same clock signal C 0, and the control end of second switch Q1 and the 4th switch Q3 controls by the inversion signal C1 of same clock signal C 0.The control end suspension control signal C2 of the 9th K switch 0 controls, and the inversion signal C3 of the control end suspension control signal C2 of the tenth K switch 1 controls.The control end of the 5th switch P 0 and the 7th switch P 2 controls by same clock signal C 4, and the control end of the 6th switch P 1 and the 8th switch P 3 controls by the inversion signal C5 of same clock signal C 4.Switch J0 constant conduction, switch J1 subject clock signal C6 controls, and the inversion signal C7 of switch J2 subject clock signal C6 controls.
Clock signal C 0, clock signal C 4 and clock signal C 6 form 8 unit period clocks, and clock signal C 0, C4, C6 cover 000,001,010,011,100,101,110,111 these 8 kinds of states.Control signal C2 is such as the square wave of 50% duty ratio.Suppose
for being mirrored to the transmission error of nmos pass transistor B1 from nmos pass transistor B0, the electric current flowing through nmos pass transistor B1 can be used
represent, wherein I
0represent the current value of reference current, similarly, the transmission error between other MOS transistor and the electric current flowing through each MOS transistor also can adopt as upper type is stated, then every 8 unit period clock charging current I
chargingwith discharging current I
electric dischargeratio is:
Suppose
be 0.7, substitution can obtain:
This shows, adopt the program, charge pump charging, discharging current matching degree are significantly improved.
With reference to figure 5, Fig. 5 shows the detailed circuit diagram of the second embodiment, wherein N equals 2, in the case, 2 switches in first current cycle switching array are all in permanent conducting state, thus the first cyclic switching array can be saved and direct termination, other structures and aforementioned first embodiment similar, be described in detail below.
The grid of nmos pass transistor B0 and drain electrode short circuit, source ground.The grid of nmos pass transistor B1 and NNMOS transistor B2 is connected to the grid of nmos pass transistor B0, source ground.The drain electrode of nmos pass transistor B1 is connected to one end of switch Q0 and Q3, and the drain electrode of nmos pass transistor B2 is connected to one end of switch Q1 and Q2.The other end of switch Q0 and Q1 is connected to the grid of PMOS transistor A1, and the other end of switch Q2 and Q3 is connected to one end of K switch 1.One end of switch P 0 and P1 is connected to the grid of PMOS transistor A1, and the grid of PMOS transistor A2 is connected to the grid of PMOS transistor A1, and the source electrode of PMOS transistor A1, A2 is connected to power supply.The other end of K switch 1 is connected to one end of external capacitive C0 and K switch 0, the other end ground connection of electric capacity C0.The other end of switch P 0 and P3 is connected to the drain electrode of PMOS transistor A1.The other end of switch P 1 and P2 is connected to the drain electrode of PMOS transistor A2.
Switch Q0 and Q2 controls by same clock signal C 0, and switch Q1 and Q3 controls by the inversion signal C1 of same clock signal C 0.K switch 0 suspension control signal C2 controls, and the inversion signal C3 of K switch 1 suspension control signal C2 controls.Switch P 0 and P2 control by same clock signal C 4, and switch P 1 and P3 control by the inversion signal C5 of same clock signal C 4.
Clock signal C 0, clock signal C 4 form 4 unit period clocks, and C0, C4 cover 00,01,10,11 these 4 kinds of states.Control signal C2 can be the square wave of 50% duty ratio.
Suppose
for being mirrored to the transmission error of nmos pass transistor B1 from nmos pass transistor B0, the electric current flowing through nmos pass transistor B1 can be used
represent, wherein I
0represent the current value of reference current, similarly, the transmission error between other MOS transistor and the electric current flowing through each MOS transistor also can adopt as upper type is stated, then every 4 unit period clock charging currents and discharging current ratio are:
Suppose
be 0.7, substitution can obtain
This shows, adopt the program, charge pump charging, discharging current matching degree are significantly improved.
In sum, the invention provides a kind of charge pump to be charged, discharging current switches eliminates process deviation between transistor to the circuit of the impact that matching degree causes through loop cycle, above raising charge pump charges, in the circuit for eliminating of discharging current matching degree prior art due to impact that the deviation between transistor causes matching precision.
Above-described embodiment is just to explanation of the present invention, instead of limitation of the present invention, any innovation and creation do not exceeded in spirit of the present invention, charging circuit and discharge circuit structure is included but not limited to exchange, change clock signal sequential, to the change of the local structure of circuit (as utilize those skilled in the art thinkable technical method replace current source structure in the present invention, electric capacity is replaced to electric capacity with being connected to and is connected to power supply etc.), to the type of components and parts or the replacement (as PMOS is replaced with NMOS tube etc.) of model, and the replacement of other unsubstantialities or amendment, all fall within scope.
Claims (6)
1. improve a circuit for charge pump charging and discharging currents matching degree, it is characterized in that, comprising:
First current lens array, for by reference current mirror image being N number of first image current equal with this reference current, wherein N be greater than 1 integer;
First current cycle switching array, there are N number of current input terminal and 2 circulating current outputs, N number of current input terminal of described first current cycle switching array receives N number of first image current of described first current lens array output respectively, described first current cycle switching array carries out cyclic switching to described N number of first image current, from wherein selecting 2 the first image currents and exporting via described 2 circulating current outputs respectively;
Second current cycle switching array, there are 2 current input terminals, 2 circulating current outputs, 2 current input terminals of described second current cycle switching array connect 2 circulating current outputs of described first current cycle switching array respectively, 2 the first image currents that 2 the circulating current outputs of described second current cycle switching array to described first current cycle switching array export carry out cyclic switching, make the two alternate conduction to 2 circulating current outputs of described second current cycle switching array;
Second current lens array, comprises the first current source and the second current source, is second image current equal with this reference current by described reference current mirror image;
3rd current cycle switching array, there is 1 current input terminal, 1 circulating current output and 2 cyclic switching ends, the current input terminal of described 3rd current cycle switching array connects one in 2 circulating current outputs of described second current cycle switching array, 2 cyclic switching ends of described 3rd current cycle switching array connect the output of described first current source and the second current source respectively, described 3rd current cycle switching array carries out cyclic switching to described first current source and the second current source, make the two alternately as reference source and the output source of current mirror, wherein reference source receives the first image current of the current input terminal transmission of described 3rd current cycle switching array, described second image current is transferred to the circulating current output of described 3rd current cycle switching array by output source,
Charging and discharging switch, there is 2 inputs and 1 output, these 2 inputs are connected respectively to the circulating current output of another and described 3rd current cycle switching array in 2 circulating current outputs of described second current cycle switching array, and this output is connected to external capacitive to carry out charge or discharge to it.
2. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1, it is characterized in that, described first current cycle switching array comprises N number of switch, the first end of this N number of switch receives N number of first image current of described first current lens array output respectively, second end of this N number of one of them switch of switch connects a circulating current output of described first current cycle switching array, second end of another N-1 switch in this N number of switch connects another circulating current output of described first current cycle switching array, have in a described another N-1 switch in the clock cycle in office and only have a conducting, and each conducting of a described another N-1 switch is once within N-1 clock cycle.
3. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1, is characterized in that, described second current cycle switching array comprises:
First switch, its first end connects one in 2 circulating current outputs of described first current cycle switching array;
Second switch, its first end connect in 2 circulating current outputs of described first current cycle switching array another, its second end connect described first switch the second end and as a circulating current output of described second current cycle switching array;
3rd switch, its first end connects the first end of described second switch;
4th switch, its first end connects the first end of described first switch, its second end connect described 3rd switch the second end and as another circulating current output of described second current cycle switching array;
Wherein, the control end of described first switch and the 3rd switch receives same control signal, and the control end of described second switch and the 4th switch receives the inversion signal of described control signal.
4. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1, is characterized in that, described 3rd current cycle switching array comprises:
5th switch, its first end connects the control end of first, second current source described, its second end connect described first current source output and as the current input terminal of described 3rd current cycle switching array;
6th switch, its first end connects the first end of described 5th switch, and its second end connects the output of described second current source;
7th switch, its first end is as the circulating current output of described 3rd current cycle switching array, and its second end connects the output of described second current source;
8th switch, its first end connects the first end of described 7th switch, and its second end connects the second end of described 5th switch;
Wherein, the control end of described 5th switch and the 7th switch receives same control signal, and the control end of described 6th switch and the 8th switch receives the inversion signal of described control signal.
5. the circuit of raising charge pump charging and discharging currents matching degree according to claim 1, it is characterized in that, described charging and discharging switch comprises:
9th switch, its first end connects the circulating current output of described 3rd current cycle switching array, and its second end connects described external capacitive;
Tenth switch, its first end connect described second current cycle switching array 2 circulating current outputs in another, its second end connects described external capacitive;
Wherein, the control signal that receives of the control end of described 9th switch and the tenth switch is mutually anti-phase.
6. a switch power converter, is characterized in that, comprises the circuit of the raising charge pump charging and discharging currents matching degree according to any one of claim 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210595125.4A CN103001489B (en) | 2012-12-31 | 2012-12-31 | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210595125.4A CN103001489B (en) | 2012-12-31 | 2012-12-31 | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump |
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| Publication Number | Publication Date |
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| CN103001489A CN103001489A (en) | 2013-03-27 |
| CN103001489B true CN103001489B (en) | 2015-01-07 |
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| CN201210595125.4A Active CN103001489B (en) | 2012-12-31 | 2012-12-31 | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6124741A (en) * | 1999-03-08 | 2000-09-26 | Pericom Semiconductor Corp. | Accurate PLL charge pump with matched up/down currents from Vds-compensated common-gate switches |
| US7385429B1 (en) * | 2005-05-31 | 2008-06-10 | Altera Corporation | Charge pump with reduced current mismatch |
| CN101888178A (en) * | 2010-06-13 | 2010-11-17 | 浙江大学 | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop |
| CN201754557U (en) * | 2010-07-30 | 2011-03-02 | 苏州科山微电子科技有限公司 | Charge pump capable of solving problems of charge distribution and current mismatch |
| CN102255498A (en) * | 2011-06-28 | 2011-11-23 | 上海宏力半导体制造有限公司 | Charge pump circuit |
| CN203014674U (en) * | 2012-12-31 | 2013-06-19 | 杭州士兰微电子股份有限公司 | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump |
-
2012
- 2012-12-31 CN CN201210595125.4A patent/CN103001489B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6124741A (en) * | 1999-03-08 | 2000-09-26 | Pericom Semiconductor Corp. | Accurate PLL charge pump with matched up/down currents from Vds-compensated common-gate switches |
| US7385429B1 (en) * | 2005-05-31 | 2008-06-10 | Altera Corporation | Charge pump with reduced current mismatch |
| CN101888178A (en) * | 2010-06-13 | 2010-11-17 | 浙江大学 | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop |
| CN201754557U (en) * | 2010-07-30 | 2011-03-02 | 苏州科山微电子科技有限公司 | Charge pump capable of solving problems of charge distribution and current mismatch |
| CN102255498A (en) * | 2011-06-28 | 2011-11-23 | 上海宏力半导体制造有限公司 | Charge pump circuit |
| CN203014674U (en) * | 2012-12-31 | 2013-06-19 | 杭州士兰微电子股份有限公司 | Switch power inverter and circuit for improving charging and discharging current matching degree of charge pump |
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| Publication number | Publication date |
|---|---|
| CN103001489A (en) | 2013-03-27 |
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