CN103021843A - Improved method of bipolar integrated circuit amplification coefficient process - Google Patents

Abstract

The invention relates to an improved method of a bipolar integrated circuit amplification coefficient process, comprising a step of manufacturing a basic circuit of a bipolar integrated circuit compatible with a BJT (Bipolar Junction Transistor) and a JFET (Junction Field-Effect Transistor) by a conventional process, a step of manufacturing an electrode lead wire on the basic circuit and a step of carrying out follow-up process arrangement. The improved method is characterized in that the step of manufacturing the electrode lead wire on the basic circuit comprises the steps of: 1, primary photoetching and corrosion on a contact hole; 2, hole oxidization; 3, silicon nitride deposition; 4, secondary photoetching and hole secondary corrosion on the contact hole; 5, pure aluminum sputtering; and 6, formation of the electrode lead wire (25) and a press welding point by the photoetching and the corrosion. The improved method disclosed by the invention has the following advantages that (1) the stress of a silicon nitride dielectric film is effectively released so as to be matched with the property of bipolar circuits; (2) the attenuation of a PNP pipe amplification coefficient is effectively prevented and the PNP pipe amplification coefficient is stabilized; and (3) a technological approach is easy to realize.

Description

A kind of bipolar integrated circuit amplification coefficient process modification method

Technical field

The present invention relates to field of semiconductor fabrication processes, particularly a kind of process of improving the bipolar integrated circuit amplification coefficient.

Background technology

Amplification coefficient is an important performance characteristic index during bipolar integrated circuit is made, and its stability is the reliability of decision-making circuit directly.At more existing BJT with silicon nitride and JFET mutually in the compatible bipolar integrated circuit manufacturing process, before the fairlead reticle, used the silicon nitride medium film, because stress characteristics and this kind circuit Incomplete matching of silicon nitride medium film, when the horizontal and vertical PNP of this type of bipolar circuit of test pipe amplification coefficient, show the bad phenomenon of ohmic contact of contact hole logical or aluminum lead and silicon substrate, and in fact this is that situation about showing after the decay has appearred in the amplification coefficient of PNP pipe, and this does not reach technical indicator with regard to the circuit that causes producing.

Summary of the invention

Purpose of the present invention is exactly for stress characteristics and this kind circuit Incomplete matching owing to the silicon nitride medium film, the defective that causes this type of bipolar circuit amplification coefficient to decay, a kind of bipolar integrated circuit amplification coefficient process modification method that provides are provided.

To achieve these goals, the present invention has adopted following technical scheme:

A kind of bipolar integrated circuit amplification coefficient process modification method, comprise common process make BJT and JFET mutually the basic circuit of compatible bipolar integrated circuit step, make contact conductor step and subsequent technique arrangement step at basic circuit, it is characterized in that the step of making contact conductor on the described basic circuit is:

A, basic circuit surface deposition LTO:

Under 420 ℃ furnace temperature, by the silicon dioxide LTO layer (20) of LPCVD deposit one deck 450nm, then the LTO layer to deposit carries out density under 850 ℃ temperature;

B, a photoetching of contact hole:

Utilize the photo etched mask technology, form the figure of the lead-in wire contact hole (21) in the basic circuit; Through etching of via hole the oxide layer in the contact hole is removed totally, formed lead-in wire contact hole (21);

C, the hole oxidation of lead-in wire contact hole:

Logical snperoxiaized mode is growth certain thickness oxide layer (22) in LTO layer and lead-in wire contact hole;

D, deposit silicon nitride:

On the oxide layer of oxide layer (22) and lead-in wire contact hole, by LPCVD deposit one deck silicon nitride film (23);

E, the photoetching of lead-in wire contact hole secondary:

Utilize the photo etched mask technology, each lead-in wire contact hole (21) is carried out the alignment second time; And silicon nitride film (23) and oxide layer (22) etching in the contact hole that will go between are clean, in the secondary lead wires hole (24) of bottom formation less than lead-in wire contact hole (21), each secondary lead wires hole (24) is respectively with base boron (14), emitter region phosphorus (16) and grid region phosphorus (19) contact accordingly in the following basic circuit;

F, spatter fine aluminium:

Pure aluminium film at basic circuit surface sputtering one deck 1.2～1.5 μ m;

G, the photoetching of aluminum steel bar:

Utilize photoetching technique, form concrete aluminium line and pressure welding point figure; Then use rotten aluminium liquid that aluminium erosion unnecessary on the litho pattern is clean, form respectively the contact conductor (25) and the pressure welding point that link to each other with corresponding base boron (14), emitter region phosphorus (16) and grid region phosphorus (19).

  

Owing to adopted technique scheme, the present invention to have following advantage: (1) is the stress of liberating nitrogen SiClx deielectric-coating effectively, and the characteristic of itself and this type of bipolar circuit is complementary; (2) effectively prevent PNP to manage the decay of amplification coefficient, stablize PNP pipe amplification coefficient; (3) technological approaches is easy to realize.

Description of drawings:

Fig. 1-Fig. 6 is each processing step structure chart of making contact conductor on the basic circuit of the present invention.

Embodiment

A kind of bipolar integrated circuit amplification coefficient process modification method provided by the invention, comprise common process make BJT and JFET mutually the basic circuit of compatible bipolar integrated circuit step, make the contact conductor step and subsequent technique is put step in order at basic circuit.

Described basic circuit comprises bottom silicon P substrate 1, N _-Epitaxial loayer 9, P+ district 12, N+ district 4, base boron (14), emitter region phosphorus (16) and grid region phosphorus (19).

The invention is characterized in that the step of making contact conductor on the described basic circuit is:

A, deposit LTO---as shown in Figure 1, under 420 ℃ furnace temperature, by the LPCVD(vapor phase growing apparatus) silicon dioxide 20 about deposit one deck 450nm, as the circuit capacitance dielectric layer; Then the LTO layer to deposit carries out density under 850 ℃ temperature, increases the compactness of LTO dielectric layer;

B, a photoetching of contact hole---as shown in Figure 2, utilize the photo etched mask technology, form the figure of circuit lead contact hole 21; Through etching of via hole the oxide layer in the contact hole is removed totally, formed circuit lead contact hole 21;

C, lead-in wire contact hole hole oxidation-as shown in Figure 3, lead to snperoxiaized mode certain thickness oxide layer 22 of growth in LTO layer and lead-in wire contact hole;

D, deposit silicon nitride---as shown in Figure 4, pass through LPCVD deposit one deck silicon nitride film 23 in oxide layer 22 and lead-in wire contact hole;

E, the photoetching of lead-in wire contact hole secondary---as shown in Figure 5, utilize the photo etched mask technology, the circuit contact hole is carried out the alignment second time; And the silicon nitride 23 in the contact hole and oxide layer 22 etchings is clean, form the little fairlead 24 less than lead-in wire contact hole 21 in the bottom, little fairlead 24 contacts with following base boron 14;

F, spatter fine aluminium---as shown in Figure 6, at the pure aluminium film of substrate surface sputter one deck (1.2～1.5) μ m, as aluminium line and contact conductor;

G, the photoetching of aluminum steel bar---as shown in Figure 6, utilize photoetching technique, form concrete aluminium line and pressure welding point figure; Then use rotten aluminium liquid that aluminium erosion unnecessary on the litho pattern is clean, form aluminium line 25 and pressure welding point.

  

Below connect conventional subsequent technique arrangement step

I, alloy carry out alloy annealing 20min under 420 ℃ of nitrogen, make aluminium pressure welding point and silicon substrate form good ohmic and contact;

J, passivation utilize the composite membrane of PECVD deposit layer of silicon dioxide and silicon nitride under 380 ℃ temperature, and thickness is respectively 650nm and 250nm, as the protective layer of circuit surface;

K, passivation layer photoetching utilize photoetching technique, form the protective layer figure;

L, PD dry corrosion adopt dry etching, and the passivation layer etching on the circuit pressure welding point is clean;

Alloy annealing 20min is carried out in m, alloy annealing under 500 ℃ of nitrogen, strengthen the ohmic contact of aluminium pressure welding point and silicon substrate, eliminates simultaneously passivating film stress;

N, the test of PED single tube are tested circuit single tube function, determine whether circuit arrives requirement.

Utilize above-mentioned technological process, can effectively discharge silicon nitride film stress, successfully prevent the decay of this type of bipolar integrated circuit PNP pipe amplification coefficient, the amplification coefficient of its horizontal and vertical PNP pipe can reach following index respectively:

Lateral PNP:

β 〉=10 (V _CE=-5V, I _B=1 μ A/ level)

Longitudinal P NP:

β 〉=15 (V _CE=-5V, I _B=1 μ A/ level).

Claims (1)

1. bipolar integrated circuit amplification coefficient process modification method, comprise common process make BJT and JFET mutually the basic circuit of compatible bipolar integrated circuit step, make contact conductor step and subsequent technique arrangement step at basic circuit, it is characterized in that the step of making contact conductor on the described basic circuit is:

A, basic circuit surface deposition LTO:

Under 420 ℃ furnace temperature, by the silicon dioxide LTO layer (20) of LPCVD deposit one deck 450nm, then the LTO layer to deposit carries out density under 850 ℃ temperature;

B, a photoetching of contact hole:

Utilize the photo etched mask technology, form the figure of the lead-in wire contact hole (21) in the basic circuit; Through etching of via hole the oxide layer in the contact hole is removed totally, formed lead-in wire contact hole (21);

C, the hole oxidation of lead-in wire contact hole:

Logical snperoxiaized mode is growth certain thickness oxide layer (22) in LTO layer and lead-in wire contact hole;

D, deposit silicon nitride:

On the oxide layer of oxide layer (22) and lead-in wire contact hole, by LPCVD deposit one deck silicon nitride film (23);

E, the photoetching of lead-in wire contact hole secondary:

Utilize the photo etched mask technology, each lead-in wire contact hole (21) is carried out the alignment second time; And silicon nitride film (23) and oxide layer (22) etching in the contact hole that will go between are clean, in the secondary lead wires hole (24) of bottom formation less than lead-in wire contact hole (21), each secondary lead wires hole (24) is respectively with base boron (14), emitter region phosphorus (16) and grid region phosphorus (19) contact accordingly in the following basic circuit;

F, spatter fine aluminium:

Pure aluminium film at basic circuit surface sputtering one deck 1.2～1.5 μ m;

G, the photoetching of aluminum steel bar:

Utilize photoetching technique, form concrete aluminium line and pressure welding point figure; Then use rotten aluminium liquid that aluminium erosion unnecessary on the litho pattern is clean, form respectively the contact conductor (25) and the pressure welding point that link to each other with corresponding base boron (14), emitter region phosphorus (16) and grid region phosphorus (19).

Images