CN103035478B - Back-end process control method of wafer - Google Patents
Back-end process control method of wafer Download PDFInfo
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- CN103035478B CN103035478B CN201110296321.7A CN201110296321A CN103035478B CN 103035478 B CN103035478 B CN 103035478B CN 201110296321 A CN201110296321 A CN 201110296321A CN 103035478 B CN103035478 B CN 103035478B
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Abstract
The invention provides a back-end process control method of a wafer. The method utilizes at least one control process for adjusting the semiconductor wafer manufacture process and is capable of conducting timely adjustment and improving product reliability when errors occur in the manufacture process of the back-end process of the wafer.
Description
Technical field
The present invention relates to integrated circuit fabrication process, particularly a kind of wafer back-end process control method.
Background technology
In integrated circuit fabrication process, the performance of characteristic size to device of device is most important.When the characteristic size of device can meet the requirement preset, it often can make the resistance of device, capacitance characteristic is greatly enhanced, and reduces signal delay and power consumption, improves electron mobility etc.
The manufacture of semiconductor crystal wafer must go through a technological process, and this flow process comprises the such as various different semiconductor wafer process step such as etching and photoetching.Traditional manufacturing process can comprise 300 ~ 400 steps, and wherein each step all can affect the final pattern of device on this semiconductor crystal wafer, namely affects the characteristic size of device, thus affects the various electrical characteristics of device.Traditional technological process can be divided into the secondary technological process that two classes are main, be respectively FEOL (front end of line, FEOL) and back-end process (back end of line, BEOL).
Traditional FEOL by the laser labelling of wafer, and following shallow trench isolation from formation, form P trap and the ion implantation of N trap, the etching of polysilicon, and the ion implantation in the multiple region such as the drain electrode of such as transistor arrangement and source electrode.
Back-end process can comprise the formation of metal level, and the metal interlevel metal interconnecting wires of different layers, the formation of contact hole (via contact) on wafer, usually has two-layer or more metal level.When forming the structure of above-mentioned back-end process, usually, will use the processing steps such as chemical vapor deposition method (CVD), photoetching process (Lithography), etching technics (Etch), physical gas-phase deposition (PVD) and chemical mechanical milling tech (CMP), all there is correlation between each processing step, namely the error of previous step often will chain reaction in subsequent step, thus finally cause the characteristic size of device not meet preset requirement, reduce device performance.
Please refer to Fig. 1, it is the device profile schematic diagram in existing wafer back-end process after physical gas-phase deposition.As shown in Figure 1, after have passed through chemical vapor deposition method, photoetching process, etching technics and physical gas-phase deposition, often there is the situation that the rete of formation is blocked up or excessively thin, when the rete formed is excessively thin time, challenge is proposed to follow-up chemical mechanical milling tech, namely the rete giving chemical mechanical milling tech will be thinner, thus higher to the control overflow of chemical mechanical milling tech; When the rete formed is excessively thin time, need again when chemical mechanical milling tech, remove more rete, thus make the characteristic size of formed device can meet default requirement.Especially, one rete often will form different device architectures in the zones of different of wafer, as shown in Figure 1, such as utilize the silicon dioxide of same doping carbon (also known as black diamond, Black Diamond, BD) layer forms damascene structure (Dualdamascene structure, DD), barrier liner district (Isolation pad area, ISO), wafer acceptance test district (wafer acceptance test, WAT), therefore the accurate control of technique is more needed, to improve the reliability of device.In prior art, the process conditions of each technique set, often after there occurs obvious fabrication error, such as, in the situation such as the characteristic size of the large quantities of products is defective, just can adjust the process conditions of relevant technological in back-end process, thus reduce the reliability of product.In addition, because processing step involved in back-end process is many, goes out at which processing step by the defective very difficult discovery particular problem of final products, thus, also bring very large difficulty to technique adjustment.
Summary of the invention
The object of the present invention is to provide a kind of wafer back-end process control method, manufacturing process error can not be solved in time to solve in existing wafer back-end process, thus reduce the problem of product reliability.
For solving the problems of the technologies described above, the invention provides a kind of wafer back-end process control method, comprising: multiple tracks semiconductor wafer manufacturing technique and at least one is in order to adjust the Controlling Technology of semiconductor wafer manufacturing technique.
Optionally, in described wafer back-end process control method, described Controlling Technology comprises feedfoward control and FEEDBACK CONTROL.
Optionally, in described wafer back-end process control method, described semiconductor wafer manufacturing technique comprises: one or more in chemical vapor deposition method, photoetching process, etching technics, physical gas-phase deposition and chemical mechanical milling tech.
Optionally, in described wafer back-end process control method, described feedfoward control comprises the first feedfoward control, and in order to adjust described etching technics, wherein, the feedback parameter of described first feedfoward control is the process results of described chemical vapor deposition method.
Optionally, in described wafer back-end process control method, described feedfoward control also comprises the second feedfoward control, and in order to adjust described etching technics, wherein, the feedback parameter of described second feedfoward control is the process results of described photoetching process.
Optionally, in described wafer back-end process control method, described FEEDBACK CONTROL comprises the first FEEDBACK CONTROL, and in order to adjust described etching technics, wherein, the feedback parameter of described first FEEDBACK CONTROL is the process results of described etching technics.
Optionally, in described wafer back-end process control method, adjust described etching technics and comprise: adjust the process time of described etching technics and/or adjust the etching gas flow of described etching technics.
Optionally, in described wafer back-end process control method, described feedfoward control also comprises the 3rd feedfoward control, and in order to adjust described physical gas-phase deposition, wherein, the feedback parameter of described 3rd feedfoward control is the process results of described etching technics.
Optionally, in described wafer back-end process control method, adjust described physical gas-phase deposition and comprise: the process time adjusting described physical gas-phase deposition.
Optionally, in described wafer back-end process control method, described feedfoward control also comprises the 4th feedfoward control, and in order to adjust described chemical mechanical milling tech, wherein, the feedback parameter of described 4th feedfoward control is the process results of described etching technics.
Optionally, in described wafer back-end process control method, described feedfoward control also comprises the 5th feedfoward control, in order to adjust described chemical mechanical milling tech, wherein, the feedback parameter of described 5th feedfoward control is the process results of described physical gas-phase deposition.
Optionally, in described wafer back-end process control method, adjust described chemical mechanical milling tech and comprise: the process time adjusting described chemical mechanical milling tech.
In wafer back-end process control method provided by the invention, make use of at least one in order to adjust the Controlling Technology of semiconductor wafer manufacturing technique, when there is error in the manufacturing process of wafer back-end process, can adjust in time, thus improve product reliability.
Accompanying drawing explanation
Fig. 1 is the device profile schematic diagram in existing wafer back-end process after physical gas-phase deposition;
Fig. 2 is the schematic flow sheet of the wafer back-end process control method of the embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the wafer back-end process control method that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, make use of at least one in order to adjust the Controlling Technology of semiconductor wafer manufacturing technique, when there is error in the manufacturing process of wafer back-end process, can adjust in time, thus improves product reliability.
Please refer to Fig. 2, it is the schematic flow sheet of the wafer back-end process control method of the embodiment of the present invention.As shown in Figure 2, in the present embodiment, wafer back-end process control method specifically comprises the steps:
First, step S10 is performed: chemical vapor deposition method.In this step, certain thickness rete can be formed by chemical vapor deposition method, such as, preset and need to form the silicon dioxide (also known as black diamond, Black Diamond, BD) that thickness is the doping carbon of 1000 dusts.Such as, but after chemical vapor deposition method, might not form the thickness preset, the thickness of the black diamond formed may be 990 dusts or 1010 dusts, namely higher or on the low side compared to the thickness preset.
Therefore, in the present embodiment, perform the step S100: the first feedfoward control, the process results of step S10 (chemical vapor deposition method) is supplied to step S30 (etching technics) as feedback parameter, by this first feedfoward control to adjust the process conditions of the follow-up step S30 (etching technics) that will perform, the process time and/or etching gas flow that adjust described etching technics can be comprised.Such as, by performing step S10: the rete that chemical vapor deposition method is formed is partially thicker than the rete preset, then, now, can be extended the process time of follow-up etching technics by described first feedfoward control.
In the present embodiment, after completing steps S10 (chemical vapor deposition method), then perform step S20 (photoetching process).Wherein, step S20 (photoetching process) does not interact with the execution of step S100 (the first feedfoward control), therefore, in the present embodiment, photoetching process and the first feedfoward control perform simultaneously, to reduce the technique time of implementation, improve execution efficiency.In other embodiments of the invention, described photoetching process and the first feedfoward control also can different time perform.By performing step S20 (photoetching process) to form required device pattern, but, when performing photoetching process, may under-exposure be there is, thus make the problems such as formed etching pattern defectiveness.
Therefore, in the present embodiment, after execution step S20 (photoetching process), perform step S200 (the second feedfoward control), by this second feedfoward control to adjust the process conditions of the follow-up step S30 (etching technics) that will perform, the process time and/or etching gas flow that adjust described etching technics can be comprised.
At completing steps S20: after photoetching process, then perform step S30 (etching technics).Wherein, if step S200 (the second feedfoward control) performs before the step S30 (etching technics), then can set-up procedure S30 (photoetching process) at the right time; If step S200 (the second feedfoward control) and step S30 (etching technics) perform simultaneously, or be later than step S30 (etching technics), then time delay will not be produced on wafer manufacturing process, namely production efficiency is maintained, in the present invention, the order of step S30 and step S200 is not limited.
Because etching technics may occur to etch problem that is not enough or over etching, therefore, after execution step S30 (etching technics), perform step S300 (the first FEEDBACK CONTROL), adjust later etching technics by the process results of this etching technics, prevent the large batch of etching problem of follow-up generation.In addition, if there occurs the problem of etching deficiency or over etching, also made up by other follow-up steps, therefore, after execution step S30 (etching technics), also perform step S400 (the 3rd feedfoward control), the process results of step S30 (etching technics) is supplied to step S40 (physical gas-phase deposition) as feedback parameter by the 3rd feedfoward control, with the process conditions of set-up procedure S40 (physical gas-phase deposition), the process time etc. adjusting described physical gas-phase deposition can be comprised.
In addition, after execution step S30 (etching technics), also perform step S500 (the 4th feedfoward control), the process results of step S30 (etching technics) is supplied to step S50 (chemical mechanical milling tech) as feedback parameter by the 4th feedfoward control, with the process conditions of set-up procedure S50 (chemical mechanical milling tech), the process time etc. adjusting described chemical mechanical milling tech can be comprised.
By the adjustment to subsequent step S40 and step S50, reduce the error that step S30 occurs, thus improve the reliability of product.Wherein, execution sequence between step S40 and step S400 can execution sequence between refer step S30 and step S200, and execution sequence between step S40 and step S500 can execution sequence between refer step S20 and step S100, the present invention repeats no more this.
After completing steps S30 (etching technics), perform step S40 (physical gas-phase deposition).Certain thickness rete can be formed by described physical gas-phase deposition, wherein, the thicknesses of layers formed by step S400 (the 3rd feedfoward control) adjustable step S40 (physical gas-phase deposition).If when over etching occurs step S30 (etching technics), formed thicknesses of layers can be improved in this step S40.In addition, due to when performing step S40 (physical gas-phase deposition), the situation that the thicknesses of layers that yet can occur to be formed is not inconsistent with the requirement preset.
Therefore, in the present embodiment, perform step S600 (the 5th feedfoward control), the process results of step S40 (physical gas-phase deposition) is supplied to step S50 (chemical mechanical milling tech) as feedback parameter by described 5th feedfoward control, by the 5th feedfoward control to adjust the process conditions of the follow-up step S50 (chemical mechanical milling tech) that will perform, the process time etc. adjusting described chemical mechanical milling tech can be comprised.
After execution step S40 (physical gas-phase deposition), perform step S50 (chemical mechanical milling tech).The process conditions of described chemical mechanical milling tech are subject to the adjustment of step S500 (the 4th feedfoward control) and step S600 (the 5th feedfoward control), to improve the reliability of chemical mechanical milling tech.
Wafer back-end process control method provided by the invention, make use of at least one in order to adjust the Controlling Technology of semiconductor wafer manufacturing technique, when there is error in the manufacturing process of wafer back-end process, can adjust in time, thus improves product reliability.
In addition, wafer back-end process control method provided by the invention carries out overall-in-one control schema to the back-end process of whole wafer, namely a certain step semiconductor wafer manufacturing technique of not single adjustment, but carry out integrated regulation, improve efficiency and the reliability of technique adjustment, thus further increase the reliability of product.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (9)
1. a wafer back-end process control method, is characterized in that, comprising: multiple tracks semiconductor wafer manufacturing technique and at least one is in order to adjust the Controlling Technology of semiconductor wafer manufacturing technique;
Described Controlling Technology comprises feedfoward control and FEEDBACK CONTROL;
Described semiconductor wafer manufacturing technique comprises: one or more in chemical vapor deposition method, photoetching process, etching technics, physical gas-phase deposition and chemical mechanical milling tech;
Described feedfoward control comprises the first feedfoward control, and in order to adjust described etching technics, wherein, the feedback parameter of described first feedfoward control is the process results of described chemical vapor deposition method.
2. wafer back-end process control method as claimed in claim 1, it is characterized in that, described feedfoward control also comprises the second feedfoward control, in order to adjust described etching technics, wherein, the feedback parameter of described second feedfoward control is the process results of described photoetching process.
3. wafer back-end process control method as claimed in claim 1, it is characterized in that, described FEEDBACK CONTROL comprises the first FEEDBACK CONTROL, and in order to adjust described etching technics, wherein, the feedback parameter of described first FEEDBACK CONTROL is the process results of described etching technics.
4. the wafer back-end process control method as described in any one in claims 1 to 3, is characterized in that, adjusts described etching technics and comprises: adjust the process time of described etching technics and/or adjust the etching gas flow of described etching technics.
5. wafer back-end process control method as claimed in claim 1, it is characterized in that, described feedfoward control also comprises the 3rd feedfoward control, in order to adjust described physical gas-phase deposition, wherein, the feedback parameter of described 3rd feedfoward control is the process results of described etching technics.
6. wafer back-end process control method as claimed in claim 5, is characterized in that, adjust described physical gas-phase deposition and comprise: the process time adjusting described physical gas-phase deposition.
7. wafer back-end process control method as claimed in claim 1, it is characterized in that, described feedfoward control also comprises the 4th feedfoward control, in order to adjust described chemical mechanical milling tech, wherein, the feedback parameter of described 4th feedfoward control is the process results of described etching technics.
8. wafer back-end process control method as claimed in claim 1, it is characterized in that, described feedfoward control also comprises the 5th feedfoward control, in order to adjust described chemical mechanical milling tech, wherein, the feedback parameter of described 5th feedfoward control is the process results of described physical gas-phase deposition.
9. wafer back-end process control method as claimed in claim 7 or 8, is characterized in that, adjust described chemical mechanical milling tech and comprise: the process time adjusting described chemical mechanical milling tech.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6486492B1 (en) * | 1999-06-29 | 2002-11-26 | Applied Materials, Inc. | Integrated critical dimension control for semiconductor device manufacturing |
| TW530319B (en) * | 2000-06-09 | 2003-05-01 | Advanced Micro Devices Inc | Method and apparatus for using scatterometry to perform feedback and feed-forward control |
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| US6567717B2 (en) * | 2000-01-19 | 2003-05-20 | Advanced Micro Devices, Inc. | Feed-forward control of TCI doping for improving mass-production-wise, statistical distribution of critical performance parameters in semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6486492B1 (en) * | 1999-06-29 | 2002-11-26 | Applied Materials, Inc. | Integrated critical dimension control for semiconductor device manufacturing |
| TW530319B (en) * | 2000-06-09 | 2003-05-01 | Advanced Micro Devices Inc | Method and apparatus for using scatterometry to perform feedback and feed-forward control |
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