CN103094251B - For evaluating the test structure of OPC effect - Google Patents
For evaluating the test structure of OPC effect Download PDFInfo
- Publication number
- CN103094251B CN103094251B CN201110335409.5A CN201110335409A CN103094251B CN 103094251 B CN103094251 B CN 103094251B CN 201110335409 A CN201110335409 A CN 201110335409A CN 103094251 B CN103094251 B CN 103094251B
- Authority
- CN
- China
- Prior art keywords
- cmos
- monocrystalline silicon
- cmos device
- evaluating
- silicon active
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a kind of test structure for evaluating CMOS polysilicon layer OPC effect, this structure comprises 2N cmos device, a set of cmos semiconductor explained hereafter comprising OPC process is accordingly adopted according to setting size, using N number of cmos device as a group pattern, this array Yin Butu mode is different and be divided into 2 groups, one group as check groups, another group is as reference group; Cmos device in check groups, the spacing of its L conformal polysilicon distance monocrystalline silicon active area equals e; Cmos device in reference group, the spacing of its L conformal polysilicon distance monocrystalline silicon active area is more than or equal to 2e; E is the minimum range of the L conformal polysilicon in this cover cmos semiconductor technological design rule apart from the monocrystalline silicon active area of same MOS.The invention also discloses a kind of test structure for evaluating CMOS monocrystalline silicon active region layer OPC effect.Whether test structure of the present invention, can eliminate the impact of corner rounding effect on device property according to device electrology characteristic data detection OPC intuitively.
Description
Technical field
The present invention relates to semiconductor technology, particularly for evaluating the test structure of OPC effect, comprising the test structure for evaluating CMOS polysilicon layer OPC effect, and for evaluating the test structure of CMOS monocrystalline silicon active region layer OPC effect.
Background technology
Photoetching is the main technique of IC manufacturing, and the task of photoetching process realizes figure on mask to the transfer on silicon face layers of material.Projected light is by propagating on silicon chip after mask pattern, mask pattern, concerning light wave, is equivalent to the obstacle on round, thus on silicon chip, obtains the litho pattern relevant to mask pattern.According to Diffraction of light wave and principle of interference, by will diffraction be there is during mask in light wave, light wave between mask diverse location also can interfere, and the light distribution be therefore actually projected on silicon chip is the stack result of diffraction light wave, and it and mask pattern are not identical.
According to Diffraction of light wave principle, when the size of barrier is much larger than optical wavelength, the figure deviation produced by diffraction is negligible, that is, when mask graph size (characteristic size of integrated circuit) is much larger than optical wavelength, on silicon chip, litho pattern and mask graph are substantially identical.But under Super deep submicron process, integrated circuit feature size is at 0.13um even below 0.09um, and close to being even less than optical wavelength, the diffracting effect of light will clearly, and the needle drawing of silicon chip glazing cannot be ignored just as the deviation between mask graph.Along with integrated circuit feature size constantly reduces, the distortion of this litho pattern and deviation become more and more serious, become the key factor affecting chip performance and rate of finished products.
Particularly at the position that figure is close to mutually, due to optical interference and diffraction obvious, figure deviation can be relatively large, such as just obvious in line end top and figure corner deviation, and these figure positions are often to the place that electric property and the circuit performance of circuit play a crucial role, thus have impact on the performance of whole chip, even cause circuit malfunction.This due to Diffraction of light wave, interference and the phenomenon making litho pattern and mask pattern produce deviation is called optical proximity effect (OPE:opticalproximity effect).In a lithographic process, optical proximity effect is inevitable, and corresponding measure therefore must be adopted to reduce mask pattern as much as possible to the distortion of silicon slice pattern and deviation, to ensure performance and the rate of finished products of chip.
The method that current industrial quarters generally adopts between traditional physical Design and mask manufacture, adds the mask that rate of finished products drives correct, in this step, the distortion of the litho pattern produced in photoetching process is made up by changing the shape of figure or the phase place of figure printing opacity on mask, the figure that photoetching on silicon chip is obtained and the figure of expection meet substantially, the compensation mechanism of this mask graph is called photoetching enhancing technology (RET:reticle enhancement technology), two kinds of conventional methods are that optical proximity effect corrects (OPC:optical proximity correction) and phase shift mask (PSM:phase shift mask), wherein OPC is a kind of effective photoetching enhancing technology.
Along with constantly reducing of technique live width, to 90nm and following technique, corner rounding (cornerrounding) effect is more remarkable on the impact of figure, for some key levels, for some narrow raceway grooves or short channel device (small size device), this effect directly can affect device property, so also more and more higher to the requirement of OPC, wish to make corner rounding effect can not have influence on the channel region of device by OPC, thus make device property not by the impact of corner rounding effect.
Such as, for the polysilicon layer of cmos device, namely define the level of the channel length (Lch) of cmos device, optical proximity effect corrects the impact of corner rounding effect for device that OPC need eliminate this layer; For monocrystalline silicon active region layer, namely define the level of the channel width (Wch) of cmos device, OPC need eliminate the impact of corner rounding effect for device of this layer.
The so how rectification effect of OPC scheme that uses of accurate evaluation, current evaluation method just rests on the dimension of picture Data Collection of physical structure, these data are comparatively large by the impact of the factor such as operating personnel, test position, and intuitively can not be reflected to the impact of corners effect on device property.
Summary of the invention
The technical problem to be solved in the present invention is, whether can eliminate the impact of corner rounding effect on device property intuitively according to device electrology characteristic data detection OPC.
For solving the problems of the technologies described above, the invention provides a kind of test structure for evaluating CMOS polysilicon layer OPC effect, described test structure comprises 2*N cmos device, N be more than or equal to 3 integer, adopt a set of cmos semiconductor explained hereafter comprising OPC process accordingly according to setting size;
N number of cmos device in a described 2*N cmos device is as check groups;
N number of cmos device in a described 2*N cmos device is as reference group;
Cmos device in described check groups, the spacing of its L conformal polysilicon distance monocrystalline silicon active area equals e;
Cmos device in described reference group, the spacing of its L conformal polysilicon distance monocrystalline silicon active area is more than or equal to 2e;
E is the minimum range of the L conformal polysilicon in this cover cmos semiconductor technological design rule apart from the monocrystalline silicon active area of same MOS.
The grid of each cmos device, source, leakage, with many finger-like, realize domain by through hole and metal with parallel form, and wherein grid number in parallel is more than or equal to 3.
The channel width of each cmos device, be more than or equal to f, and be more than or equal to (2c+a), and be less than 1um, f is the minimum channel width in this cover cmos semiconductor technological design rule, c is the minimum dimension that monocrystalline silicon active area in this cover cmos semiconductor technological design rule encases through hole, and a is the size of the through hole in this cover cmos semiconductor technological design rule.
The channel width scope of each cmos device is at 0.2 ~ 0.5um.
The channel length of each cmos device, is more than or equal to g, and g is the minimum channel length in this cover cmos semiconductor technological design rule.
For solving the problems of the technologies described above, present invention also offers a kind of test structure for evaluating CMOS monocrystalline silicon active region layer OPC effect, described test structure comprises 2*N cmos device, N be more than or equal to 3 integer, adopt a set of cmos semiconductor explained hereafter comprising OPC process accordingly according to setting size;
N number of cmos device in a described 2*N cmos device is as check groups;
N number of cmos device in a described 2*N cmos device is as reference group;
Cmos device in described check groups, the spacing of the polysilicon on the L shape active area monocrystalline silicon distance raceway groove of its source and drain equals h;
Cmos device in described reference group, the spacing of the polysilicon on the L shape active area monocrystalline silicon distance raceway groove of its source and drain is more than or equal to 2h;
H is the minimum range of the L shape monocrystalline silicon active area in this cover cmos semiconductor technological design rule apart from the polysilicon of same MOS.
The grid of each cmos device, source, leakage, with many finger-like, realize domain by through hole and metal with parallel form, and wherein grid number in parallel is more than or equal to 3.
The channel width of each cmos device, is more than or equal to f, and f is the minimum channel width in this cover cmos semiconductor technological design rule.
The channel length of each cmos device, is more than or equal to g, and g is the minimum channel length in this cover cmos semiconductor technological design rule.
The projection of L shape monocrystalline silicon active area is more than or equal to the minimum dimension of this cover cmos semiconductor technological design rule predetermining;
L conformal polysilicon is more than or equal to 2e apart from the distance of the monocrystalline silicon active area of same MOS;
E is the minimum range of the L conformal polysilicon in this cover cmos semiconductor technological design rule apart from the monocrystalline silicon active area of same MOS.
Test structure of the present invention, a set of cmos semiconductor explained hereafter comprising optical proximity effect correcting process is accordingly adopted according to setting size, comprise check groups, reference group two groups of cmos devices, the polysilicon of two groups of cmos devices is different to the distance of monocrystalline silicon active area, ensure identical test condition (grid source pressure reduction Vgs, source and drain pressure reduction Vds), the relatively saturation current value of two groups of cmos devices, if both are close, then illustrate that OPC has eliminated the impact of corner rounding effect on device property, if both differences are comparatively large (as shown in Figure 6, the saturation current of two groups differs by more than 5%), then illustrate and also do not eliminate the impact of corner rounding effect on device property, OPC scheme has to be optimized.Whether test structure of the present invention, can eliminate the impact of corner rounding effect on device property according to device electrology characteristic data detection OPC intuitively.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the design rule schematic diagram that cmos semiconductor process portion is general;
Fig. 2 is the cmos device schematic diagram in the test structure for evaluating CMOS polysilicon layer OPC effect;
Fig. 3 is the schematic diagram of the reference group cmos device raceway groove in the test structure for evaluating CMOS polysilicon layer OPC effect by corner rounding effects;
Fig. 4 is the schematic diagram of the check groups cmos device raceway groove in the test structure for evaluating CMOS polysilicon layer OPC effect by corner rounding effects;
Fig. 5 is the cmos device schematic diagram in the test structure for evaluating CMOS monocrystalline silicon active region layer OPC effect;
Fig. 6 is the schematic diagram of the reference group cmos device raceway groove in the test structure for evaluating CMOS monocrystalline silicon active region layer OPC effect by corner rounding effect;
Fig. 7 is the schematic diagram of the check groups cmos device raceway groove in the test structure for evaluating CMOS monocrystalline silicon active region layer OPC effect by corner rounding effect;
Fig. 8 is that the saturation current value of two groups of cmos devices compares schematic diagram.
Embodiment
Every suit cmos semiconductor technique all can have corresponding design rule, and for convenience of expressing, as shown in Figure 1, cmos semiconductor technological design rule is represented by following code name:
Through hole is of a size of a; The minimum spacing of through hole is b; The minimum dimension that monocrystalline silicon active area 101 encases through hole is c; The minimum dimension that polysilicon 102 encases through hole is d; L conformal polysilicon 102 is e apart from the minimum range of the monocrystalline silicon active area of same MOS; Minimum channel width is f; Minimum channel length is g; L shape monocrystalline silicon active area is h apart from the minimum range of the polysilicon 102 of same MOS;
The first embodiment of the present invention, one for evaluating the test structure of CMOS polysilicon layer OPC (optical proximity effect rectification) effect, described test structure comprises 2*N cmos device (NMOS or PMOS), N be more than or equal to 3 integer, a set of cmos semiconductor explained hereafter comprising OPC process is accordingly adopted according to setting size, its size is the respective design rule settings based on this cover cmos semiconductor technique, the cmos semiconductor technique that the concrete numerical value of size overlaps because of difference and being not quite similar;
N number of cmos device in a described 2*N cmos device is as check groups;
N number of cmos device in a described 2*N cmos device is as reference group;
Cmos device in described check groups, its L conformal polysilicon 102 apart from monocrystalline silicon active area 101 spacing (as on Fig. 2 the A that indicates) equal e;
Cmos device in described reference group, its L conformal polysilicon 102 apart from monocrystalline silicon active area 101 spacing (as on Fig. 2 the A that indicates) be more than or equal to 2e, preferably, be more than or equal to 0.5um and be less than or equal to 1um;
The grid of each cmos device, source, leakage, with many finger-like (muti-finger), realize domain by through hole 103 and metal 104 with parallel form, and wherein grid number in parallel is more than or equal to 3, as shown in Figure 2;
The channel width of each cmos device, is more than or equal to f, and is more than or equal to (2c+a), and is less than 1um, and preferably, scope is at 0.2 ~ 0.5um;
The channel length of each cmos device, is more than or equal to g, preferably, equals g.
Check groups, reference group two groups of cmos devices placement location on silicon chip are close as far as possible.
The above-mentioned test structure for evaluating CMOS polysilicon layer OPC effect, can be positioned in test chip and also can be positioned over scribe line area.
The above-mentioned test structure for evaluating CMOS polysilicon layer OPC effect, multiple cmos devices are wherein divided into check groups, reference group two groups by its L conformal polysilicon 102 apart from the spacing of monocrystalline silicon active area 101, the cmos device of reference group as shown in Figure 3, because its L conformal polysilicon 102 is chosen much larger than design rule apart from the spacing of monocrystalline silicon active area 101, ensure that the corner rounding effect of polysilicon can not have influence on device channel region; The cmos device of check groups as shown in Figure 4, its L conformal polysilicon 102 apart from the spacing of monocrystalline silicon active area 101 select be CMOS design rule allow minimum value, the cmos device of check groups, whether the corner rounding of polysilicon can have influence on device channel region, depend on whether OPC scheme used really plays the effect of optical approach effect rectification, if OPC scheme does not reach target, then effective electricity channel width W of the cmos device of check groups
effbe less than designed channel width W
ch, relative to the cmos device of reference group, its saturation current declines, and tests and the cmos device saturation current of comparing check group, reference group two groups, gets final product inspection institute's polysilicon layer OPC scheme for revising corner rounding effect.
The second embodiment of the present invention is one for evaluating the test structure of CMOS monocrystalline silicon active region layer OPC (optical proximity effect rectification) effect; Described test structure comprises 2*N cmos device (NMOS or PMOS), N be more than or equal to 3 integer, a set of cmos semiconductor explained hereafter comprising OPC process is accordingly adopted according to setting size, its size is the respective design rule settings based on this cover cmos semiconductor technique, the cmos semiconductor technique that the concrete numerical value of size overlaps because of difference and being not quite similar;
N number of cmos device in a described 2*N cmos device is as check groups;
N number of cmos device in a described 2*N cmos device is as reference group;
Cmos device in described check groups, the L shape active area monocrystalline silicon 101 of its source and drain apart from the polysilicon 102 on raceway groove spacing (as on Fig. 5 the D that indicates) equal h;
Cmos device in described reference group, the L shape active area monocrystalline silicon 101 of its source and drain apart from the polysilicon 102 on raceway groove spacing (as on Fig. 5 the D that indicates) be more than or equal to 2h, preferably, the spacing range of the polysilicon on the L shape active area monocrystalline silicon distance raceway groove of its source and drain is at 0.2um ~ 1um;
As shown in Figure 5, the grid of each cmos device, source, leakage are with many finger-like (muti-finger), realize domain by through hole 103 and metal 104 with parallel form, wherein grid number in parallel is more than or equal to 3, and source and drain monocrystalline silicon active area 101 adopts L shape to design;
The channel width of each cmos device, is more than or equal to f, preferably, equals f;
The channel length of each cmos device, is more than or equal to g, preferably, equals g;
The projection (as shown in Figure 5 B) of L shape monocrystalline silicon active area 101 is more than or equal to the minimum dimension of this cover cmos semiconductor technological design rule predetermining;
L conformal polysilicon is more than or equal to 2e apart from the distance (as shown in Figure 5 C) of the monocrystalline silicon active area of same MOS;
Check groups, reference group two groups of cmos devices placement location on silicon chip are close as far as possible.
The above-mentioned test structure for electrically evaluating CMOS polysilicon layer optical proximity effect rectification effect, can be positioned in test chip and also can be positioned over scribe line area.
The above-mentioned test structure for evaluating CMOS monocrystalline silicon active region layer OPC effect, multiple cmos devices are wherein divided into check groups, reference group two groups by the L shape active area monocrystalline silicon 101 of source and drain apart from the space D of the polysilicon 102 on raceway groove, two groups of cmos devices, L conformal polysilicon chooses the size much larger than design rule apart from the distance C of the monocrystalline silicon active area of same MOS, to ensure that the corner rounding effect of polysilicon layer can not have influence on device channel region.The cmos device of reference group as shown in Figure 6, because the L shape active area monocrystalline silicon 101 of source and drain is chosen much larger than design rule apart from the space D of the polysilicon 102 on raceway groove, ensure that the corner rounding effect of monocrystalline silicon active region layer can not have influence on device channel region, the cmos device of check groups as shown in Figure 7, the cmos device of check groups, source, what the L shape active area monocrystalline silicon 101 of drain terminal was selected apart from the space D of the polysilicon 102 on raceway groove is the minimum value that CMOS design rule allows, the cmos device of check groups, whether the corner rounding of monocrystalline silicon can have influence on device channel region, depend on whether OPC scheme used really plays the effect of optical approach effect rectification, if OPC does not reach target, then effective electricity channel width of the cmos device of check groups is greater than designed channel width, relative to the cmos device of reference group, its saturation current rises, test is comparing check group also, the cmos device saturation current of reference group two groups, get final product inspection institute's monocrystalline silicon active region layer OPC scheme for revising corner rounding effect.
Test structure of the present invention, a set of cmos semiconductor explained hereafter comprising optical proximity effect correcting process is accordingly adopted according to setting size, comprise check groups, reference group two groups of cmos devices, the polysilicon of two groups of cmos devices is different to the distance of monocrystalline silicon active area, ensure identical test condition (grid source pressure reduction Vgs, source and drain pressure reduction Vds), the relatively saturation current value of two groups of cmos devices, if both are close, then illustrate that OPC has eliminated the impact of corner rounding effect on device property, if both differences are comparatively large (as shown in Figure 6, the saturation current of two groups differs by more than 5%), then illustrate and also do not eliminate the impact of corner rounding effect on device property, OPC scheme has to be optimized.Whether test structure of the present invention, can eliminate the impact of corner rounding effect on device property according to device electrology characteristic data detection OPC intuitively.
Claims (15)
1. one kind for evaluating the test structure of CMOS polysilicon layer OPC effect, described test structure comprises 2*N cmos device, N be more than or equal to 3 integer, adopt a set of cmos semiconductor explained hereafter comprising OPC process accordingly according to setting size, it is characterized in that
N number of cmos device in a described 2*N cmos device is as check groups;
N number of cmos device in a described 2*N cmos device is as reference group;
Cmos device in described check groups, the spacing of its L conformal polysilicon distance monocrystalline silicon active area equals e;
Cmos device in described reference group, the spacing of its L conformal polysilicon distance monocrystalline silicon active area is more than or equal to 2e;
E is the minimum range of the L conformal polysilicon in this cover cmos semiconductor technological design rule apart from the monocrystalline silicon active area of same MOS.
2. the test structure for evaluating CMOS polysilicon layer OPC effect according to claim 1, is characterized in that, the cmos device in described reference group, and the spacing of its L conformal polysilicon distance monocrystalline silicon active area is more than or equal to 0.5um and is less than or equal to 1um.
3. the test structure for evaluating CMOS polysilicon layer OPC effect according to claim 1, is characterized in that, the grid of each cmos device, source, leakage, with many finger-like, realize domain by through hole and metal with parallel form, and wherein grid number in parallel is more than or equal to 3.
4. the test structure for evaluating CMOS polysilicon layer OPC effect according to claim 1, is characterized in that, the channel width scope of each cmos device is at 0.2 ~ 0.5um.
5. the test structure for evaluating CMOS polysilicon layer OPC effect according to claim 1, it is characterized in that, the channel length of each cmos device, is more than or equal to g, and g is the minimum channel length in this cover cmos semiconductor technological design rule.
6. the test structure for evaluating CMOS polysilicon layer OPC effect according to claim 5, it is characterized in that, the channel length of each cmos device equals g.
7. one kind for evaluating the test structure of CMOS monocrystalline silicon active region layer OPC effect, described test structure comprises 2*N cmos device, N be more than or equal to 3 integer, adopt a set of cmos semiconductor explained hereafter comprising OPC process accordingly according to setting size, it is characterized in that
N number of cmos device in a described 2*N cmos device is as check groups;
N number of cmos device in a described 2*N cmos device is as reference group;
Cmos device in described check groups, the spacing of the polysilicon on the L shape active area monocrystalline silicon distance raceway groove of its source and drain equals h;
Cmos device in described reference group, the spacing of the polysilicon on the L shape active area monocrystalline silicon distance raceway groove of its source and drain is more than or equal to 2h;
H is the minimum range of the L shape monocrystalline silicon active area in this cover cmos semiconductor technological design rule apart from the polysilicon of same MOS.
8. the test structure for evaluating CMOS monocrystalline silicon active region layer OPC effect according to claim 7, it is characterized in that, cmos device in described reference group, the spacing range of the polysilicon on the L shape active area monocrystalline silicon distance raceway groove of its source and drain is at 0.2um ~ 1um.
9. the test structure for evaluating CMOS monocrystalline silicon active region layer OPC effect according to claim 7, it is characterized in that, the grid of each cmos device, source, leakage, with many finger-like, realize domain by through hole and metal with parallel form, and wherein grid number in parallel is more than or equal to 3.
10. the test structure for evaluating CMOS monocrystalline silicon active region layer OPC effect according to claim 7, it is characterized in that, the channel width of each cmos device, is more than or equal to f, and f is the minimum channel width in this cover cmos semiconductor technological design rule.
11. test structures for evaluating CMOS monocrystalline silicon active region layer OPC effect according to claim 10, it is characterized in that, the channel width of each cmos device equals f.
12. test structures for evaluating CMOS monocrystalline silicon active region layer OPC effect according to claim 7, it is characterized in that, the channel length of each cmos device, is more than or equal to g, and g is the minimum channel length in this cover cmos semiconductor technological design rule.
13. test structures for evaluating CMOS monocrystalline silicon active region layer OPC effect according to claim 12, it is characterized in that, the channel length of each cmos device equals g.
14. test structures for evaluating CMOS monocrystalline silicon active region layer OPC effect according to claim 7, is characterized in that, the projection of L shape monocrystalline silicon active area is more than or equal to the minimum dimension of this cover cmos semiconductor technological design rule predetermining.
15. test structures for evaluating CMOS monocrystalline silicon active region layer OPC effect according to claim 7, it is characterized in that, L conformal polysilicon is more than or equal to 2e apart from the distance of the monocrystalline silicon active area of same MOS;
E is the minimum range of the L conformal polysilicon in this cover cmos semiconductor technological design rule apart from the monocrystalline silicon active area of same MOS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110335409.5A CN103094251B (en) | 2011-10-28 | 2011-10-28 | For evaluating the test structure of OPC effect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110335409.5A CN103094251B (en) | 2011-10-28 | 2011-10-28 | For evaluating the test structure of OPC effect |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103094251A CN103094251A (en) | 2013-05-08 |
| CN103094251B true CN103094251B (en) | 2015-08-19 |
Family
ID=48206648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110335409.5A Active CN103094251B (en) | 2011-10-28 | 2011-10-28 | For evaluating the test structure of OPC effect |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103094251B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230009090A1 (en) * | 2021-07-12 | 2023-01-12 | Changxin Memory Technologies, Inc. | Semiconductor device layout structure and method of forming semiconductor device |
| CN115621271A (en) * | 2021-07-12 | 2023-01-17 | 长鑫存储技术有限公司 | Semiconductor device layout structure and semiconductor device forming method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW556294B (en) * | 2001-08-27 | 2003-10-01 | Nec Electronics Corp | Semiconductor device |
| KR20090041896A (en) * | 2007-10-25 | 2009-04-29 | 주식회사 하이닉스반도체 | Method for fabricating dual poly gates |
| KR20090066924A (en) * | 2007-12-20 | 2009-06-24 | 주식회사 하이닉스반도체 | Method for optical proximity correction |
| KR20090130895A (en) * | 2008-06-17 | 2009-12-28 | 주식회사 동부하이텍 | Method for forming an auxiliary pattern in a mask for a semiconductor device and a mask for a semiconductor device manufactured by using the method |
| CN101697351A (en) * | 2009-09-25 | 2010-04-21 | 上海宏力半导体制造有限公司 | Structure for testing semiconductor |
| US7908578B2 (en) * | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
| CN102142383A (en) * | 2010-02-03 | 2011-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting positions of wells |
-
2011
- 2011-10-28 CN CN201110335409.5A patent/CN103094251B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW556294B (en) * | 2001-08-27 | 2003-10-01 | Nec Electronics Corp | Semiconductor device |
| US7908578B2 (en) * | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
| KR20090041896A (en) * | 2007-10-25 | 2009-04-29 | 주식회사 하이닉스반도체 | Method for fabricating dual poly gates |
| KR20090066924A (en) * | 2007-12-20 | 2009-06-24 | 주식회사 하이닉스반도체 | Method for optical proximity correction |
| KR20090130895A (en) * | 2008-06-17 | 2009-12-28 | 주식회사 동부하이텍 | Method for forming an auxiliary pattern in a mask for a semiconductor device and a mask for a semiconductor device manufactured by using the method |
| CN101697351A (en) * | 2009-09-25 | 2010-04-21 | 上海宏力半导体制造有限公司 | Structure for testing semiconductor |
| CN102142383A (en) * | 2010-02-03 | 2011-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting positions of wells |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103094251A (en) | 2013-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8458627B2 (en) | Semiconductor device including logic circuit having areas of different optical proximity accuracy | |
| US9551923B2 (en) | Cut mask design layers to provide compact cell height | |
| US20040229135A1 (en) | Multiple exposure method for circuit performance improvement | |
| JP4254871B2 (en) | Optical proximity effect correction method, optical proximity effect correction device, optical proximity effect correction program, semiconductor device manufacturing method, pattern design constraint formulation method, and optical proximity effect correction condition calculation method | |
| JP2010056548A (en) | Method of automatically forming integrated circuit layout | |
| US10339251B2 (en) | Method to improve transistor matching | |
| US20120117519A1 (en) | Method of transistor matching | |
| CN109669319A (en) | Improve the OPC modification method of polysilicon layer line end dimensional homogeneity | |
| CN105093809A (en) | Optical proximity correction method for enhancing lithography process window | |
| CN103094251B (en) | For evaluating the test structure of OPC effect | |
| CN102760651A (en) | Layout logic-operation method for vertical and shallow injection layers and integrated circuit manufacturing method | |
| US8584053B2 (en) | Manufacturability enhancements for gate patterning process using polysilicon sub layer | |
| US8383300B2 (en) | Exposure mask with double patterning technology and method for fabricating semiconductor device using the same | |
| EP2153239A1 (en) | Method for compensation of process-induced performance variation in a mosfet integrated circuit | |
| US8176443B2 (en) | Layout of printable assist features to aid transistor control | |
| CN100592494C (en) | Method for correcting layout design for correcting metallic coating of contact hole | |
| US8751977B2 (en) | Method for generating ultra-short-run-length dummy poly features | |
| TW201430484A (en) | Method of optical proximity correction | |
| US8621399B2 (en) | Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices | |
| KR20090000868A (en) | Method for optical proximity correct | |
| CN102445834A (en) | Optical modeling proximity correction method of SRAM (Static Random Access Memory) grid dimension | |
| US8969870B2 (en) | Pattern for ultra-high voltage semiconductor device manufacturing and process monitoring | |
| CN103091970A (en) | Optical proximity correction method applied to square-hole pattern | |
| KR20110104767A (en) | Method for fabricating semiconductor device | |
| US8765495B1 (en) | Method of forming pattern of doped region |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140109 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140109 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |