CN103137455A - Manufacturing method of chip with low-voltage logic component and high-voltage component - Google Patents
Manufacturing method of chip with low-voltage logic component and high-voltage component Download PDFInfo
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- CN103137455A CN103137455A CN2011103884246A CN201110388424A CN103137455A CN 103137455 A CN103137455 A CN 103137455A CN 2011103884246 A CN2011103884246 A CN 2011103884246A CN 201110388424 A CN201110388424 A CN 201110388424A CN 103137455 A CN103137455 A CN 103137455A
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Abstract
The invention discloses a manufacturing method of a chip with a low-voltage logic component and a high-voltage component. Growth of a thick grid electrode oxidation layer of the high-voltage component happens before shallow trench isolation is formed, a protection-hard masking film layer is formed on the thick grid electrode oxidation layer, and under the condition that the thickness of the thick grid electrode oxidation layer is accurately controlled, risks including performance of electrical characteristics and reliability and the like, caused by the growth of the thick grid electrode oxidation layer, are completely eliminated. Meanwhile, the thick grid electrode oxidation layer of the high-voltage component can be used as an alignment basic reference, a conventional alignment basic reference masking film plate is saved, so that the number of total photo-etching masking film plates is saved by one, and the technology is further optimized.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of manufacture method of high-voltage metal oxide semiconductor device.
Background technology
Along with the development of integrated circuit, the integrated trend that becomes of system-on-a-chip.This just need to have Low-Voltage Logic Devices (as the intelligence control circuit of Micro-processor MCV) and high tension apparatus (simulation or high-tension circuit) simultaneously on chip piece.
But in the chip manufacturing process of reality, the thick grid oxic horizon of high tension apparatus is grown up and can be introduced extra high temperature Long Time Thermal process and wet etching process, cause the variation of relevant particle injection condition, the silicon substrate STRESS VARIATION is brought out lattice defect and is occured and surface silicon consumption, thereby causes that serious Low-Voltage Logic Devices electrical characteristics and reliability performance change.The existing solution that has the manufacturing method of chip of Low-Voltage Logic Devices and high tension apparatus all concentrates on the thick grid oxic horizon of high tension apparatus is grown up and occurs in shallow trench isolation (STI) afterwards, before the Low-Voltage Logic Devices grid oxic horizon is grown up, make up the caused variation of thick grid oxic horizon growth of high tension apparatus by the adjustment of particle injection condition, so just have the dangerous high disadvantage of complex process.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacture method that has the chip of Low-Voltage Logic Devices and high tension apparatus, can eliminate low-voltage device electrical characteristics and reliability performance variation equivalent risk that thick grid oxic horizon is grown up and caused.
For solving the problems of the technologies described above, the manufacture method that has the chip of Low-Voltage Logic Devices and high tension apparatus of the present invention comprises the following steps:
One. a side of silicon substrate is the high tension apparatus zone, and opposite side is the Low-Voltage Logic Devices zone, and then the thick grid oxic horizon of growing up on silicon substrate forms the protection hard mask layer on thick grid oxic horizon;
Two. the protection hard mask layer in Low-Voltage Logic Devices zone and thick grid oxic horizon are removed exposed silicon substrate, keep thick grid oxic horizon and the protection hard mask layer in high tension apparatus zone;
Three. form the protection oxide layer on the thick grid oxic horizon top protection hard mask layer on the silicon substrate in Low-Voltage Logic Devices zone and high tension apparatus zone;
Four. utilize the thick grid oxic horizon in high tension apparatus zone as alignment fiducials, carry out the high tension apparatus trap and inject and thermal process;
Five. form the channel isolation hard mask layer on the protection oxide layer in high tension apparatus zone and Low-Voltage Logic Devices zone;
Six. form shallow trench isolation;
Seven. in shallow trench isolation, place oxide deposition and cmp and channel isolation hard mask layer are peeled off, make and be followed successively by thick grid oxic horizon, protection hard mask layer and protection oxide layer on the silicon substrate in high tension apparatus zone, be the protection oxide layer on the silicon substrate in Low-Voltage Logic Devices zone;
Eight. carry out in the Low-Voltage Logic Devices zone that the low voltage CMOS trap injects and cut-in voltage is regulated and injected;
Nine. with the protection oxide layer removal in Low-Voltage Logic Devices zone, expose silicon substrate, simultaneously the protection oxide layer on the protection hard mask layer in high tension apparatus zone is removed;
Ten. with the hard mask layer removal in high tension apparatus zone, expose the thick grid oxic horizon in high tension apparatus zone;
11. growth low pressure grid oxic horizon on the silicon substrate in Low-Voltage Logic Devices zone.
The manufacturing method of chip that has Low-Voltage Logic Devices and high tension apparatus of the present invention; before the thick grid oxic horizon growth of high tension apparatus occurs in shallow trench isolation (STI) formation; form the protection hard mask layer above thick grid oxic horizon; under the accurate control of guaranteeing thick thickness of grid oxide layer, low-voltage device electrical characteristics and reliability performance variation equivalent risk that thick grid oxic horizon is grown up and caused have been eliminated fully.The thick grid oxic horizon of high tension apparatus can be used as the alignment fiducials (Alignment Key) of subsequent optical carving technology simultaneously, saved the alignment fiducials mask plate (Alignment Key mask) of a routine, make total photo mask board number reduce one, technique is further optimized.
Description of drawings
In order to be illustrated more clearly in the present invention or technical scheme of the prior art, the below will do simple the introduction to the accompanying drawing of required use in the present invention or description of the Prior Art, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 forms protection hard mask layer schematic diagram on thick grid oxic horizon;
Fig. 2 removes the protection hard mask layer in Low-Voltage Logic Devices zone and thick grid oxic horizon to expose the silicon substrate schematic diagram;
Fig. 3 forms protection oxide layer schematic diagram;
Fig. 4 carries out the high tension apparatus trap to inject and the thermal process schematic diagram;
Fig. 5 forms channel isolation hard mask layer schematic diagram on the protection oxide layer;
Fig. 6 forms the shallow trench isolation schematic diagram;
Fig. 7 is that place oxide deposition and cmp and channel isolation hard mask layer are peeled off schematic diagram in shallow trench isolation;
Fig. 8 carries out in the Low-Voltage Logic Devices zone that the low voltage CMOS trap injects and cut-in voltage is regulated and injected schematic diagram;
Fig. 9 removes schematic diagram with the protection oxide layer;
Figure 10 is with the hard mask layer removal in high tension apparatus zone, exposes the thick grid oxic horizon schematic diagram in high tension apparatus zone;
Figure 11 is growth low pressure grid oxic horizon schematic diagram on the silicon substrate in Low-Voltage Logic Devices zone.
Embodiment
Below in conjunction with the accompanying drawing in the present invention, the technical scheme in the present invention is carried out clear, complete description, obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiment.Based on the embodiment in the present invention, all other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work belong to the scope of protection of the invention.
Embodiment one
Have manufacture method one execution mode of chip of Low-Voltage Logic Devices and high tension apparatus as shown in Fig. 1 to 11, comprise the following steps;
One. a side of silicon substrate 1 is the high tension apparatus zone, and opposite side is the Low-Voltage Logic Devices zone, and then the thick grid oxic horizon 11 of growing up on silicon substrate 1 forms protection hard mask layer 12, as shown in Figure 1 on thick grid oxic horizon 11; Better, thick grid oxic horizon 11 is SiO2, protection hard mask layer 12 is SiN;
Two. utilize the method for photoetching, dry plasma corrosion and wet etching, the protection hard mask layer 12 in Low-Voltage Logic Devices zone and thick grid oxic horizon 11 are removed exposed silicon substrate 1, the thick grid oxic horizon 11 and the protection hard mask layer 12 that keep the high tension apparatus zone, as shown in Figure 2;
Three. adopt insitu moisture to generate (in-situ steam generation, ISSG) annealing process, form protection oxide layer 13 on the thick grid oxic horizon 11 tops protection hard mask layers 12 on the silicon substrate in Low-Voltage Logic Devices zone and high tension apparatus zone, as shown in Figure 3; Better, protection oxide layer 13 is SiO2;
Four. utilize the thick grid oxic horizon 11 in high tension apparatus zone as alignment fiducials (Alignment Key), carry out high tension apparatus trap 14 and inject and thermal processs, as shown in Figure 4;
Five. form channel isolation hard mask layer 15 on the protection oxide layer 13 in high tension apparatus zone and Low-Voltage Logic Devices zone, as shown in Figure 5; Better, channel isolation hard mask layer 15 is SiN;
Six. utilize the method for photoetching and dry plasma corrosion to form shallow trench isolation (STI), as shown in Figure 6;
Seven. in shallow trench isolation, place oxide layer 16 depositions and cmp (CMP) and channel isolation hard mask layer 15 are peeled off, make and be followed successively by thick grid oxic horizon 11, protection hard mask layer 12 and protection oxide layer 13 on the silicon substrate in high tension apparatus zone, be protection oxide layer 13 on the silicon substrate in Low-Voltage Logic Devices zone, as shown in Figure 7;
Eight. carry out in the Low-Voltage Logic Devices zone that low voltage CMOS trap 17 injects and relevant cut-in voltage is regulated and injected, as shown in Figure 8;
Nine. use the method for wet etching with protection oxide layer 13 removals in Low-Voltage Logic Devices zone, expose silicon substrate, simultaneously the protection oxide layer 13 on the protection hard mask layer 12 in high tension apparatus zone is removed, as shown in Figure 9;
Ten. utilize the method for wet etching with hard mask layer 12 removals in high tension apparatus zone, expose the thick grid oxic horizon 11 in high tension apparatus zone, as shown in figure 10;
11. utilize the method for the thermal oxidation low pressure grid oxic horizon 18 of growing on the silicon substrate in Low-Voltage Logic Devices zone, as shown in figure 11;
12. carry out subsequent process steps, subsequent process steps is consistent with traditional handicraft.
The manufacturing method of chip that has Low-Voltage Logic Devices and high tension apparatus of the present invention; before the thick grid oxic horizon growth of high tension apparatus occurs in shallow trench isolation (STI) formation; form the protection hard mask layer above thick grid oxic horizon; under the accurate control of guaranteeing thick thickness of grid oxide layer, low-voltage device electrical characteristics and reliability performance variation equivalent risk that thick grid oxic horizon is grown up and caused have been eliminated fully.The thick grid oxic horizon of high tension apparatus can be used as the alignment fiducials (Alignment Key) of subsequent optical carving technology simultaneously, saved the alignment fiducials mask plate (Alignment Key mask) of a routine, make total photo mask board number reduce one, technique is further optimized.
Claims (7)
1. a manufacture method that has the chip of Low-Voltage Logic Devices and high tension apparatus, is characterized in that, comprises the following steps:
One. a side of silicon substrate is the high tension apparatus zone, and opposite side is the Low-Voltage Logic Devices zone, and then the thick grid oxic horizon of growing up on silicon substrate forms the protection hard mask layer on thick grid oxic horizon;
Two. the protection hard mask layer in Low-Voltage Logic Devices zone and thick grid oxic horizon are removed exposed silicon substrate, keep thick grid oxic horizon and the protection hard mask layer in high tension apparatus zone;
Three. form the protection oxide layer on the thick grid oxic horizon top protection hard mask layer on the silicon substrate in Low-Voltage Logic Devices zone and high tension apparatus zone;
Four. utilize the thick grid oxic horizon in high tension apparatus zone as alignment fiducials, carry out the high tension apparatus trap and inject and thermal process;
Five. form the channel isolation hard mask layer on the protection oxide layer in high tension apparatus zone and Low-Voltage Logic Devices zone;
Six. form shallow trench isolation;
Seven. in shallow trench isolation, place oxide deposition and cmp and channel isolation hard mask layer are peeled off, make and be followed successively by thick grid oxic horizon, protection hard mask layer and protection oxide layer on the silicon substrate in high tension apparatus zone, be the protection oxide layer on the silicon substrate in Low-Voltage Logic Devices zone;
Eight. carry out in the Low-Voltage Logic Devices zone that the low voltage CMOS trap injects and cut-in voltage is regulated and injected;
Nine. with the protection oxide layer removal in Low-Voltage Logic Devices zone, expose silicon substrate, simultaneously the protection oxide layer on the protection hard mask layer in high tension apparatus zone is removed;
Ten. with the hard mask layer removal in high tension apparatus zone, expose the thick grid oxic horizon in high tension apparatus zone;
11. growth low pressure grid oxic horizon on the silicon substrate in Low-Voltage Logic Devices zone.
2. the manufacture method that has the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1, is characterized in that,
Described thick grid oxic horizon is SiO2, and described protection hard mask layer is SiN, and described protection oxide layer is SiO2, and described channel isolation hard mask layer is SiN.
3. the manufacture method that has the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1 and 2, is characterized in that,
In step 2, the method for utilizing the corrosion of photoetching, dry plasma and wet etching is removed the protection hard mask layer in Low-Voltage Logic Devices zone and thick grid oxic horizon and is exposed silicon substrate.
4. the manufacture method that has the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1 and 2, is characterized in that,
In step 3, adopt insitu moisture to generate annealing process, form the protection oxide layer on the thick grid oxic horizon top protection hard mask layer on the silicon substrate in Low-Voltage Logic Devices zone and high tension apparatus zone.
5. the manufacture method that has the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1 and 2, is characterized in that,
In step 6, utilize the method for photoetching and dry plasma corrosion to form shallow trench isolation.
6. the manufacture method that has the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1 and 2, is characterized in that,
In step 9, will protect oxide layer to remove with the method for wet etching;
In step 10, use the method for wet etching with the hard mask layer removal in high tension apparatus zone.
7. the manufacture method that has the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1 and 2, is characterized in that,
In step 11, utilize the method for the thermal oxidation low pressure grid oxic horizon of growing on the silicon substrate in Low-Voltage Logic Devices zone.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110634735A (en) * | 2019-09-26 | 2019-12-31 | 上海华力集成电路制造有限公司 | Method for growing dual gate oxide layer and method for manufacturing semiconductor device |
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| US7132330B2 (en) * | 2000-05-26 | 2006-11-07 | Renesas Technology Corp. | Nonvolatile semiconductor memory device with improved gate oxide film arrangement |
| CN101211846A (en) * | 2007-12-21 | 2008-07-02 | 上海宏力半导体制造有限公司 | On-chip system device thick grating oxide layer preparation method |
| CN101320692A (en) * | 2007-06-08 | 2008-12-10 | 联华电子股份有限公司 | Method for producing high pressure metal-oxide-semiconductor element |
| US7808071B2 (en) * | 2008-07-02 | 2010-10-05 | Texas Instruments Incorporated | Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7132330B2 (en) * | 2000-05-26 | 2006-11-07 | Renesas Technology Corp. | Nonvolatile semiconductor memory device with improved gate oxide film arrangement |
| CN101320692A (en) * | 2007-06-08 | 2008-12-10 | 联华电子股份有限公司 | Method for producing high pressure metal-oxide-semiconductor element |
| CN101211846A (en) * | 2007-12-21 | 2008-07-02 | 上海宏力半导体制造有限公司 | On-chip system device thick grating oxide layer preparation method |
| US7808071B2 (en) * | 2008-07-02 | 2010-10-05 | Texas Instruments Incorporated | Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110634735A (en) * | 2019-09-26 | 2019-12-31 | 上海华力集成电路制造有限公司 | Method for growing dual gate oxide layer and method for manufacturing semiconductor device |
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