CN103137455B - Have the manufacturing method of chip of Low-Voltage Logic Devices and high tension apparatus - Google Patents
Have the manufacturing method of chip of Low-Voltage Logic Devices and high tension apparatus Download PDFInfo
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- CN103137455B CN103137455B CN201110388424.6A CN201110388424A CN103137455B CN 103137455 B CN103137455 B CN 103137455B CN 201110388424 A CN201110388424 A CN 201110388424A CN 103137455 B CN103137455 B CN 103137455B
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Abstract
The invention discloses a kind of manufacturing method of chip having Low-Voltage Logic Devices and high tension apparatus; the thick grid oxic horizon of high tension apparatus is grown up and is occurred in before shallow trench isolation formed; protection hard mask layer is formed above thick grid oxic horizon; under the accurate control guaranteeing thick thickness of grid oxide layer, completely eliminate thick grid oxic horizon and to grow up the low-voltage device electrical characteristics that cause and reliability performance change equivalent risk.Simultaneously the thick grid oxic horizon of high tension apparatus can be used as the alignment fiducials of subsequent optical carving technology, and save a conventional alignment fiducials mask plate, make total photo mask board number reduce one piece, technique is optimized further.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of manufacture method of high-voltage metal oxide semiconductor device.
Background technology
Along with the development of integrated circuit, system-on-a-chip is integrated becomes trend.This just needs to have Low-Voltage Logic Devices (intelligent control circuit as Micro-processor MCV) and high tension apparatus (simulation or high-tension circuit) on one chip simultaneously.
But in the chip manufacturing process of reality, the thick grid oxic horizon growth of high tension apparatus can introduce extra high temperature Long Time Thermal process and wet etching process, cause the change of correlated particle injection condition, silicon substrate STRESS VARIATION is brought out lattice defect and is occurred and surface silicon consumption, thus causes serious Low-Voltage Logic Devices electrical characteristics and reliability performance change.After the existing solution having the manufacturing method of chip of Low-Voltage Logic Devices and high tension apparatus all concentrates on and to be grown up by the thick grid oxic horizon of high tension apparatus and occur in shallow trench isolation (STI), before Low-Voltage Logic Devices grid oxic horizon is grown up, made up the change caused by thick grid oxic horizon growth of high tension apparatus by the adjustment of particle injection condition, so just there is the dangerous high disadvantage of complex process.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacture method having the chip of Low-Voltage Logic Devices and high tension apparatus, can eliminate thick grid oxic horizon and to grow up the low-voltage device electrical characteristics that cause and reliability performance change equivalent risk.
For solving the problems of the technologies described above, the manufacture method having the chip of Low-Voltage Logic Devices and high tension apparatus of the present invention, comprises the following steps:
One. the side of silicon substrate is high tension apparatus region, and opposite side is Low-Voltage Logic Devices region, thick grid oxic horizon of growing up on a silicon substrate, then on thick grid oxic horizon, forms protection hard mask layer;
Two. the protection hard mask layer in Low-Voltage Logic Devices region and thick grid oxic horizon are removed and exposes silicon substrate, retain thick grid oxic horizon and the protection hard mask layer in high tension apparatus region;
Three. on the silicon substrate in Low-Voltage Logic Devices region and on the thick grid oxic horizon top protection hard mask layer in high tension apparatus region, form protection oxide layer;
Four. utilize the thick grid oxic horizon in high tension apparatus region as alignment fiducials, carry out the injection of high tension apparatus trap and thermal process;
Five. in the protection oxide layer in high tension apparatus region and Low-Voltage Logic Devices region, form channel isolation hard mask layer;
Six. form shallow trench isolation;
Seven. in shallow trench isolation, place oxide deposition and cmp and channel isolation hard mask layer are peeled off, making the silicon substrate in high tension apparatus region to be followed successively by thick grid oxic horizon, protection hard mask layer and protection oxide layer, the silicon substrate in Low-Voltage Logic Devices region is protection oxide layer;
Eight. the injection of low voltage CMOS trap and cut-in voltage adjustment injection is carried out in Low-Voltage Logic Devices region;
Nine. the protection oxide layer in Low-Voltage Logic Devices region is removed, exposes silicon substrate, the protection oxide layer on the protection hard mask layer in high tension apparatus region is removed simultaneously;
Ten. the hard mask layer in high tension apparatus region is removed, exposes the thick grid oxic horizon in high tension apparatus region;
11. on the silicon substrate in Low-Voltage Logic Devices region, grow low voltage gate oxide layer.
The manufacturing method of chip having Low-Voltage Logic Devices and high tension apparatus of the present invention; the thick grid oxic horizon of high tension apparatus is grown up and is occurred in before shallow trench isolation (STI) formed; protection hard mask layer is formed above thick grid oxic horizon; under the accurate control guaranteeing thick thickness of grid oxide layer, completely eliminate thick grid oxic horizon and to grow up the low-voltage device electrical characteristics that cause and reliability performance change equivalent risk.The thick grid oxic horizon of high tension apparatus can be used as the alignment fiducials (Alignment Key) of subsequent optical carving technology simultaneously, save a conventional alignment fiducials mask plate (Alignment Keymask), make total photo mask board number reduce one piece, technique is optimized further.
Accompanying drawing explanation
In order to be illustrated more clearly in the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in the present invention or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 forms protection hard mask layer schematic diagram on thick grid oxic horizon;
The protection hard mask layer in Low-Voltage Logic Devices region and thick grid oxic horizon are removed to expose silicon substrate schematic diagram by Fig. 2;
Fig. 3 forms protection oxide layer schematic diagram;
Fig. 4 carries out the injection of high tension apparatus trap and thermal process schematic diagram;
Fig. 5 forms channel isolation hard mask layer schematic diagram in protection oxide layer;
Fig. 6 forms shallow trench isolation schematic diagram;
Fig. 7 is that in shallow trench isolation, place oxide deposition and cmp and channel isolation hard mask layer peel off schematic diagram;
Fig. 8 carries out the injection of low voltage CMOS trap and cut-in voltage adjustment injection schematic diagram in Low-Voltage Logic Devices region;
Protection oxide layer is removed schematic diagram by Fig. 9;
The hard mask layer in high tension apparatus region is removed by Figure 10, exposes the thick grid oxic horizon schematic diagram in high tension apparatus region;
Figure 11 grows low voltage gate oxide layer schematic diagram on the silicon substrate in Low-Voltage Logic Devices region.
Embodiment
Below in conjunction with the accompanying drawing in the present invention, carry out clear, complete description to the technical scheme in the present invention, obviously, described embodiment is a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, other embodiments all that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belong to the scope of protection of the invention.
Embodiment one
Manufacture method one execution mode having the chip of Low-Voltage Logic Devices and high tension apparatus, as shown in Fig. 1 to 11, comprises the following steps;
One. the side of silicon substrate 1 is high tension apparatus region, and opposite side is Low-Voltage Logic Devices region, thick grid oxic horizon 11 that silicon substrate 1 is grown up, and then on thick grid oxic horizon 11, forms protection hard mask layer 12, as shown in Figure 1; Preferably, thick grid oxic horizon 11 is SiO2, and protection hard mask layer 12 is SiN;
Two. utilize photoetching, dry plasma corrosion and the method for wet etching, the protection hard mask layer 12 in Low-Voltage Logic Devices region and thick grid oxic horizon 11 are removed and exposes silicon substrate 1, retain thick grid oxic horizon 11 and the protection hard mask layer 12 in high tension apparatus region, as shown in Figure 2;
Three. adopt insitu moisture to generate (in-situ steam generation, ISSG) annealing process, protection oxide layer 13 is formed, as shown in Figure 3 on the silicon substrate in Low-Voltage Logic Devices region and on the thick grid oxic horizon 11 top protection hard mask layer 12 in high tension apparatus region; Preferably, oxide layer 13 is protected to be SiO2;
Four. utilize the thick grid oxic horizon 11 in high tension apparatus region as alignment fiducials (AlignmentKey), carry out high tension apparatus trap 14 and inject and thermal process, as shown in Figure 4;
Five. in the protection oxide layer 13 in high tension apparatus region and Low-Voltage Logic Devices region, form channel isolation hard mask layer 15, as shown in Figure 5; Preferably, channel isolation hard mask layer 15 is SiN;
Six. utilize the method for photoetching and dry plasma corrosion to form shallow trench isolation (STI), as shown in Figure 6;
Seven. in shallow trench isolation, place oxide layer 16 deposits and cmp (CMP) and channel isolation hard mask layer 15 are peeled off, make the silicon substrate in high tension apparatus region to be followed successively by thick grid oxic horizon 11, protection hard mask layer 12 and protection oxide layer 13, the silicon substrate in Low-Voltage Logic Devices region is protection oxide layer 13, as shown in Figure 7;
Eight. carry out low voltage CMOS trap 17 in Low-Voltage Logic Devices region and inject and relevant cut-in voltage adjustment injection, as shown in Figure 8;
Nine. by the method for wet etching, the protection oxide layer 13 in Low-Voltage Logic Devices region is removed, expose silicon substrate, the protection oxide layer 13 on the protection hard mask layer 12 in high tension apparatus region is removed, as shown in Figure 9 simultaneously;
Ten. utilize the method for wet etching to be removed by the hard mask layer 12 in high tension apparatus region, expose the thick grid oxic horizon 11 in high tension apparatus region, as shown in Figure 10; ;
11. utilize the method for thermal oxidation on the silicon substrate in Low-Voltage Logic Devices region, grow low voltage gate oxide layer 18, as shown in figure 11;
12. carry out subsequent process steps, subsequent process steps is consistent with traditional handicraft.
The manufacturing method of chip having Low-Voltage Logic Devices and high tension apparatus of the present invention; the thick grid oxic horizon of high tension apparatus is grown up and is occurred in before shallow trench isolation (STI) formed; protection hard mask layer is formed above thick grid oxic horizon; under the accurate control guaranteeing thick thickness of grid oxide layer, completely eliminate thick grid oxic horizon and to grow up the low-voltage device electrical characteristics that cause and reliability performance change equivalent risk.The thick grid oxic horizon of high tension apparatus can be used as the alignment fiducials (Alignment Key) of subsequent optical carving technology simultaneously, save a conventional alignment fiducials mask plate (Alignment Keymask), make total photo mask board number reduce one piece, technique is optimized further.
Claims (7)
1. have a manufacture method for the chip of Low-Voltage Logic Devices and high tension apparatus, it is characterized in that, comprise the following steps:
One. the side of silicon substrate is high tension apparatus region, and opposite side is Low-Voltage Logic Devices region, thick grid oxic horizon of growing up on a silicon substrate, then on thick grid oxic horizon, forms protection hard mask layer;
Two. the protection hard mask layer in Low-Voltage Logic Devices region and thick grid oxic horizon are removed and exposes silicon substrate, retain thick grid oxic horizon and the protection hard mask layer in high tension apparatus region;
Three. on the silicon substrate in Low-Voltage Logic Devices region and on the thick grid oxic horizon top protection hard mask layer in high tension apparatus region, form protection oxide layer;
Four. utilize the thick grid oxic horizon in high tension apparatus region as alignment fiducials, carry out the injection of high tension apparatus trap and thermal process;
Five. in the protection oxide layer in high tension apparatus region and Low-Voltage Logic Devices region, form channel isolation hard mask layer;
Six. form shallow trench isolation;
Seven. in shallow trench isolation, place oxide deposition and cmp and channel isolation hard mask layer are peeled off, making the silicon substrate in high tension apparatus region to be followed successively by thick grid oxic horizon, protection hard mask layer and protection oxide layer, the silicon substrate in Low-Voltage Logic Devices region is protection oxide layer;
Eight. the injection of low voltage CMOS trap and cut-in voltage adjustment injection is carried out in Low-Voltage Logic Devices region;
Nine. the protection oxide layer in Low-Voltage Logic Devices region is removed, exposes silicon substrate, the protection oxide layer on the protection hard mask layer in high tension apparatus region is removed simultaneously;
Ten. the hard mask layer in high tension apparatus region is removed, exposes the thick grid oxic horizon in high tension apparatus region;
11. on the silicon substrate in Low-Voltage Logic Devices region, grow low voltage gate oxide layer.
2. the manufacture method having the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1, is characterized in that,
Described thick grid oxic horizon is SiO2, and described protection hard mask layer is SiN, and described protection oxide layer is SiO2, and described channel isolation hard mask layer is SiN.
3. the manufacture method having the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1 and 2, is characterized in that,
In step 2, utilize photoetching, dry plasma is corroded and the protection hard mask layer in Low-Voltage Logic Devices region and the removal of thick grid oxic horizon are exposed silicon substrate by the method for wet etching.
4. the manufacture method having the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1 and 2, is characterized in that,
In step 3, adopt insitu moisture to generate annealing process, on the silicon substrate in Low-Voltage Logic Devices region and on the thick grid oxic horizon top protection hard mask layer in high tension apparatus region, form protection oxide layer.
5. the manufacture method having the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1 and 2, is characterized in that,
In step 6, the method for photoetching and dry plasma corrosion is utilized to form shallow trench isolation.
6. the manufacture method having the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1 and 2, is characterized in that,
In step 9, oxide layer will be protected to remove by the method for wet etching;
In step 10, by the method for wet etching, the hard mask layer in high tension apparatus region is removed.
7. the manufacture method having the chip of Low-Voltage Logic Devices and high tension apparatus according to claim 1 and 2, is characterized in that,
In step 11, utilize the method for thermal oxidation on the silicon substrate in Low-Voltage Logic Devices region, grow low voltage gate oxide layer.
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| US7132330B2 (en) * | 2000-05-26 | 2006-11-07 | Renesas Technology Corp. | Nonvolatile semiconductor memory device with improved gate oxide film arrangement |
| CN101211846A (en) * | 2007-12-21 | 2008-07-02 | 上海宏力半导体制造有限公司 | On-chip system device thick grating oxide layer preparation method |
| CN101320692A (en) * | 2007-06-08 | 2008-12-10 | 联华电子股份有限公司 | Method for producing high pressure metal-oxide-semiconductor element |
| US7808071B2 (en) * | 2008-07-02 | 2010-10-05 | Texas Instruments Incorporated | Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7132330B2 (en) * | 2000-05-26 | 2006-11-07 | Renesas Technology Corp. | Nonvolatile semiconductor memory device with improved gate oxide film arrangement |
| CN101320692A (en) * | 2007-06-08 | 2008-12-10 | 联华电子股份有限公司 | Method for producing high pressure metal-oxide-semiconductor element |
| CN101211846A (en) * | 2007-12-21 | 2008-07-02 | 上海宏力半导体制造有限公司 | On-chip system device thick grating oxide layer preparation method |
| US7808071B2 (en) * | 2008-07-02 | 2010-10-05 | Texas Instruments Incorporated | Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof |
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