CN103151263A - Preparation method of thyristor chip - Google Patents
Preparation method of thyristor chip Download PDFInfo
- Publication number
- CN103151263A CN103151263A CN2013100758236A CN201310075823A CN103151263A CN 103151263 A CN103151263 A CN 103151263A CN 2013100758236 A CN2013100758236 A CN 2013100758236A CN 201310075823 A CN201310075823 A CN 201310075823A CN 103151263 A CN103151263 A CN 103151263A
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- CN
- China
- Prior art keywords
- diffusion
- aluminium
- silicon chip
- logical
- aluminum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 71
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 71
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 54
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 54
- 239000010703 silicon Substances 0.000 claims abstract description 54
- 238000009792 diffusion process Methods 0.000 claims abstract description 52
- 238000005498 polishing Methods 0.000 claims abstract description 16
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- 238000001704 evaporation Methods 0.000 claims abstract description 10
- 230000008020 evaporation Effects 0.000 claims abstract description 10
- 238000007796 conventional method Methods 0.000 claims abstract description 6
- 230000007797 corrosion Effects 0.000 claims abstract description 6
- 238000005260 corrosion Methods 0.000 claims abstract description 6
- 239000004411 aluminium Substances 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 18
- 238000003475 lamination Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000005465 channeling Effects 0.000 abstract 3
- 239000012535 impurity Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000012797 qualification Methods 0.000 description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229960000583 acetic acid Drugs 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 239000012362 glacial acetic acid Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- -1 hydrogen potassium oxide Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910001950 potassium oxide Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- Thyristors (AREA)
Abstract
The invention relates to a preparation method of a thyristor chip. Photoetching and corrosion channeling are adopted in an aluminum diffusion method; and a silicon wafer is subjected to double-side evaporation of aluminum, prediffusion, polishing and aluminum rediffusion sequentially in sequence, so that the silicon wafer forms an aluminum isolation area. According to the invention, channeling and polishing are combined, so that the diffusion time is shortened by channeling diffusion; a residual aluminum small island after an aluminum layer is etched is removed by polishing thoroughly; the problem of the aluminum small island of silicon wafer diffusion in the preparation of the thyristor chip by a conventional method is solved; and by using the preparation method of the thyristor chip, the rate of finished products of the thyristor chip can be increased by over 10 percent.
Description
Technical field
The present invention relates to a kind of thyristor chip preparation method, belong to the semiconductor device processing technology field.
Background technology
At present, in preparing the method for chip of square thyristor, generally all comprise using logical diffusion method is formed logical isolated area, the diffuse source that logical part is adopted mainly is divided into pure boron, gallium aluminium or fine aluminium.Fine aluminium is that diffusion time is short, speed is fast for the advantage to logical diffuse source, and the N-type silicon chip two face portion P types more than 400 microns of can realizing are to logical.Silicon chip is completed after logical isolation, then carries out successively passivation in p type impurity diffusion, photoetching, N-type Impurity Diffusion, table top moulding, groove, double-sided metal and chip and cut apart, and makes at last thyristor chip.
The aluminium of prior art comprises the following steps logical diffusion conventional method: (1) Wafer Cleaning; (2) the two-sided evaporation of aluminum of silicon chip; (3) photoengraving aluminium; (4) to logical diffusion, form aluminium to logical isolated area.Conventional simple to logical diffusion method technique, but be that aluminium to silicon chip surface carries out logical diffusion due to this to circulation method, its diffusion time is long, diffusion temperature is high, and particularly owing to anti-carving aluminium, its reticle overwhelming majority is black matrix, area is larger, be difficult to intactly in the process of reprint, then in photoetching process, silicon chip contact with reticle and easily causes the reticle damage, inevitably can produce the aluminium island at silicon chip surface thus.And because silicon dioxide can not shield aluminium, gallium, the aluminium island will spread in wafer bulk in to logical diffusion process, and its degree of depth and suitable to logical position diffusion depth can cause forward and reverse voltage low pressure, and even break-through has a strong impact on the qualification rate of thyristor chip.
Summary of the invention
The present invention mainly solves the aluminium island problem that silicon chip uses conventional method to exist leading to diffusion in the thyristor chip preparation, and a kind of thyristor chip preparation method newly is provided, and improves the thyristor chip qualification rate.
A kind of thyristor chip preparation method of the present invention comprises the following steps:
(1) in silicon chip selected zone of doing logical diffusion, with the etching groove of the method two sides symmetry of photoetching and corrosion, the wide 60-300 micron of its grooving, dark 20-120 micron;
(2) at the two-sided evaporation of aluminum of the silicon chip of grooving, aluminum layer thickness 0.3-3 micron;
(3) silicon chip that aluminium lamination is arranged in grooving is placed on prediffusion in diffusion furnace, temperature 600-1200 ℃, time 1-20 hour;
(4) with the silicon chip twin polishing after prediffusion, single face is removed thickness 5-15 micron;
(5) polished silicon slice is carried out aluminium to logical diffusion again in diffusion furnace, temperature 1200-1250 ℃, time 10-50 hour form aluminium to logical isolated area.
The present invention is in conjunction with grooving and finishing method, make silicon chip form aluminium to logical isolated area, its grooving was shortened logical diffusion time, more thoroughly removed aluminium lamination through polishing and anti-carve residual island, with adopting conventional aluminium, circulation method is compared, the thyristor chip rate of finished products improves more than 10%.
Description of drawings
Fig. 1 is that conventional method aluminium is to logical diffusion schematic flow sheet.
Fig. 2 is that aluminium of the present invention is to logical diffusion schematic flow sheet.
Embodiment
The accompanying drawing marking explanation: after N-type silicon chip sectional view (1-1), the two-sided evaporation of aluminum of silicon chip sectional view (1-3) after sectional view (1-2), silicon chip photoengraving aluminium, silicon chip aluminium to logical diffusion after schematic cross-section (1-4); After N-type silicon chip schematic cross-section (2-1), silicon chip photoetching and etching groove after schematic cross-section (2-2), the two-sided evaporation of aluminum of silicon chip schematic cross-section (2-4) after schematic cross-section (2-3), silicon chip twin polishing, silicon chip aluminium to logical diffusion after schematic cross-section (2-5).And N-type silicon chip (10,20), grooving 21, aluminium lamination (12,22,23), aluminium are to logical isolated area (14,24).
As shown in Fig. 1 (1-2) to (1-4), in conventional thyristor chip preparation method, its silicon chip aluminium to logical diffusing step is: Wafer Cleaning, the two-sided evaporation of aluminum of silicon chip, silicon chip photoengraving aluminium and silicon chip aluminium are to logical diffusion.
As shown in Fig. 2 (1-2) to (1-5), a kind of thyristor chip preparation method of the present invention comprises the following steps:
(1) in silicon chip 20 selected zone of doing logical diffusion isolation, with the etching groove 21 of the method two sides symmetry of photoetching and corrosion, the wide 60-300 micron of its grooving 21, dark 20-120 micron;
(2) at the two-sided evaporation of aluminum of the silicon chip of grooving 21, aluminium lamination (22,23) thickness 0.3-3 micron;
(3) will there be the silicon chip of aluminium lamination 23 to be placed on prediffusion in diffusion furnace in grooving 21, temperature 600-1200 ℃, time 1-20 hour;
(4) with the silicon chip twin polishing after prediffusion, single face is removed thickness 5-15 micron;
(5) polished silicon slice is carried out aluminium to logical diffusion again in diffusion furnace, temperature 1200-1250 ℃, time 10-50 hour form aluminium to logical isolated area.
The present invention passes through successively Wafer Cleaning, photoetching corrosion grooving, evaporation of aluminum, prediffusion, polishing, spreads logical again, thereby make silicon chip complete aluminium, logical diffusion is isolated.Its method combines grooving and polishing dexterously, spreads by grooving and shortens logical diffusion time, thoroughly removes aluminium lamination by polishing and anti-carves residual island, with conventional aluminium, circulation method is compared, and thyristor chip rate of finished products of the present invention improves more than 10%.
In addition, polishing and aluminium are cut apart the silicon chip passivation in rear operation is carried out p type impurity diffusion, photoetching, N-type Impurity Diffusion, table top moulding, groove successively, double-sided metal and the chip that lead to after spreading, made the mesa thyristor chip.
The diffusion of described p type impurity is that the silicon chip after to logical diffusion is placed on and carries out the diffusion of gallium aluminium, temperature 1200-1260 ℃ under the stopped pipe vacuum environment with polishing and aluminium, time 10-30 hour, junction depth 30-120 micron, surface concentration 30-100 Europe nurse ∕ square forms silicon chip base PN junction.
Described N-type Impurity Diffusion is the phosphorus diffusion, diffusion temperature 1000-1200 ℃, and time 1-6 hour, junction depth 10-30 micron, surface concentration 0.08-1.5 Ou Mu ∕ square.
Described table top moulding is to adopt photoetching process to erode away etching tank, and the component volume proportion of corrosive liquid is: fuming nitric aicd: nitric acid: hydrofluoric acid: glacial acetic acid=3:2:4:2, etching time: 5-8 minute; Groove depth 70-150 micron.
In described groove, passivation is glassivation.
Described double-sided metal is to adopt evaporation aluminium, titanium, nickel, silver, alloy under vacuum and temperature 380-500 ℃ condition.
Described chip is cut apart, and is from aluminium, cutting in the middle of logical isolated area to be divided into single thyristor chip.
The present invention removes impurities on surface of silicon chip before the photoetching corrosion grooving can heat 50-100 ℃ with the deionized water solution of 5-20% concentration hydrogen potassium oxide or NaOH, and etching time 5-30 minute, the silicon chip surface glimmer.
The present invention carries out aluminium to logical diffusion in the bottom of grooving, conventional aluminium carries out the aluminium diffusion to logical method of diffusion at silicon chip surface, and with the conventional method ratio, the present invention is to shortening 20-50 hour logical diffusion time.
To in leading to diffusion process, photo-mask process causes at the residual island of silicon face inevitable, makes the deliquescing of chip puncture voltage or break-through at conventional aluminium.And the inventive method is to carry out polishing after aluminium prediffusion, the two-sided 5-15 micron of removing respectively, with the aluminium lamination of silicon chip surface and anti-carve the aluminium island of aluminium under residual all remove clean, thereby make the thyristor chip qualification rate significantly improve.
The present invention adopts the method that grooving and polishing combine on silicon chip, makes silicon chip can comparatively fast form aluminium to logical isolated area, and has thoroughly solved the conventional aluminium of long-term puzzlement to the silicon chip surface residual aluminum island problem of logical diffusion technology.Polishing process is removed silicon wafer thickness 5-15 micron, can make the rooved face width be reduced to the front width of polishing below 1/2nd, does not carry out but can not affect other operation.The present invention also applicable other semiconductor product to logical diffusion technology.
What should be understood that is: above-described embodiment is just to explanation of the present invention, and any innovation and creation that do not exceed in connotation scope of the present invention are within all falling into protection scope of the present invention.
Claims (1)
1.. a thyristor chip preparation method, it is characterized in that: the method comprises the following steps:
(1) conventional method cleaning silicon chip;
(2) in silicon chip selected zone of doing logical diffusion, with the etching groove of the method two sides symmetry of photoetching and corrosion,
The wide 60-300 micron of its grooving, dark 20-120 micron;
(3) at the two-sided evaporation of aluminum of the silicon chip of grooving, aluminum layer thickness 0.3-3 micron;
(4) silicon chip that aluminium lamination is arranged in grooving is placed on prediffusion in diffusion furnace, temperature 600-1200 ℃, time 1-20 hour;
(5) with the silicon chip twin polishing after prediffusion, single face is removed thickness 5-15 micron;
(6) polished silicon slice is carried out aluminium to logical diffusion again in diffusion furnace, temperature 1200-1250 ℃, time 10-50 hour form aluminium to logical isolated area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310075823.6A CN103151263B (en) | 2013-03-11 | 2013-03-11 | A kind of thyristor chip preparation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310075823.6A CN103151263B (en) | 2013-03-11 | 2013-03-11 | A kind of thyristor chip preparation method |
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| Publication Number | Publication Date |
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| CN103151263A true CN103151263A (en) | 2013-06-12 |
| CN103151263B CN103151263B (en) | 2015-08-19 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779156A (en) * | 2014-01-13 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | Method for removing residual aluminum |
| CN105448807A (en) * | 2015-11-20 | 2016-03-30 | 浙江正邦电力电子有限公司 | Opposite-through isolation manufacturing technology for semiconductor device chip |
| CN114005743A (en) * | 2021-10-13 | 2022-02-01 | 华中科技大学 | Square semiconductor pulse power switch and preparation method thereof |
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| US5998813A (en) * | 1996-01-19 | 1999-12-07 | Sgs-Thomson Microelectronics S.A. | Component for protecting telephone line interfaces |
| US6448589B1 (en) * | 2000-05-19 | 2002-09-10 | Teccor Electronics, L.P. | Single side contacts for a semiconductor device |
| CN1913130A (en) * | 2006-08-28 | 2007-02-14 | 汤庆敏 | Manufacturing process of semiconductor device chip punch through isolation area and PN junction |
| CN101901763A (en) * | 2010-06-28 | 2010-12-01 | 启东吉莱电子有限公司 | Production technology of controllable silicon |
| CN101901832A (en) * | 2010-06-28 | 2010-12-01 | 启东吉莱电子有限公司 | Controlled silicon punchthrough structure formed by gallium diffusion and production method thereof |
| CN201804873U (en) * | 2010-06-28 | 2011-04-20 | 启东吉莱电子有限公司 | Silicon-controlled structure capable of shortening punch-through time |
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2013
- 2013-03-11 CN CN201310075823.6A patent/CN103151263B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5998813A (en) * | 1996-01-19 | 1999-12-07 | Sgs-Thomson Microelectronics S.A. | Component for protecting telephone line interfaces |
| US6448589B1 (en) * | 2000-05-19 | 2002-09-10 | Teccor Electronics, L.P. | Single side contacts for a semiconductor device |
| CN1913130A (en) * | 2006-08-28 | 2007-02-14 | 汤庆敏 | Manufacturing process of semiconductor device chip punch through isolation area and PN junction |
| CN101901763A (en) * | 2010-06-28 | 2010-12-01 | 启东吉莱电子有限公司 | Production technology of controllable silicon |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779156A (en) * | 2014-01-13 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | Method for removing residual aluminum |
| CN104779156B (en) * | 2014-01-13 | 2017-10-17 | 中芯国际集成电路制造(上海)有限公司 | The minimizing technology of aluminium residual |
| CN105448807A (en) * | 2015-11-20 | 2016-03-30 | 浙江正邦电力电子有限公司 | Opposite-through isolation manufacturing technology for semiconductor device chip |
| CN105448807B (en) * | 2015-11-20 | 2017-11-10 | 浙江正邦电子股份有限公司 | A kind of semiconductor device chip is to logical isolation manufacturing process |
| CN114005743A (en) * | 2021-10-13 | 2022-02-01 | 华中科技大学 | Square semiconductor pulse power switch and preparation method thereof |
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| Publication number | Publication date |
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| CN103151263B (en) | 2015-08-19 |
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Address after: 321400 Zhejiang County of Jinyun city of Lishui Province East five East Industrial Zone Zhejiang Zhengbang Power Electronics Co Ltd Patentee after: ZHEJIANG ZHENGBANG ELECTRONIC CO.,LTD. Address before: 321400 Zhejiang County of Jinyun city of Lishui Province East five East Industrial Zone Zhejiang Zhengbang Power Electronics Co Ltd Patentee before: ZHEJIANG ZHENGBANG ELECTRIC POWER ELECTRONICS Co.,Ltd. |
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Denomination of invention: A method for preparing thyristor chips Granted publication date: 20150819 Pledgee: Lishui Jinyun Sub branch of Zhejiang Tailong Commercial Bank Co.,Ltd. Pledgor: ZHEJIANG ZHENGBANG ELECTRONIC CO.,LTD. Registration number: Y2024980007381 |