CN103165487B - The method of test pattern sheet silicon grinding rate - Google Patents
The method of test pattern sheet silicon grinding rate Download PDFInfo
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- CN103165487B CN103165487B CN201110412661.1A CN201110412661A CN103165487B CN 103165487 B CN103165487 B CN 103165487B CN 201110412661 A CN201110412661 A CN 201110412661A CN 103165487 B CN103165487 B CN 103165487B
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Abstract
The invention discloses a kind of method of test pattern sheet silicon grinding rate, comprise the following steps: step one, measure and record the initial offset of graphic structure sheet specified quantitative mapping shape diverse location; Step 2, select the pattern piece that several pieces of silicon growth thickness is suitable, with chemical-mechanical polisher, each piece of epitaxial wafer is ground with different time; Step 3, each piece to be measured by silicon graphics structure sheet value after the offset of specified quantitative mapping shaped position that different time grinds and value after recording; Step 4, to value after the offset of each piece of silicon graphics structure sheet and different milling times mapping draw straight line.The slope K of this straight line is the grinding rate in silicon chip any position.The present invention can obtain can the silicon grinding rate of any different graphic sheet of Accurate Determining, fast effectively.Be different from section to detect the destructiveness of silicon chip, high to the reuse ratio of silicon chip.
Description
Technical field
The present invention relates to the method for a kind of semiconductor grinding speed monitoring.
Background technology
At present, semiconductor technology silicon epitaxial wafer thickness method of testing mainly adopts fourier infrared (FTIR) method of testing, the method has obvious difference to demarcate the thickness (substrate generally has high doping content, such as highly doped P type or N-type substrate) of epitaxial loayer according to the doping content of silicon epitaxy layer and substrate layer.But epitaxial growth is (generally higher than 1000 degree) carried out under the high temperature conditions, the dopant of substrate can spread in epitaxial layers in epitaxial process, thus cause the interface of substrate and epitaxial loayer being moved and thickening, the degree that different epitaxial growth conditions interfaces is moved is different, comparatively big error is there is by the result that the method is measured, and can not accurate measurement pattern needed for positioning pattern silicon chip surface, therefore in silicon graphics sheet, FTIR is inapplicable.Due to opaqueness and the surface roughness of silicon, traditional MTE measures also exists certain error inefficacy.The monitoring of pattern piece silicon grinding rate mainly rely on now FA section carry out X-SEM video picture measure EPI extension CMP after value thus calculate silicon grinding rate by thickness difference and the relation of time, complicated and not high to the utilance of silicon chip.
Traditional graph sheet, in the chemical mechanical milling tech (CMP) of silicon, because the epitaxial silicon on the monocrystalline of filling in deep trench and substrate belongs to commaterial, does not have Selection radio to silicon lapping liquid.If directly touch substrate silicon surface in process of lapping, then may affect some electric property of device.Traditional (MTE) ellipse inclined thickness measurement platform goes measure its thickness thus accurately monitor process of lapping.Usually the monocrystalline thickness FTIR of non-graphic sheet measures, the method has obvious difference to demarcate the thickness (substrate generally has high doping content, such as highly doped P type or N-type substrate) of epitaxial loayer according to the doping content of silicon epitaxy layer and substrate layer.But epitaxial growth is (generally higher than 1000 degree) carried out under the high temperature conditions, the dopant of substrate can spread in epitaxial layers in epitaxial process, thus cause the interface of substrate and epitaxial loayer being moved and thickening, the degree that different epitaxial growth conditions interfaces is moved is different, comparatively big error is there is by the result that the method is measured, and can not accurate measurement pattern needed for positioning pattern silicon chip surface, therefore in silicon graphics sheet, FTIR is inapplicable.
For CMP, the grinding rate of non-graphic and pattern piece has larger difference usually.For the rate detection of pattern piece, cannot complete with FTIR, at present usually through being that (FA section) is carried out X-SEM video picture and measured thickness and then carry out calculating pattern piece (patternwafer) rate detection in conjunction with milling time, process complexity and not there is practicality.
Summary of the invention
Technical problem to be solved by this invention is to provide one, and it can solve silicon epitaxy pattern piece grinding rate monitoring problem, controls adjustment CMP easily and effectively.
In order to solve above technical problem, the invention provides a kind of method of test pattern sheet silicon grinding rate, comprising the following steps: step one, measure and record graphic structure sheet specified quantitative mapping shape diverse location initial offset; Step 2, select the pattern piece that several pieces of silicon growth thickness is suitable, with chemical-mechanical polisher, each piece of epitaxial wafer is ground with different time; Step 3, each piece to be measured by silicon graphics structure sheet value after the offset of specified quantitative mapping shaped position that different time grinds and value after recording; Step 4, to value after the offset of each piece of silicon graphics structure sheet and different milling times mapping draw straight line.The slope K of this straight line is the grinding rate in silicon chip any position.
Beneficial effect of the present invention is: the method can obtain can the silicon grinding rate of any different graphic sheet of Accurate Determining, fast effectively.Be different from section to detect the destructiveness of silicon chip, high to the reuse ratio of silicon chip.
In described step one, measurement platform can be MRH scan-probe or AFM atomic force microscope.
The silicon graphics sheet that in described step 2, each piece of thickness is suitable grinds with different time, and it can be any time having certain intervals that the time is chosen.
Carry out the grinding of different time in described step 4 with many pieces of silicon graphics structure sheets respectively, avoid the speed that may produce when grinding separately on one piece and suddenly change thus cause the error of mensuration, with the rate value that this makes, there is linear correlation.
The preparation method of the silicon graphics sheet required for present invention also offers: comprise the following steps:
Step one, surface of silicon hard mask hardmask deposit, and hard mask hardmask used can be oxide-film, nitride film or nitrogen oxidation film;
Step 2, hard mask hardmask etch, oxide-film dry etching, and channel bottom is carved into the end;
Step 3, selective epitaxial monocrystalline deposition, make the height of epitaxy single-crystal be greater than hard mask hardmask surface.
In described step 2, the growing process of the etching of nitride film and oxide-film can be plasma enhanced chemical vapor deposition method PE-CVD, Films Prepared by APCVD method AP-CVD, and low pressure chemical phase sinks method LP-CVD.
In described step 2, the thickness of nitride film and oxide-film is 10 ~ 5000 dusts.
In described step 3, hard mask hardmask etches, oxide-film dry etching, and channel bottom is carved into the end; Characteristic size size can be 5 ~ 50 microns.
In described step 4, extension height can be 10.0-100.0 micron.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is pattern piece growing epitaxial silicon initial offset H0 schematic diagram;
Fig. 2 is worth H1 schematic diagram after pattern piece silicon grinding t1 time offset;
Fig. 3 is worth H2 schematic diagram after pattern piece silicon grinding t2 time offset;
Fig. 4 is worth H3 schematic diagram after pattern piece silicon grinding t3 time offset;
Fig. 5 is pattern piece silicon grinding rate straight line schematic diagram.
Description of reference numerals in figure:
1: silicon substrate, 2: oxide-film (nitride film) barrier layer, 3: silicon epitaxy layer.
Embodiment
The present invention propose a kind of measure many pieces of silicon graphics sheet different times grindings by (MRH) section difference instrument after a certain specified quantitative mapping shape offset value thus mapping test pattern sheet silicon grinding rate (is applicable to detection Different Silicon pattern piece at wafer diverse location, as (center Center in the middle part of Middle edge Edge) speed) method, it can detect the grinding rate of the silicon graphics sheet any time fast and effectively, without cut sections for microscopic examination, ensure that the recycling of silicon chip.The present invention is by the process of selective epitaxial, and preparation has the pattern piece of certain section difference, by detecting different milling time crystal column surface remaining section of difference with section difference instrument, carrys out the grinding rate of test pattern sheet.
The present invention is by the process of selective epitaxial, and preparation has the pattern piece of certain section difference, by detecting different milling time crystal column surface remaining section of difference with section difference instrument, carrys out the grinding rate of test pattern sheet.
Required for the preparation method of silicon graphics sheet:
1, silicon substrate 1 surface hard mask hardmask deposits, and hard mask hardmask used can be oxide-film, nitride film or nitrogen oxidation film 2.The growing process of the etching of nitride film and oxide-film 2 can be plasma enhanced chemical vapor deposition method PE-CVD, Films Prepared by APCVD method AP-CVD, and low pressure chemical phase sinks method LP-CVD etc.Thickness is 10 ~ 5000 dusts.
2, hard mask hardmask etches, and oxide-film dry etching, channel bottom is carved into the end.Characteristic size size can be 5 ~ 50 microns.
3, selectivity monocrystalline silicon extension 3 deposits, and makes the height of silicon epitaxy 3 be greater than hard mask hardmask surface.(here for super junction EPI extension, need to accomplish hard mask hardmaskopen, then carry out selective epitaxial process.) extension height can be 10.0-100.0 micron.
The method of a kind of test pattern sheet silicon grinding rate of the present invention, it comprises:
1) as shown in Figure 1, measure and record graphic structure sheet specified quantitative mapping shape diverse location initial offset;
2) as shown in figs 2-4, select the pattern piece that several pieces of silicon growth thickness is suitable, with chemical-mechanical polisher, each piece of Epi epitaxial wafer is ground with different time;
3) each piece to be measured by silicon graphics structure sheet value after the offset of specified quantitative mapping shaped position (can be the optional position of silicon chip) that different time grinds and value after recording;
4) as shown in Figure 5, straight line is shown to value after the offset of each piece of silicon graphics structure sheet and the mapping of different milling times.The slope K of this straight line is the grinding rate in silicon chip any position.
Described step 1) in measurement platform can be MRH scan-probe or AFM atomic force microscope, because the opaqueness of silicon and rough surface, Epi epitaxial thickness cannot be measured with conventional MTE board (ellipse inclined thickness measurement platform), because silicon has good conformality, offset top can be more smooth, is suitable for MRH scan-probe method.
Described step 2) silicon graphics sheet that each piece of thickness is suitable grinds with different time, and it can be any time having certain intervals that the time is chosen.
Described step 4) in carry out the grinding of different time respectively with many pieces of silicon graphics structure sheets, the speed sudden change that may produce when to avoid on a piece grinding separately thus cause the error of mensuration, with the rate value that this makes, there is linear correlation.
On silicon graphics sheet, the offset (can be the figure of any position of silicon chip) measuring its selected amount mapping shape is removed with MRH scan-probe board, record primary data, then the silicon graphics sheet that several pieces of levels are suitable is selected, with chemical-mechanical polisher, each piece of silicon graphics sheet is ground with different time respectively, be worth after removing the offset of the selected figure measuring each piece of pattern piece with MRH more afterwards, the slope straight line made from this, namely slope K is the grinding rate of silicon graphics sheet in selected graph position.
In example, silicon fiml can be LPC growth also can be EPI epitaxial growth, measuring instrument used can be MRH offset instrument and AFM atomic force microscope, and the method is applicable to the pattern piece of any silicon growth, and cutting into slices without FA to the detection of silicon grinding rate, is not destructive.
The present invention is not limited to execution mode discussed above.Above the description of embodiment is intended to describe and the technical scheme that the present invention relates to being described.Based on the present invention enlightenment apparent conversion or substitute also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, can apply numerous embodiments of the present invention and multiple alternative to reach object of the present invention to make those of ordinary skill in the art.
Claims (8)
1. detect a method for silicon graphics slice lapping speed, it is characterized in that, comprise the following steps:
Step one, measure and record silicon graphics sheet specified quantitative mapping shape diverse location initial offset;
Required for the preparation method of silicon graphics sheet: comprise the following steps:
Step 11, surface of silicon hard mask deposit, and hard mask used is oxide-film, nitride film or nitrogen oxidation film;
Step 12, hard mask etch, and channel bottom is carved into the end;
Step 13, selective silicon epitaxy single-crystal deposit, and make the height of silicon epitaxial single crystal be greater than hard mask surface;
Step 2, select the silicon graphics sheet that several pieces of silicon epitaxial single crystal growth thickness are suitable, with chemical-mechanical polisher, each piece of silicon graphics sheet is ground with different time;
Step 3, each piece to be measured by silicon graphics sheet value after the offset of specified quantitative mapping shaped position that different time grinds and value after recording;
Step 4, draw straight line to value and different milling times after the offset of each piece of silicon graphics sheet, the slope K of this straight line is the grinding rate in silicon chip any position.
2. the method detecting silicon graphics slice lapping speed as claimed in claim 1, it is characterized in that, in described step one, measurement platform is MRH scan-probe or AFM atomic force microscope.
3. the as claimed in claim 1 method detecting silicon graphics slice lapping speed, is characterized in that, the silicon graphics sheet that in described step 2, each piece of thickness is suitable grinds with different time, and it is any time having certain intervals that the time is chosen.
4. the method detecting silicon graphics slice lapping speed as claimed in claim 1, is characterized in that, carry out the grinding of different time in described step 4 with many pieces of silicon graphics sheets respectively.
5. the method detecting silicon graphics slice lapping speed as claimed in claim 1, it is characterized in that, in described step 11, the growing process of nitride film and oxide-film is plasma enhanced chemical vapor deposition method PE-CVD, Films Prepared by APCVD method AP-CVD, and low pressure chemical phase sinks method LP-CVD.
6. the method detecting silicon graphics slice lapping speed as claimed in claim 5, it is characterized in that, in described step 11, the thickness of nitride film and oxide-film is 10 dust ~ 5000 dusts.
7. the method detecting silicon graphics slice lapping speed as claimed in claim 1, it is characterized in that, in described step 12, characteristic size size is 5 microns ~ 50 microns.
8. the method detecting silicon graphics slice lapping speed as claimed in claim 1, is characterized in that, in described step 13, epitaxial deposition process is normal pressure or reduced pressure epitaxy growth, is highly 10.0 microns ~ 100.0 microns.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5658183A (en) * | 1993-08-25 | 1997-08-19 | Micron Technology, Inc. | System for real-time control of semiconductor wafer polishing including optical monitoring |
| CN1340210A (en) * | 1999-10-13 | 2002-03-13 | 皇家菲利浦电子有限公司 | Method and system for polishing semiconductor wafers |
| CN1492213A (en) * | 2002-10-23 | 2004-04-28 | 台湾积体电路制造股份有限公司 | Method for measuring non-metal layer thickness in chemical and mechanical grinding process |
| CN101081488A (en) * | 2006-06-02 | 2007-12-05 | 联华电子股份有限公司 | Online control method of mixed type chemical mechanical buffing technics |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5658183A (en) * | 1993-08-25 | 1997-08-19 | Micron Technology, Inc. | System for real-time control of semiconductor wafer polishing including optical monitoring |
| CN1340210A (en) * | 1999-10-13 | 2002-03-13 | 皇家菲利浦电子有限公司 | Method and system for polishing semiconductor wafers |
| CN1492213A (en) * | 2002-10-23 | 2004-04-28 | 台湾积体电路制造股份有限公司 | Method for measuring non-metal layer thickness in chemical and mechanical grinding process |
| CN101081488A (en) * | 2006-06-02 | 2007-12-05 | 联华电子股份有限公司 | Online control method of mixed type chemical mechanical buffing technics |
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