CN103166633A - Switched capacitor unit - Google Patents

Abstract

The invention discloses a switched capacitor unit. The switched capacitor unit comprises a first switched capacitor circuit, wherein the first switched capacitor circuit comprises a first capacitor unit, a first switch unit which is connected with the first capacitor unit, and a first control unit. When the first switch unit is disconnected, the first control unit enables a first middle node between the first capacitor unit and the first switch unit to be connected on a resonant cavity. When the first switch unit is connected, the first switch unit enables the first middle node to be pulled downward to a ground level. Through the technical scheme, the invention discloses the switched capacitor unit which is further improved.

Description

A kind of switching capacity unit

Technical field

The present invention relates to field of oscillators, relate in particular to a kind of switching capacity unit.

Background technology

take inductance capacitance type voltage controlled oscillator (LC-VCO:inductor and capacitor based voltage-controlled oscillator) as example, it is one of nucleus module of radio frequency transceiver chip, in order to reduce frequency tuning gain Kvco, present LC-VCO is the method for designing that adopts based on numerically controlled switched capacitor array (DCCA:digitally controlled capacitor array), first adopt DCCA to realize the frequency coarse adjustment, then adopt the simulation varactor to realize the frequency fine tuning, this method for designing is under the prerequisite that does not affect frequency tuning range, greatly reduce Kvco.

usually LC-VCO is the difference channel of left and right full symmetric, therefore its switching capacity unit also is designed to the difference form of left and right symmetrical configuration usually, typical switching capacity cellular construction as shown in Figure 1, capacitor C 1 and C2 are identical, metal-oxide-semiconductor Mn2 and Mn4 are also identical, the source ground level of metal-oxide-semiconductor Mn2 and Mn4, it is that (value is logical zero or logical one to SN that grid connects control signal, logical zero equals ground level, logical one equals supply voltage), the Mn2 drain electrode connects an end of capacitor C 1, the other end of capacitor C 1 connects an end of LC resonant cavity, the Mn4 drain electrode connects an end of capacitor C 2, the other end of capacitor C 2 connects the other end of LC resonant cavity, metal-oxide-semiconductor Mn2 wherein, Mn4 is as switch, during switch conduction (SN is logical one), capacitor C 1, C2 is connected to the two ends of resonant cavity by switch, this moment, the total capacitance of resonant cavity increased, therefore frequency of oscillation reduces, when switch disconnects (SN is logical zero), capacitor C 1, C2 and resonant cavity disconnect, and this moment, the total capacitance of resonant cavity reduced, so the frequency of oscillation rising, " leading to " of this switch and " opening ", have just realized the frequency of oscillation digitlization tuning.when SN is logical one, switch conduction, the switch equivalence is a very little resistance (being called internal resistance), this moment, the switching capacity unit of Fig. 1 can equivalence be shown in Fig. 2 a, when SN is logical zero, switch disconnects, impedance is infinitely great, but because switch is to make of metal-oxide-semiconductor, its drain electrode has parasitic capacitance (being designated as Cd) over the ground, therefore, this moment, the switching capacity unit of Fig. 1 can equivalence be shown in Fig. 2 b, capacitor C d is mainly the pn junction capacitance of metal-oxide-semiconductor drain electrode and the overlap capacitance between grid leak, therefore be nonlinear capacitance, be subjected to the impact of metal-oxide-semiconductor drain voltage (being X point voltage and Y point voltage), in the switch conduction attitude, the equivalent capacity of switching capacity unit is approximately C1/2, in switch off state, the equivalent capacity of switching capacity unit is C1Cd/ (C1+Cd)/2.As seen, during switch off state, the equivalent capacity of switching capacity unit is also non-linear, is subjected to the impact of metal-oxide-semiconductor drain voltage (being X point voltage and Y point voltage), if the change in voltage of nodes X and Y, the equivalent capacity of switching capacity unit also and then changes.

Structure shown in Figure 1 can not directly be used in LC-VCO, and reason is when switch disconnects, and nodes X and Y are in floating dummy status, and level is fluid.Although the electric charge of nodes X and Y storage is subject to the impact of MOS switch electric leakage, finally may be released, but this process often reaches several milliseconds, this phenomenon is particularly evident at low temperatures.in the slow leakage process of the electric charge of nodes X and Y, the voltage of nodes X and Y is drift slowly thereupon also, thereby cause the equivalent capacity of switching capacity unit to change slowly, the frequency of oscillation of LC-VCO is and then drift slowly also, due to drift time long (millisecond rank), the normal operation (locking time of PLL is the 100us rank normally) of PLL will obviously be affected, worsen phase noise and spuious (spur) performance of PLL, if LC-VCO is as the open loop frequency modulator in transmitter, the drift of frequency of oscillation will directly cause launching the drift of carrier wave, thereby cause the successful receiving rate of receiver to descend.

In order to prevent the floating sky of nodes X and Y, someone has proposed switching capacity unit as shown in Figure 3, namely adopt the method for large resistance biasing to eliminate floating empty node, in Fig. 3, nodes X and Y are connected to the A point by large resistance R 1 and R2, the A point is that the output of inverter INV1 (is logical zero or logical one, be ground level or supply voltage), be low-impedance node, when SN was logical one, A was logical zero (being ground level), B is logical one, therefore MOS switch Mn2, Mn4 conducting, nodes X and Y pull down to ground level by the MOS switch, therefore do not exist floating empty; When SN was logical zero, A was logical one (being supply voltage), and B is logical zero, so MOS switch Mn2, Mn4 disconnection, and nodes X and Y move the A point voltage to by large resistance R 1, R2, and namely supply voltage, therefore do not exist floating empty yet.This technology has been eliminated floating empty problem, but there are many shortcomings in this technology: one, and the resistance of resistance R 1 and R2 can have influence on the turn-off characteristic of switching capacity unit; Its two, the resistance of resistance R 1 and R2 must be enough greatly, just can make the switching capacity unit well be turn-offed.Compare as seen with structure shown in Figure 1, structure shown in Figure 1 is when switch disconnects, and the equivalent capacity of switching capacity unit is C1Cd/ (C1+Cd)/2, is pure capacitance characteristic, without resistive composition, so lossless; And should equivalence electric capacity and frequency-independent, do not rely on the frequency of oscillation of LC-VCO, therefore frequency linearity is good, be called the shutoff perfect condition, and structure shown in Figure 3 is when switch disconnects, equivalent electric circuit can be reduced to shown in Figure 4, can be easy to derive the admittance of switching capacity unit at this moment be:

$Y\left(\mathrm{j\ω}\right)=\frac{{\mathrm{j\ωC}}_1}{2}\·\frac{1+{\mathrm{j\ωC}}_d{R}_1}{1+\mathrm{j\ω}(C_d+C_1)R_1}---\left(1\right)$

Wherein, ω is frequency of oscillation, and j is imaginary unit, can know from formula (1), and the switching capacity unit is no longer pure capacitance characteristic at this moment, but existing capacitive has again resistive composition, therefore has loss, following formula can be decomposed into real part and imaginary part, for:

$Y\left(\mathrm{j\ω}\right)=\frac{1}{2}\·\frac{{\mathrm{\ω}}^2{C}_1^2{R}_1}{1+{\mathrm{\ω}}^2{(C_d+C_1)}^2{R}_1^2}+\frac{{\mathrm{j\ωC}}_1}{2}\·\frac{1+{\mathrm{\ω}}^2{C}_d(C_d+C_1)R_1^2}{1+{\mathrm{\ω}}^2{(C_d+C_1)}^2{R}_1^2}---\left(2\right)$

This switching capacity unit equivalence is the parallel connection of a capacitor C eq and a resistance R eq, and:

$\begin{array}{c}{C}_{\mathrm{eq}}=\frac{C_1}{2}\·\frac{1+{\mathrm{\ω}}^2{C}_d(C_d+C_1)R_1^2}{1+{\mathrm{\ω}}^2{(C_d+C_1)}^2{R}_1^2}\\ R_{\mathrm{eq}}=2\×\frac{1+{\mathrm{\ω}}^2{(C_d+C_1)}^2{R}_1^2}{{\mathrm{\ω}}^2{C}_1^2{R}_1}\end{array}---\left(3\right)$

as seen, structural equivalents electric capacity shown in Figure 3 and equivalent resistance are all the amount of nonlinearity with frequency dependence, if R1 (equaling R2) is enough little, Ceq is approximately equal to C1/2 (being the equivalent capacity of OFF state), the equivalent capacity of switch conduction attitude is C1/2, the OFF state equivalent capacity is too large, this means that the switching capacity unit does not have the effect that changes electric capacity at this moment, therefore, only have when R1 is enough large, OFF state Ceq is just close to perfect condition shown in Figure 1, be C1Cd/ (C1+Cd)/2, also only have when R1 is enough large, Req is just enough large, loss is less, therefore, for structure shown in Figure 3, R1 and R2 need enough large, just can make the switching capacity unit better in the characteristic of OFF state, R1 and R2 need tens k Ω just can meet design requirement usually, yet, the problem that so large resistance brings is, chip occupying area is large, parasitic capacitance is large, all bring very burden for parameter designing and the layout design of switching capacity unit.

Summary of the invention

The invention provides a kind of more perfect switching capacity unit.

For solving the problems of the technologies described above, the present invention by the following technical solutions:

A kind of switching capacity unit comprises the first switched-capacitor circuit, and described the first switched-capacitor circuit comprises the first capacitor cell, the first switch element that is connected with described the first capacitor cell, and the first control unit; When described the first switch element disconnected, described the first control unit was connected to the first intermediate node between described the first capacitor cell and the first switch element on resonant cavity; During described the first switch element conducting, described the first switch element is pulled down to ground level with described the first intermediate node.

Described the first control unit comprises the first metal-oxide-semiconductor; Described the first capacitor cell comprises the first electric capacity; Described the first switch element comprises the second metal-oxide-semiconductor; Described the first electric capacity is connected with described the second metal-oxide-semiconductor, described the first metal-oxide-semiconductor and described the first Capacitance parallel connection.

Described the first metal-oxide-semiconductor is a NMOS pipe; The second metal-oxide-semiconductor is the 2nd NMOS pipe; The grid of described the 2nd NMOS pipe is connected to a control signal by the first inverter and the second inverter; The source ground of described the 2nd NMOS pipe, drain electrode connects an end of described the first electric capacity, and the other end of described the first electric capacity is connected to resonant cavity; The grid of a described NMOS pipe connects described control signal by described the first inverter, and source electrode connects described the first intermediate node, and drain electrode is connected to described resonant cavity.

This switching capacity unit also comprises the second switch condenser network with described the first switched-capacitor circuit structure full symmetric; Described the first switched-capacitor circuit is connected to the Vop end of resonant cavity, and described second switch condenser network is connected to the Von end of resonant cavity; Perhaps described the first switched-capacitor circuit is connected to the Von end of resonant cavity, and described second switch condenser network is connected to the Vop end of resonant cavity.

A kind of switching capacity unit comprises the first capacitor cell, the first switch element, the first control unit, the second capacitor cell and the second control unit; Described the first capacitor cell all is connected with described the first switch element with described the second capacitor cell; When described the first switch element disconnects, described the first control unit is connected to the first intermediate node between described the first capacitor cell and the first switch element on resonant cavity, and described the second control unit is connected to the second intermediate node between described the second capacitor cell and the first switch element on resonant cavity.

Described the first control unit comprises the first metal-oxide-semiconductor; Described the second control unit comprises the 3rd metal-oxide-semiconductor; Described the first switch element comprises the second metal-oxide-semiconductor; Described the first capacitor cell comprises the first electric capacity; Described the second capacitor cell comprises the second electric capacity; Described the first electric capacity, described the second metal-oxide-semiconductor are connected successively with described the second electric capacity; Described the first metal-oxide-semiconductor and described the first Capacitance parallel connection; Described the 3rd metal-oxide-semiconductor and described the second Capacitance parallel connection.

Described the first metal-oxide-semiconductor is a NMOS pipe, and the second metal-oxide-semiconductor is the 2nd NMOS pipe, and described the 3rd metal-oxide-semiconductor is the 3rd NMOS pipe; The grid of described the 2nd NMOS pipe is connected to a control signal by the first inverter and the second inverter; The drain electrode of described the 2nd NMOS pipe connects an end of described the first electric capacity, and the other end of described the first electric capacity is connected to resonant cavity; The grid of a described NMOS pipe connects described control signal by described the first inverter, and source electrode connects described the first intermediate node, and drain electrode is connected to described resonant cavity; The source electrode of described the 2nd NMOS pipe connects an end of described the second electric capacity, and the other end of described the second electric capacity is connected to resonant cavity; The grid of described the 3rd NMOS pipe connects described control signal by described the first inverter, and drain electrode connects described the second intermediate node, and source electrode is connected to described resonant cavity.

This switching capacity unit also comprises the 3rd control unit and the 4th control unit; During described the first switch element conducting, described the 3rd control unit is pulled down to ground level with described the first intermediate node, and described the 4th control unit is pulled down to ground level with described the second intermediate node.

Described the 3rd control unit comprises the 5th NMOS pipe, and described the 4th control unit comprises the 6th NMOS pipe; Described the 5th NMOS pipe is connected to described control signal with the grid of described the 6th NMOS pipe by described the first inverter and described the second inverter, the source ground of described the 5th NMOS pipe, drain electrode connects described the first intermediate node, the source ground of described the 6th NMOS pipe, drain electrode connects described the second intermediate node.

Described the second electric capacity and described the first electric capacity are identical, and a described NMOS pipe is identical with described the 3rd NMOS pipe, and described the 5th NMOS pipe is identical with described the 6th NMOS pipe.

The invention provides a kind of switching capacity unit, comprise the first switched-capacitor circuit, the first switched-capacitor circuit comprises the first capacitor cell, the first switch element that is connected with this first capacitor cell, and the first control unit; When the first switch element disconnected, this first control unit was connected to the first intermediate node between the first capacitor cell and the first switch element on resonant cavity; During the first switch element conducting, the first switch element is pulled down to ground level with the first intermediate node.The present invention is connected to the first intermediate node between the first capacitor cell and the first switch element on resonant cavity by the first control unit by when the first switch element disconnects, and can eliminate the floating empty problem of the first intermediate node.

Further, the first control unit is metal-oxide-semiconductor, the metal-oxide-semiconductor chip occupying area is less, impact on the parameter designing of switch capacitor cell and layout design is little, and because the switching capacity unit is enough large in the equivalent parallel impedance of OFF state, loss is little, and the first capacitor cell is subjected to the impact of frequency less, therefore the linearity is better, has promoted the turn-off performance of switching capacity unit.

Description of drawings

Fig. 1 is the schematic diagram of a kind of switching capacity unit in prior art;

Fig. 2 a is the equivalent electric circuit of switching capacity cell conduction state shown in Figure 1;

Fig. 2 b is the equivalent electric circuit of switching capacity shown in Figure 1 unit off-state;

Fig. 3 is a kind of switching capacity cell schematics of another embodiment in prior art;

Fig. 4 is the equivalent electric circuit of switching capacity shown in Figure 3 unit off-state;

Fig. 5 is a kind of switching capacity cell schematics of the embodiment of the present invention;

Fig. 6 is a kind of switching capacity cell schematics of another embodiment of the present invention;

Fig. 7 is the equivalent electric circuit of switching capacity shown in Figure 6 unit off-state;

Fig. 8 is a kind of switching capacity cell schematics of another embodiment of the present invention.

Embodiment

By reference to the accompanying drawings the present invention is described in further detail below by embodiment.

Fig. 5 is the schematic diagram of a kind of switching capacity of embodiment of the present invention unit, please investigate Fig. 5:

The switching capacity unit comprises the first switched-capacitor circuit, the first switched-capacitor circuit comprises the first capacitor cell, the first switch element and the first control unit, first control unit of the present embodiment is a NMOS pipe Mn1, the first capacitor cell is the first capacitor C 1, the first switch element is the 2nd NMOS pipe Mn2, the grid of the one NMOS pipe Mn1 is connected to a control signal SN by the first inverter INV1, and (value is logical zero or logical one, logical zero equals ground level, and logical one equals supply voltage); The grid of the 2nd NMOS pipe Mn2 is connected to this control signal SN by the first inverter INV1 and the second inverter INV2; The source ground of the 2nd NMOS pipe Mn2, drain electrode connects an end of the first capacitor C 1; Another termination resonant cavity of the first capacitor C 1; The source electrode of the one NMOS pipe Mn1 meets the first intermediate node X between the 2nd NMOS pipe Mn2 drain electrode and the first capacitor C 1, the drain electrode of the one NMOS pipe Mn1 connects resonant cavity, the drain electrode of the present embodiment the one NMOS pipe Mn1 and the other end of described the first capacitor C 1 all connect the Vop end of resonant cavity, when SN is logical one, A is that logical zero and B are logical one, and this moment, Mn1 disconnected, the Mn2 conducting, the switching capacity unit is in conducting state, and switch Mn1 does not affect the work of switching capacity unit; When SN is logical zero, A is that logical one and B are logical zero, Mn1 conducting this moment, and Mn2 disconnects, the switching capacity unit is in off-state, the first intermediate node X is connected with the Vop end of resonant cavity by switch Mn1, it is an end of resonant cavity due to Vop, its average DC level and waveform are all highly stable, there is not floating empty problem with drifting about, so the same floating sky and the drifting problem of not existing of the first intermediate node X, simultaneously, switch Mn1 adds, and is very little to the switching capacity cell influence that is in off-state.

The switched-capacitor circuit of the present embodiment can be applicable in single-ended oscillator, in single-ended LC-VCO, for symmetrical difference channel LC-VCO, its switching capacity unit also can be designed to the difference form of left and right symmetrical configuration, Fig. 6 is a kind of switching capacity cell schematics of another embodiment of the present invention, please refer to Fig. 6:

compare Fig. 5, Fig. 6 also comprises the second switch condenser network with the first switched-capacitor circuit structure full symmetric, and the second switch condenser network comprises the second capacitor C 2, the 3rd NMOS pipe Mn3 and the 4th NMOS pipe Mn4, the grid of the 3rd NMOS pipe Mn3 is connected to control signal SN by the first inverter INV1, the grid of the 4th NMOS pipe Mn4 is connected to this control signal SN by the first inverter INV1 and the second inverter INV2, the source electrode of the source electrode of the 4th NMOS pipe Mn4 and the 2nd NMOS pipe Mn2 is connected to ground level in the lump, the drain electrode of the 4th NMOS pipe Mn4 connects an end of the second capacitor C 2, the Von end of another termination resonant cavity of the second capacitor C 2, the source electrode of the 3rd NMOS pipe Mn3 meets the drain electrode of the 4th NMOS pipe Mn4 and the second intermediate node Y between the second capacitor C 2, the drain electrode Mn3 of the 3rd NMOS pipe connects the Von end of resonant cavity, when SN is logical one, A is that logical zero and B are logical one, this moment Mn1, Mn3 disconnects, and Mn2, the Mn4 conducting, the first switched-capacitor circuit, the equal conducting of second switch condenser network, the switching capacity unit is in conducting state, and Mn1, Mn3 does not affect the work of switching capacity unit, when SN is logical zero, A is that logical one and B are logical zero, this moment Mn1, the Mn3 conducting, and Mn2, Mn4 disconnects, the first switched-capacitor circuit, the second switch condenser network all is in off-state, the first intermediate node X is connected with the Vop end of resonant cavity by switch Mn1, the second intermediate node Y is connected with the Von end of resonant cavity by switch Mn3, holding due to Vop end and Von is the two ends of LC-VCO resonant cavity, its average DC level and waveform are all highly stable, there is not floating empty problem with drifting about, , the first intermediate node X do not exist floating sky and drifting problem the same as Y in the middle of second.Simultaneously, Mn1 and Mn3 add, very little to the switching capacity cell influence that is in off-state, close to shutoff perfect condition shown in Figure 1, the equivalent electric circuit of structure shown in Figure 6 when OFF state, as shown in Figure 7, the admittance of the first switched-capacitor circuit is (admittance of second switch condenser network also can draw with reference to following manner) at this moment:

$Y\left(\mathrm{j\ω}\right)=\frac{{\mathrm{j\ωC}}_d}{2}\·\frac{1+{\mathrm{j\ωC}}_1{R}_{\mathrm{on}}}{1+\mathrm{j\ω}(C_1+C_d)R_{\mathrm{on}}}---\left(4\right)$

Formula (4) is decomposed into real part and imaginary part, and the real part equivalence is a resistance R eq, and the imaginary part equivalence is a capacitor C eq, and Req is in parallel with Ceq, process, and derivation can obtain:

$\begin{array}{c}{C}_{\mathrm{eq}}=\frac{C_d}{2}\·\frac{1+{\mathrm{\ω}}^2{C}_1(C_1+C_d)R_{\mathrm{on}}^2}{1+{\mathrm{\ω}}^2{(C_1+C_d)}^2{R}_{\mathrm{on}}^2}\\ R_{\mathrm{eq}}=2\×\frac{1+{\mathrm{\ω}}^2{(C_1+C_d)}^2{R}_{\mathrm{on}}^2}{{\mathrm{\ω}}^2{C}_d^2{R}_{\mathrm{on}}}\end{array}---\left(5\right)$

More reasonably estimate by one, suppose Cd=0.2C1, and Ron=0.1/ (ω C1), substitution formula (5) can obtain by abbreviation:

$\left\{\begin{array}{c}{C}_{\mathrm{eq}}=\frac{C_d}{2}\·\frac{1+{\mathrm{\ω}}^2{C}_1\·{1.2C}_1\·{\left(\frac{0.1}{{\mathrm{\ωC}}_1}\right)}^2}{1+{\mathrm{\ω}}^2{\left({1.2C}_1\right)}^2\·{\left(\frac{0.1}{{\mathrm{\ωC}}_1}\right)}^2}=\frac{C_d}{2}\·0.9976\≈\frac{C_d}{2}=0.1C_1\\ R_{\mathrm{eq}}=2\×\frac{1+{\mathrm{\ω}}^2{\left(1.2C_1\right)}^2\·{\left(\frac{0.1}{{\mathrm{\ωC}}_1}\right)}^2}{{\mathrm{\ω}}^2{\left({0.2C}_1\right)}^2\frac{0.1}{{\mathrm{\ωC}}_1}}\≈\frac{500}{{\mathrm{\ωC}}_1}\end{array}\right.---\left(6\right)$

1/ (ω C1) is exactly the impedance of capacitor C 1, usually in k Ω rank, therefore Req is up to 500k Ω, be connected in parallel on resonant cavity, can ignore the impact of resonant cavity, therefore, in the first switched-capacitor circuit off-state, its resistive composition can be ignored, and switched-capacitor circuit is similar to pure electric capacity, is subjected to the impact of frequency very little, its OFF state performance is close to shutoff perfect condition shown in Figure 1.

Formula (3) is done one more reasonably estimate, suppose Cd=0.2C1, and R1=5/ (ω C1), substitution formula (3) can obtain by abbreviation:

$\left\{\begin{array}{c}{C}_{\mathrm{eq},\mathrm{old}}=\frac{C_1}{2}\·\frac{1+{\mathrm{\ω}}^2\×{0.2C}_1\×{1.2C}_1\×{\left(\frac{5}{{\mathrm{\ωC}}_1}\right)}^2}{1+{\mathrm{\ω}}^2{\left({1.2C}_1\right)}^2{\left(\frac{5}{\mathrm{\ω}{C}_1}\right)}^2}=\frac{C_1}{2}\·0.19\≈{0.1C}_1\\ R_{\mathrm{eq},\mathrm{old}}=2\×\frac{1+{\mathrm{\ω}}^2{(C_d+C_1)}^2{R}_1^2}{{\mathrm{\ω}}^2{C}_1^2{R}_1}=2\×\frac{1+{\mathrm{\ω}}^2{\left({1.2C}_1\right)}^2{\left(\frac{5}{{\mathrm{\ωC}}_1}\right)}^2}{{\mathrm{\ω}}^2{C}_1^2\×\frac{5}{\mathrm{\ωC}}}\≈\frac{15}{{\mathrm{\ωC}}_1}\end{array}\right.---\left(7\right)$

Comparing result (6) and result (7) can be seen, in the situation that the OFF state electric capacity of two kinds of structures approximate the same (being about 0.1C1), the scheme that the equivalent resistance in parallel of Fig. 3 proposes much smaller than Fig. 6, therefore the structure that the loss that brings proposes much larger than Fig. 6, suppose that 1/ (ω C1) is in k Ω rank, the Req of result (7) is in 15k Ω rank, this impedance is obviously large not, the loss that not only brings is apparent in view, and make the hold impact of frequency of equivalent electric in parallel very large, must increase the resistance of R1.If R1 is increased to R1=20/ (ω C1), repeat the computational process of front, can obtain:

$\left\{\begin{array}{c}{C}_{\mathrm{eq},\mathrm{old}}\≈{0.09C}_1\\ R_{\mathrm{eq},\mathrm{old}}\≈\frac{86}{{\mathrm{\ωC}}_1}\end{array}\right.---\left(8\right)$

Equivalent capacity Ceq in parallel is approximate constant, and equivalent resistance in parallel is increased to 90k Ω rank, and this moment, equivalent resistance in parallel was enough large, but in Fig. 6 other equivalent resistance in parallel of 500k Ω level.Because resistance R 1 has increased to 20k Ω rank, and two resistance (R1 and R2) are arranged, not only take than the large chip area, and be unfavorable for layout design.Therefore, with respect to structure shown in Figure 3, the switching capacity unit that Fig. 6 proposes, not only solved the problem of floating sky, but also promoted the turn-off performance of switching capacity unit, and saved two large resistance, make parameter designing and the layout design of switching capacity unit all become easy.Preferably, the second capacitor C 2 and the first capacitor C 1 are identical, and the 2nd NMOS pipe Mn2 and the 4th NMOS pipe Mn4 are identical, and a NMOS pipe Mn1 and the 3rd NMOS pipe Mn3 are identical.

The present invention also comprises another kind of switching capacity unit, and this switching capacity unit comprises the first capacitor cell, the first switch element, the first control unit, the second capacitor cell and the second control unit; The first capacitor cell all is connected with the first switch element with the second capacitor cell; When the first switch element disconnects, the first control unit is connected to the first intermediate node between the first capacitor cell and the first switch element on resonant cavity, and the second control unit is connected to the second intermediate node between the second capacitor cell and the first switch element on resonant cavity.

Fig. 8 is a kind of switching capacity cell schematics of another embodiment of the present invention, please investigate Fig. 8:

first control unit of the present embodiment is a NMOS pipe Mn1, the first capacitor cell is the first capacitor C 1, the first switch element is the 2nd NMOS pipe Mn2, the second capacitor cell is the second capacitor C 2, the second control unit is the 3rd NMOS pipe Mn3, the first capacitor C 1, the 2nd NMOS pipe Mn2 connects successively with the second capacitor C 2, a described NMOS pipe Mn1 is in parallel with the first capacitor C 1, the 3rd NMOS pipe is in parallel with described the second capacitor C 2, the grid of the one NMOS pipe Mn1 is connected to a control signal SN by the first inverter INV1, and (value is logical zero or logical one, logical zero equals ground level, logical one equals supply voltage), the grid of the 2nd NMOS pipe Mn2 is connected to this control signal SN by the first inverter INV1 and the second inverter INV2, the drain electrode of the 2nd NMOS pipe Mn2 connects an end of the first capacitor C 1, the Vop end of another termination resonant cavity of the first capacitor C 1, the source electrode of the one NMOS pipe Mn1 meets the first intermediate node X between the 2nd NMOS pipe Mn2 drain electrode and the first capacitor C 1, the drain electrode of the one NMOS pipe Mn1 connects the Vop end of resonant cavity, the source electrode of the 2nd NMOS pipe Mn2 connects an end of the second capacitor C 2, the Von end of another termination resonant cavity of the second capacitor C 2, the grid of the 3rd NMOS pipe Mn3 is connected to control signal SN by the first inverter INV1, the drain electrode of the 3rd NMOS pipe Mn3 meets the source electrode of the 2nd NMOS pipe Mn2 and the second intermediate node Y between the second capacitor C 2, and the source electrode of the 3rd NMOS pipe Mn3 connects the Von end of resonant cavity.the switching capacity unit of the present embodiment also comprises the 3rd control unit and the 4th control unit, during the first switch element conducting, the 3rd control unit is pulled down to ground level with the first intermediate node, the 4th control unit is pulled down to ground level with the second intermediate node, in the present embodiment, the 3rd control unit is the 5th NMOS pipe Mn5, and the 4th control unit is the 6th NMOS pipe Mn6, the grid of the 5th NMOS pipe Mn5 and the 6th NMOS pipe Mn6 is connected to control signal SN by the first inverter INV1 and the second inverter INV2, the source ground of the 5th NMOS pipe Mn5, drain electrode meets the first intermediate node X, the source ground of the 6th NMOS pipe Mn6, drain electrode meets the second intermediate node Y, when SN is logical one, A is that logical zero and B are logical one, switch Mn2 conducting, the switching capacity unit is in conducting state, Mn5, the Mn6 conducting, move the first intermediate node X and the second intermediate node Y to ground level, therefore there are not floating empty problem in the first intermediate node X and the second intermediate node Y, switch Mn1, Mn3 disconnects, so Mn1, Mn3 does not affect the work of switching capacity unit, when SN is logical zero, A is that logical one and B are logical zero, Mn2 disconnects, the switching capacity unit is in off-state, Mn5, Mn6 disconnect, so Mn5, Mn6 do not affect the switching capacity cell operation, switch Mn1, Mn3 conducting, the first intermediate node X and the second intermediate node Y are pulled to respectively Vop and Von, therefore also eliminated floating empty problem.

This embodiment, in the switching capacity cell conduction, Mn5 and Mn6 work, and respectively the first intermediate node X and the second intermediate node Y are pulled to ground level; In switching capacity unit disconnection, Mn1 and Mn3 work, and respectively the first intermediate node X and the second intermediate node Y are pulled to Vop and Von.MOS switch in the middle of two electric capacity of this structure share, under the identical prerequisite of switch size (conducting resistance is also identical), the resistive loss of this configuration switches capacitor cell under conducting state only has half of structure shown in Figure 6.

Above embodiment is all take the NMOS pipe as example, but each NMOS pipe all can adopt the PMOS pipe to substitute, and the annexation of change and other unit correspondingly all should be considered as belonging to protection scope of the present invention with the scheme of the above NMOS pipe of PMOS alternative the present invention of pipe.

The switching capacity unit that the present invention proposes, can be applicable to the oscillator take LC as resonant cavity arbitrarily, comprise LC-VCO, orthogonal type LC-VCO (Quadrature LC-VCO), Cole's pieze (Colpitts) oscillator etc., can be applicable in multiple radio circuit, as low noise amplifier (LNA:low-noise amplifier), frequency mixer (Mixer), driving amplifier (DA:drive amplifier) etc.

Above content is in conjunction with concrete execution mode further description made for the present invention, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.

Claims (10)

1. a switching capacity unit, is characterized in that, comprise the first switched-capacitor circuit, described the first switched-capacitor circuit comprises the first capacitor cell, the first switch element that is connected with described the first capacitor cell, and the first control unit; When described the first switch element disconnected, described the first control unit was connected to the first intermediate node between described the first capacitor cell and the first switch element on resonant cavity; During described the first switch element conducting, described the first switch element is pulled down to ground level with described the first intermediate node.

2. switching capacity as claimed in claim 1 unit, is characterized in that, described the first control unit comprises the first metal-oxide-semiconductor; Described the first capacitor cell comprises the first electric capacity; Described the first switch element comprises the second metal-oxide-semiconductor; Described the first electric capacity is connected with described the second metal-oxide-semiconductor, described the first metal-oxide-semiconductor and described the first Capacitance parallel connection.

3. switching capacity as claimed in claim 2 unit, is characterized in that, described the first metal-oxide-semiconductor is a NMOS pipe; The second metal-oxide-semiconductor is the 2nd NMOS pipe; The grid of described the 2nd NMOS pipe is connected to a control signal by the first inverter and the second inverter; The source ground of described the 2nd NMOS pipe, drain electrode connects an end of described the first electric capacity, and the other end of described the first electric capacity is connected to resonant cavity; The grid of a described NMOS pipe connects described control signal by described the first inverter, and source electrode connects described the first intermediate node, and drain electrode is connected to described resonant cavity.

4. as described in claims 1 to 3 any one switching capacity unit, is characterized in that, also comprises the second switch condenser network with described the first switched-capacitor circuit structure full symmetric; Described the first switched-capacitor circuit is connected to the Vop end of resonant cavity, and described second switch condenser network is connected to the Von end of resonant cavity; Perhaps described the first switched-capacitor circuit is connected to the Von end of resonant cavity, and described second switch condenser network is connected to the Vop end of resonant cavity.

5. a switching capacity unit, is characterized in that, comprises the first capacitor cell, the first switch element, the first control unit, the second capacitor cell and the second control unit; Described the first capacitor cell all is connected with described the first switch element with described the second capacitor cell; When described the first switch element disconnects, described the first control unit is connected to the first intermediate node between described the first capacitor cell and the first switch element on resonant cavity, and described the second control unit is connected to the second intermediate node between described the second capacitor cell and the first switch element on resonant cavity.

6. switching capacity as claimed in claim 5 unit, is characterized in that, described the first control unit comprises the first metal-oxide-semiconductor; Described the second control unit comprises the 3rd metal-oxide-semiconductor; Described the first switch element comprises the second metal-oxide-semiconductor; Described the first capacitor cell comprises the first electric capacity; Described the second capacitor cell comprises the second electric capacity; Described the first electric capacity, described the second metal-oxide-semiconductor are connected successively with described the second electric capacity; Described the first metal-oxide-semiconductor and described the first Capacitance parallel connection; Described the 3rd metal-oxide-semiconductor and described the second Capacitance parallel connection.

7. switching capacity as claimed in claim 6 unit, is characterized in that, described the first metal-oxide-semiconductor is a NMOS pipe, and the second metal-oxide-semiconductor is the 2nd NMOS pipe, and described the 3rd metal-oxide-semiconductor is the 3rd NMOS pipe; The grid of described the 2nd NMOS pipe is connected to a control signal by the first inverter and the second inverter; The drain electrode of described the 2nd NMOS pipe connects an end of described the first electric capacity, and the other end of described the first electric capacity is connected to resonant cavity; The grid of a described NMOS pipe connects described control signal by described the first inverter, and source electrode connects described the first intermediate node, and drain electrode is connected to described resonant cavity; The source electrode of described the 2nd NMOS pipe connects an end of described the second electric capacity, and the other end of described the second electric capacity is connected to resonant cavity; The grid of described the 3rd NMOS pipe connects described control signal by described the first inverter, and drain electrode connects described the second intermediate node, and source electrode is connected to described resonant cavity.

8. as described in claim 5 to 7 any one switching capacity unit, is characterized in that, also comprises the 3rd control unit and the 4th control unit; During described the first switch element conducting, described the 3rd control unit is pulled down to ground level with described the first intermediate node, and described the 4th control unit is pulled down to ground level with described the second intermediate node.

9. switching capacity as claimed in claim 8 unit, is characterized in that, described the 3rd control unit comprises the 5th NMOS pipe, and described the 4th control unit comprises the 6th NMOS pipe; Described the 5th NMOS pipe is connected to described control signal with the grid of described the 6th NMOS pipe by described the first inverter and described the second inverter, the source ground of described the 5th NMOS pipe, drain electrode connects described the first intermediate node, the source ground of described the 6th NMOS pipe, drain electrode connects described the second intermediate node.

10. switching capacity as claimed in claim 9 unit, is characterized in that, described the second electric capacity and described the first electric capacity are identical, and a described NMOS pipe is identical with described the 3rd NMOS pipe, and described the 5th NMOS pipe is identical with described the 6th NMOS pipe.

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