CN103187101A

CN103187101A - Compressed data output method for DRAM repair test

Info

Publication number: CN103187101A
Application number: CN2013100888140A
Authority: CN
Inventors: 亚历山大; 王春娟
Original assignee: Xian Sinochip Semiconductors Co Ltd
Current assignee: Xian Sinochip Semiconductors Co Ltd
Priority date: 2013-03-19
Filing date: 2013-03-19
Publication date: 2013-07-03

Abstract

The invention relates to a compressed data output method for DRAM (dynamic random access memory) repair test. The method comprises the following steps: step 1, reading the value of a 32-bit cell; step 2, judging whether fail exists in the cell through an internal algorithm of a chip; step 3, carrying out calculation of 'and' to the result value of the 32-bit cell inside the chip; step 4, outputting the unique final result value of the 32-bit cell; step 5, after obtaining the result of the 32-bit cell through a testing machine, if the result is '0', a broken bit line CSL exists, then running a processing program to replace the broken bit line CSL with the redundant bit line CSL, and if the result is '1', a broken bit line CSL does not exist. The provided compressed data output method for DRAM repair test shortens the testing time and reduces the testing cost.

Description

A kind of data compression output intent for the DRAM recovery test

Technical field

The invention belongs to the chip design field, relate to a kind of data compression output intent for the DRAM recovery test.

Background technology

The elementary cell of DRAM is made up of thousands of cell unit (each unit is referred to as bit), and can guarantee that without any a kind of technology all cell unit all are correct at present, therefore in a single day find that there is problem certain unit in head end test, we utilize redundant unit that the unit that breaks down is repaired;

Referring to Fig. 1, when internally depositing into capable read-write operation, word line WL and bit line CSL can be activated, and it then is activated to deserved cell unit; The intersection point correspondence of each root bit line CSL and word line WL be 8 cell unit; Chip with DDR2X16 is example, and each read-write is 64 bit, then needs to activate 1 WL and 8 CSL, totally 8 intersection points, and corresponding is 64 cell unit;

Referring to Fig. 2, the test result information of each cell all needs to go on record; For the Advantest T5377 that memory test is used always, each clock period can only be read 1 bit; Therefore note this 64bit information, need channel and 2 clock period of 16 boards;

In this way, each chip need connect 16 IO passages, and 4 cycles can be satisfied the demand that we read 64 bit; The IO passage that board can provide is limited, is example with Advantest T5377, and it has 1280 IO passages, if each chip need connect 16 IO passages, then can only test 80 chips simultaneously at most; And this is with surveying the demand that number far can not satisfy our volume production, and the complexity cost according to technology also increases thereupon simultaneously, and the time of reading is also longer relatively.

Summary of the invention

For the correct output that guarantees to repair the used data of chip and save cost, need have enough IO channel (I/O) and the time chien shih its data all correctly export, the invention provides a kind of for the used data compression output intent of DRAM recovery test.

Technical solution of the present invention is:

1, a kind of for the required data compression output intent of DRAM reparation, this invention step is as follows:

1) reads the numerical value of 32 cell unit;

2) judge by the algorithm of chip internal whether the cell unit exists fail, if the cell unit does not have fail, then end value is " 1 ", if chip unit has fail, then end value is " 0 ";

3) chip internal to the end value of 32 cell unit carry out " with " computing:

Net result=(unit 1 result) " with " (unit 2 results) " with " (unit 3 results) " with " ... " with " (unit 31 results) " with " (unit 32 results);

4) unique net result value of 32 cell unit of output;

5) after tester table obtained the result of 32 cell unit, if the result is " 0 ", then there was the bit line CSL that breaks down in explanation, and the operation handling procedure makes redundant CSL replace the bit line CSL that breaks down; If the result is " 1 ", the bit line CSL that does not break down is described then.

2, a kind of for the required data compression output intent of DRAM reparation, this invention step is as follows:

1) reads the numerical value of 8 cell unit;

2) judge by the algorithm of chip internal whether the cell unit exists fail, if the cell unit does not have fail, then end value is " 1 ", if there is fail the cell unit, then end value is " 0 ";

3) chip internal to the end value of 8 cell unit carry out " with " computing:

Output result=(unit 1 result) " with " (unit 2 results) " with " (unit 3 results) " with " (unit 4 results) " with " (unit 5 results) " with " (unit 6 results) " with " (unit 7 results) " with " (unit 8 results);

4) unique net result value of 8 cell unit of output;

5) after tester table obtained the result of 8 cell unit, if the result is " 0 ", then there was the bit line CSL that breaks down in explanation, and the operation handling procedure makes redundant CSL replace the CSL that breaks down; If the result is " 1 ", the bit line CSL that does not break down is described then.

Advantage of the present invention:

1, the present invention adopts the data output compress mode of high compression ratio, has reduced IO channel, has increased with the possibility of surveying number, and has reduced the test duration;

2, the present invention greatly reduces testing cost because of the change of compress mode;

3, the selection of data output ratio of compression provided by the present invention makes it under the situation of common no ratio of compression, still can increase with surveying number, reduces the test duration.

Description of drawings

Fig. 1 is the active mode that existing technology internally deposits into capable read-write operation;

Fig. 2 is the test result information recording mode of existing cell;

Fig. 3 is that the present invention adopts 8 cell unit to improve with the way of output of surveying number;

Fig. 4 is that the present invention adopts 8 cell unit to improve the way of output of clock period;

Fig. 5 is the way of output that the present invention adopts 32 cell unit;

Embodiment

The present invention is a kind of to repair required data compression output intent for DRAM, and this invention step is as follows:

1) reads the numerical value of 32 cell unit;

3) chip internal to the end value of 32 cell unit carry out " with " computing:

4) unique net result value of 32 cell unit of output;

The invention provides the another kind of DRAM of being used for and repair required data compression output intent, this invention step is as follows:

1) reads the numerical value of 8 cell unit;

3) chip internal to the end value of 8 cell unit carry out " with " computing:

4) unique net result value of 8 cell unit of output;

In renovation technique, we use redundant word line WL or redundant CSL removes to repair the corresponding WL of the cell that breaks down or CSL; Be example with the CSL reparation, break down in case fail takes place in some cell unit that then Rong Yu CSL is used to repair the CSL that breaks down; And once in fact reparation is exactly that 8 cell unit are replaced together; Under this condition, do not need to know the fail situation of each cell unit, whether what need is to have fail to take place in 8 cell unit of WL and CSL intersection point, therefore in circuit design, the test result of these 8 cell unit will by one " with " logic, finally only export a result:

For this " with " for the logic, when and when having only all unit results for right value, output valve is " 1 ", as long as when having one or more unit end value incorrect, output valve is " 0 " then, means that there is fail the cell unit, needs the carrying out of repairing;

According to this output result, for the chip of DDR2X16, then do not need to export 64 bit, only need 8 bit of output to get final product;

Be example with Fig. 3, in this manner, we have saved the number of IO passage greatly, have improved with surveying number; Be example with Fig. 4, in this manner, we have saved the number of a lot of IO passages, save the clock period simultaneously also to be reduced to 2 by 4, in the reality test, can significantly reduce and read the used time;

According to different technology, variation has also taken place in repair mode; The CSL that no longer is 1 redundancy replaces 1 CSL that breaks down; But 4 redundant CSL repair the CSL that breaks down simultaneously.That is to say in a single day has a cell unit that fail is arranged in 32 cell unit, and the CSL of 4 redundancies can repair corresponding 4 CSL so; In this case, only need know whether 32 unit have fail to take place to get final product; So in circuit design, by " with " logic, make its 32 cell unit finally only export a result:

Output result=(unit 1 result) " with " (unit 2 results) " with " (unit 3 results) " with " ... " with " (unit 31 results) " with " (unit 32 results);

Referring to Fig. 5, according to this output result, for the chip of DDR2X16, then do not need to export 64 bit, only need 2 bit of output to get final product; In this manner, than 8 cell way of outputs, required IO passage is further reduced to has only 1, and the time of reading also reduces to minimum 2 clock period.Increased greatly with surveying number, made it might reach the highest with surveying several 1280 that Adantest T5377 allows; Testing the needed time simultaneously also significantly reduces;

Under this kind technology, for the chip reparation, because its repair mechanism is 4 contemporary replacing of redundant CSL, so the maximal pressure contracting can't further be compressed than for 32:1; And for chip testing, if only need know chip whether fail is arranged, then its ratio of compression can further improve;

In circuit design, we have introduced above two kinds of compress modes simultaneously, under different technology, can select different compress modes;

For DDR1, its ratio of compression is 32:1, and mean to read only needs a data at every turn; For DDR2, its ratio of compression is 64:2 then, and mean to read only needs two bits at every turn; For DDR3, its ratio of compression is 128:4 then, and mean to read only needs 4 bit data at every turn;

At present, the head end test machine is provided by Advantest company, for the tester table of Advantest, whenever reads data, then must need the time of a clock period (clock) to finish;

Referring to Fig. 3, be example with DDR2, read-write each time needs 64 cell unit of operation, if adopt compress mode 8:1,64 cell unit then need to read 8 bit data so, could satisfy our test and repair demand, under this clear condition, we need 2 IO passages and 4 clock cycle, could export 8 needed data;

Referring to Fig. 5, if adopt compress mode 32:1,2 bit data only need be read in 64 cell unit so, can satisfy our test and repair demand, and in this case, I only need 1 IO passage and 2 clock cycle is exportable all data;

Therefore according to different process conditions, technological requirement and concrete condition, adopt this two kinds of data output compress modes, we can reduce test duration and testing cost.

Claims

1. one kind is used for the required data compression output intent of DRAM reparation, and this invention step is as follows:

1) reads the numerical value of 32 cell unit;

3) chip internal to the end value of 32 cell unit carry out " with " computing:

4) unique net result value of 32 cell unit of output;

2. one kind is used for the required data compression output intent of DRAM reparation, and this invention step is as follows:

1) reads the numerical value of 8 cell unit;

3) chip internal to the end value of 8 cell unit carry out " with " computing:

4) unique net result value of 8 cell unit of output;