CN103187280A - Manufacturing method of fin type field effect transistor - Google Patents
Manufacturing method of fin type field effect transistor Download PDFInfo
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- CN103187280A CN103187280A CN2011104534983A CN201110453498A CN103187280A CN 103187280 A CN103187280 A CN 103187280A CN 2011104534983 A CN2011104534983 A CN 2011104534983A CN 201110453498 A CN201110453498 A CN 201110453498A CN 103187280 A CN103187280 A CN 103187280A
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Abstract
A manufacturing method of a fin type field effect transistor comprises the steps of providing a semiconductor substrate; depositing a stopping layer; etching the stopping layer and the semiconductor substrate to form a fin; depositing an oxidation layer to be higher than the stopping layer; conducting chemical mechanical grinding on the oxidation layer until the stopping layer exposes; conducting ion implantation on the oxidation layer; and etching the oxidation layer. Ion implantation is carried out in the oxidation layer for isolating FinFET on bulk silicon to damage the oxidation layer, accordingly etching speed of the oxidation layer is influenced, equivalently an etching stopping layer is arranged in the oxidation layer to enable the thickness of the etching oxidation layer to be controllable, accordingly the height of the fin of the FinFET is easy to control, and unification of the height of the fin can be achieved. In addition, the ion implantation quickens etching rate of the oxidation layer, a footing phenomenon produced by original direct etching is removed.
Description
Technical field
The present invention relates to semiconductor technology and make the field, relate in particular to a kind of manufacture method of fin formula field effect transistor.
Background technology
In order to catch up with the step of Moore's Law, people's have to constantly shorten length of MOSFET field effect transistor raceway groove.Doing like this to increase the tube core of chip density, switching speed of increase MOSFET etc. benefit.Shortening along with device channel length, the distance of drain electrode and source electrode also shortens thereupon, so grid is to the control ability variation of raceway groove, the difficulty of grid voltage pinch off (pinch off) raceway groove is also increasing, so just, make inferior threshold values electric leakage (Subthreshold leakage) phenomenon, i.e. the easier generation of so-called short-channel effect (SCE:short-channel effects).
Because like this, along with the development of semiconductor industry to 22 nm technology node, begin the transition to three-dimensional (3D) FinFET (fin formula field effect transistor) device architecture from the planar CMOS transistor gradually.Among the FinFET, grid can be controlled from both sides to ultra-thin body (fin) at least, have than the control ability of the much better than grid of planar MOSFET device to raceway groove, can be good at suppressing short-channel effect.And other device has the compatibility of better existing integrated circuits production technology relatively.
Fig. 1 shows the perspective view of a kind of FinFET of prior art.As shown in Figure 1, FinFET (fin formula field effect transistor) comprising: Semiconductor substrate 10 is formed with the fin (Fin) 14 of protrusion on the described Semiconductor substrate 10; Oxide layer 11 covers the part of the sidewall of the surface of described Semiconductor substrate 10 and fin 14; Grid structure across on described fin 14, covers top and the sidewall of described fin 14, and grid structure comprises gate dielectric layer (not shown) and the grid 12 that are positioned on the gate dielectric layer.For FinFET, fin 14 all becomes channel region with the part of the contacted top of grid structure and side walls, namely has a plurality of grid, is conducive to increase drive current, improves device performance.
Mainly contain two kinds of technological processes at present and form this device architecture, wherein a kind of is to adopt silicon-on-insulator (SOI) substrate, and another is to use ion to inject and forms the body silicon chip that PN junction carries out the fin isolation.
FinFET technology based on SOI is the simplest.Automatically end when the etching process of formation fin proceeds to the wafer oxidation buried regions, the height of fin will depend on fully that initial SOI goes up the thickness of Si layer.In addition, owing to exist buried oxide, isolate fully in electricity between the adjacent fin, do not need to carry out again extra isolation technology.
Owing to adopt the SOI substrate processing to form in the technology of FinFET, the thickness of SOI substrate top layer Si namely is the height of fin, so thin (about the 20nm) that the thickness requirement of SOI substrate top layer Si will be tried one's best, so it is high more a lot of than adopting body silicon chip formation FinFET cost to adopt the SOI substrate.Such cost is unacceptable for the production of a lot of devices, so need the development bulk silicon technological to form the technology of FinFET.
Compare with SOI, if adopt the body silicon chip, just can't form interface clearly in the bottom of fin, and not have intrinsic separator (oxide layer).Thereby just must adopt extra device isolation technology.After finishing the etching of fin followed by the filling step that will carry out oxide.
Method at body silicon formation FinFET in the prior art forms elongated fin for elder generation's etching groove on body silicon, and deposited oxide layer is filled the groove of fin both sides again, polishes oxide layer subsequently and exposes until silicon.Carry out again oxide layer is carried out the groove etching in order to clean out the space between fin, to determine the height of fin.
Wherein, oxide layer groove etching and initial silicon trench etching phase are similar, all there is not tangible etch stop layer, its etching depth depends on the time of etching fully, and along with fin interval variation in the design when fin density was changed, etching will be subjected to the influence of micro-loading (figure) effect.Like this, be not easy to control and unify the height of the fin of formation in the process with bulk silicon technological flow process making FinFET, and make the width of the assurance fin that must be noted that among the FinFET and highly must be consistent, otherwise just can the performance parameters such as threshold voltage of device be impacted, difference is excessive each other to cause in the circuit each transistorized performance parameter.
And in such etching, the oxide layer etch rate that is close to the side wall of fin can be lower than the oxide layer etch rate that leans on core in the groove, and after etching finished, the phenomenon of footing (label 3 indications) as shown in Figure 2 appearred in meeting in the oxide layer.Like this, the electric property to device also has bad influence.
Summary of the invention
The problem that the present invention solves is to utilize the bulk silicon technological of lower cost to form FinFET, and can control the height of fin preferably, makes the height of fin can reach unified, eliminates the footing phenomenon simultaneously.
For addressing the above problem, the present invention proposes a kind of manufacture method of fin formula field effect transistor, comprising:
Semiconductor substrate is provided;
Deposited barrier layer;
The described barrier layer of etching and Semiconductor substrate form fin;
Deposited oxide layer exceeds described barrier layer;
Carry out cmp to exposing the barrier layer in described oxide layer;
Described oxide layer is carried out ion to be injected;
The described oxide layer of etching;
Optionally, the step of formation fin comprises:
The deposition hard mask layer covers described barrier layer;
Utilize photoresist as the described hard mask layer of mask etching at described hard mask layer;
Remove photoresist;
Utilize hard mask layer as the described barrier layer of mask dry etching and Semiconductor substrate;
Remove described hard mask layer.
Optionally, described Semiconductor substrate is the body silicon substrate.
Optionally, form after the fin, also be included in before the deposited oxide layer and form silicon nitride on the semiconductor that exposes as the step of side wall.
Optionally, described oxide layer is carried out the method for ion injection and expose oxide layer for utilizing photoresist as mask, carry out ion and inject.
Optionally, described oxide layer is carried out the method for ion injection and expose oxide layer for utilizing the barrier layer as mask, carry out ion and inject.
Optionally, the ion source that described ion is injected is inert gas elements.
Optionally, the ion dose scope that described ion is injected be 3E14 to 4E15, energy range is that 2Kev is to 30Kev.
Optionally, the angle that described ion is injected is controlled at ± 40 °.
Optionally, etching proceeds to etch rate at least and slows down and stop in the step of described etching oxidation layer.
Compared with prior art, the present invention has the following advantages:
The present invention injects by ion in the oxide layer of the FinFET on being used for slider silicon and makes oxide layer impaired, thereby influence the etch rate of oxide layer, so just be equivalent in oxide layer, be provided with etching stop layer, make the thickness of etching oxidation layer become controlled, thereby allow the control easily that becomes of the height of fin of FinFET, namely can realize the unification of the height of fin.And ion injects the etch rate of having accelerated oxide layer, and the footing phenomenon that makes originally direct etching to produce has been eliminated.
Description of drawings
Fig. 1 is the perspective view of a kind of FinFET of prior art;
Fig. 2 is for occurring the schematic diagram of footing in the prior art during oxide layer etching;
Fig. 3 to Figure 14 is for forming the schematic diagram of each step of fin formula field effect transistor among the present invention.
Embodiment
The present invention injects by ion in the oxide layer of the FinFET on being used for slider silicon and makes oxide layer impaired, thereby influence the etch rate of oxide layer, so just be equivalent in oxide layer, be provided with etching stop layer, make the thickness of etching oxidation layer become controlled, thereby allow the control easily that becomes of the height of fin of FinFET, namely can realize the unification of the height of fin.And ion injects the etch rate of having accelerated oxide layer, and the footing phenomenon that makes originally direct etching to produce has been eliminated.
Wherein can utilize photoresist to do mask to the method for oxide layer ion injection and carry out the ion injection, also can utilize hard mask layer to carry out ion as mask and inject.
The ion source that ion injects is inert gas elements, because the injection of other element can influence the electric property of fin, so select the inactive inert element of chemical property.And the injection of inert gas makes that also the oxide layer quality that is injected into is sparse, is etched easily, namely helps to increase etch rate.
During concrete enforcement, the method that the present invention forms fin formula field effect transistor comprises:
Semiconductor substrate is provided;
Form pad oxide, barrier layer, hard mask layer and photoresist layer successively;
Photoresist layer forms the figure of fin as the mask etching hard mask layer;
Hard mask layer forms fin as mask etching barrier layer, pad oxide and Semiconductor substrate;
Form oxide layer as abutment wall in the part of exposing the Semiconductor substrate material;
Deposited oxide layer exceeds described fin;
Oxide layer is carried out cmp to exposing the barrier layer;
Described oxide layer is carried out ion to be injected;
It is poor that the described oxide layer of etching to fin and oxide layer has certain height;
Form gate insulation layer;
Form gate material layers;
The described gate material layers of etching forms grid.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public embodiment.
Need to prove that the purpose that these accompanying drawings are provided is to help to understand embodiments of the invention, and should not be construed as restriction improperly of the present invention.For the purpose of clearer, size shown in the figure and not drawn on scale may be done to amplify, dwindle or other changes.
Semiconductor substrate is provided; Described Semiconductor substrate is preferably the body silicon base, also can be germanium silicon substrate, III-V group element compound substrate (as GaAs, indium phosphide, gallium nitride etc.), silicon carbide substrates or its laminated construction, or diamond substrate, perhaps well known to a person skilled in the art other Semiconductor substrate.
As shown in Figure 3, on Semiconductor substrate 100, form pad oxide 102, barrier layer 104, hard mask layer 106 and photoresist layer 108 successively; Wherein, pad oxide 102 is silica, and thickness is 20～60nm, and its generation type is conventional thermal oxidation method, chemical vapor deposition (CVD), physical vapor deposition (PVD) etc.Barrier layer 104 is silicon nitride, and thickness is 100～300nm, and generation type is conventional chemical vapor deposition (CVD), physical vapor deposition (PVD) etc.Hard mask layer 106 is organic antireflection layer or amorphous carbon etc., and it act as the auxiliary layer as photoresist layer 108.Photoresist layer 108 is conventional photoresist, and the mode that adopts rotation to apply forms.
The figure that photoresist layer 108 forms fins is with as the mask in follow-up hard mask layer 106 etching processes; As shown in Figure 4, photoresist layer 108 forms the figure of fin, and its figure generation type is developed for by photomask blank photoresistance is exposed again.Preferably, photoresist is positive photoetching rubber, and the figure of formation is the figure of fin, as shown in FIG., is long and narrow raised line.Be mask with the photoresist that has formed figure, etching hard mask layer 106 is transferred to the figure of fin on the hard mask layer 106, as shown in Figure 5.In addition, what those skilled in the art should understand that is, except the photoresist layer that is formed with the figure of fin with photoresist can be used as the mask, other mode of mask that similarly can form the figure of fin likely all can adopt, just commonly used or preferred mode described herein.The mode of etching hard mask layer is preferably the plasma dry etching, because it has good anisotropy, guarantees that the pattern line width of etching formation is constant.In addition, also comprise the step of removing photoresist layer 108 after etching is intact, form structure as shown in Figure 6.
As shown in Figure 7, with the Semiconductor substrate 100 of hard mask layer 106 as mask etching barrier layer 104, pad oxide 102 and segment thickness.The thickness of carving Semiconductor substrate 100 is 50～200nm, and the lithographic method equally here is the plasma dry etching.Also comprise then and remove hard mask layer 106, to form fin, as shown in Figure 8.Before carrying out subsequent step, here also be included in the part of exposing the Semiconductor substrate material and form oxide or nitride etc. as abutment wall, abutment wall is very thin, and is not shown in present specification, but the art personnel should be understood that and rationally guess its structure.
As shown in Figure 9, deposited oxide layer 110 exceeds described fin, and preferred, oxide layer 110 is silica.Its generation type is conventional thermal oxidation method, chemical vapor deposition (CVD), physical vapor deposition (PVD) etc.Be preferably the silica that the mode that adopts high-density plasma CVD forms, the silica quality densification that this method forms, isolated effective.In addition, its speed that is etched is slower.
Then described oxide layer 110 being carried out ion injects.
The mode of oxide layer 110 being carried out the ion injection has two kinds, and a kind of is to form photoresist layer as mask (not shown), exposes oxide layer, carries out ion then and injects; Another kind is exactly directly to carry out ion to inject because also have barrier layer 104 can be when ion injects as the barrier bed of following pad oxide 102 and Semiconductor substrate 100.
The concrete operations that ion injects may further comprise the steps:
1) silicon chip that will carry out the ion injection is put into reaction chamber, adjusts ion source and guarantees that the ion that injects is N
2, inert gas such as Xe or Ar.Wherein, optimal selection is N
2, what those skilled in the art should be able to understand is, as long as other inert gas elements is not easy to influence the performance of the fin of follow-up formation, all can be used to substitute the limited several elements that exemplify in the present embodiment.
2) the ion energy scope of set injecting be 2Kev to 30Kev, dosage range be 3E14 to 4E15, angle is controlled in ± 40 °.Inject energy of ions by control and adjust the degree of depth that ion injects, and the thickness of oxide layer scope that control is etched.In the present embodiment, the thickness of oxide layer scope that control is etched is for being 10～100nm, the height that is fin is 10～100nm, those skilled in the art should understand the height of the fin that present embodiment narrates and other size just for example, and these sizes will be dwindled and adjust along with the size of integrated circuit.The angle that ion injects generally all is vertical the injection, and owing to the boundary of pad oxide 102 is not easy to be injected into, and needs are bigger near the etch rate of the pad oxide 102 of boundary, avoid forming the footing phenomenon after the etching, so need carry out a period of time injection direction and inject the injection that the normal to a surface direction has certain angle, this angular range control is in ± 40 °.
3) ion implant systems vacuumizes, and carries out ion and injects, and keeps ambient temperature in the injection process about room temperature.
4) after Preset Time arrived, inflation in the chamber of ion implant systems was taken out and is carried out the silicon chip that ion injects.
Ion can carry out etch step after injecting and finishing, and being specially the described oxide layer 110 of etching to fin and oxide layer 110, to have certain height poor, and etching adopts the HF aqueous solution to carry out wet etching.
Can improve significantly through the etch rate of the oxide layer 110 after the ion implantation damage at wet etching.By controlling dosage and the energy of ion injection, control the ion concentration that is doped in the oxidized layer and the degree of depth that is injected into, thereby make the interior etching rate of oxide layer change along with degree of depth difference.Like this, when etching oxidation layer 110, just can produce different signals because of the variation of etch rate, be equivalent in oxide layer 110, be provided with etching stop layer.Utilize suitable etching, can be so that be doped (being damaged) etch rate partly obviously greater than getting not impaired part, and also adopt etching regularly more may produce consistent etching depth simultaneously, that is to say, not impaired partial etching must be slower than doped portion, and with the timing etching, can significantly reduce the not over etching of damaged zone.Therefore, inject the control that has improved the thickness that resulting oxide layer is etched by ion, namely obtained the height control of fin.
Through inventor practice, injecting nitrogen ion is example in the silica that forms in the mode of high-density plasma CVD, and the relation of etch rate of the parameter of ion and oxide layer of injecting is with reference to following table, and wherein, the energy unit that ion injects is eV, and the unit of dosage is cm
-3, counting mode is scientific notation, as: 2.E+15 represents 2 * 15cm
-3, the unit of etch rate is
Etching agent is that the volume ratio of HF and water is 1: 100～1: 500 the HF aqueous solution.
| Sequence number | Energy | Dosage | Etch rate |
| 1 | 0 | 0 | 8.06 |
| 2 | 0 | 0 | 7.95 |
| 3 | 0 | 0 | 7.85 |
| 4 | 4K | 2.E+15 | 32.68 |
| 5 | 4K | 2.E+15 | 32.30 |
| 6 | 4K | 2.E+15 | 32.82 |
| 7 | 4K | 3.E+15 | 32.02 |
| 8 | 4K | 4.E+15 | 33.35 |
| 9 | 8K | 2.E+15 | 36.40 |
| 10 | 10K | 2.E+15 | 37.92 |
As seen 1,2,3 group of not carrying out that ion injects of last table and back carried out that ion injects 4～10 groups under equal conditions carry out wet etching, do not carried out the etch rate of the oxide layer that ion injects on average less than 8
Be far smaller than the oxide layer of carrying out after ion injects all greater than 32
Etch rate.
Because the degree of depth that is damaged can be regulated by the energy that changes the ion injection, in etching, when etching proceed to carved the silica part that is damaged after, etching can be carried out very slowly, like this, etch period is set to omit miniature carving and crosses the silica part that is damaged, and the degree of depth that just is equivalent to etching can be injected to arrange by ion.
After injecting, the ion of the same terms carries out the wet etching of the same terms at the silica of the same terms growth, its from used time of beginning to be etched into etching and slowing down be consistent with the degree of depth that it is etched, so just can control and form height consistency fin preferably.
The structure that etched portions oxide layer 110 backs form as shown in figure 11.
Remove the structure of barrier layer 104, pad oxide 102 formation as shown in figure 12, the difference in height of oxide layer 110 and semiconductor substrate layer 100 is the height of fin.The mode of removing can be wet etching, or dry etching.
As shown in figure 13, deposition goes up gate insulation layer (not mark), gate material layers 112 again.Preferably, gate insulation layer is silica, and gate material layers is polysilicon.The generation type of gate insulation layer is conventional thermal oxidation method, chemical vapor deposition (CVD), physical vapor deposition (PVD) etc.Gate material layers can be by under low pressure, and pyrolysis silane when temperature is 570～650 ℃ carries out low-pressure chemical vapor phase deposition and forms.
The described gate material layers of etching forms grid, forms structure as shown in figure 14.
The follow-up generation side wall that also comprises carries out the source to the fin two ends and leaks steps such as doping.
Namely formed FinFET of the present invention.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art are not breaking away under the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. the manufacture method of a fin formula field effect transistor is characterized in that, comprising:
Semiconductor substrate is provided;
Deposited barrier layer;
The described barrier layer of etching and Semiconductor substrate form fin;
Deposited oxide layer exceeds described barrier layer;
Carry out cmp to exposing the barrier layer in described oxide layer;
Described oxide layer is carried out ion to be injected;
The described oxide layer of etching.
2. manufacture method as claimed in claim 1 is characterized in that, the step of described formation fin comprises:
The deposition hard mask layer covers described barrier layer;
Utilize photoresist as the described hard mask layer of mask etching at described hard mask layer;
Remove photoresist;
Utilize hard mask layer as the described barrier layer of mask dry etching and Semiconductor substrate;
Remove described hard mask layer.
3. manufacture method as claimed in claim 1 is characterized in that, described Semiconductor substrate is the body silicon substrate.
4. manufacture method as claimed in claim 1 is characterized in that, forms after the fin, also is included in before the deposited oxide layer to form silicon nitride on the Semiconductor substrate of exposing as the step of side wall.
5. manufacture method as claimed in claim 1 is characterized in that, described oxide layer is carried out the method for ion injection and exposes oxide layer for utilizing photoresist as mask, carries out ion and injects.
6. manufacture method as claimed in claim 1 is characterized in that, described oxide layer is carried out the method for ion injection and exposes oxide layer for utilizing the barrier layer as mask, carries out ion and injects.
7. manufacture method as claimed in claim 1 is characterized in that, the ion source that described ion injects is inert gas elements.
8. manufacture method as claimed in claim 1 is characterized in that, the ion dose scope that described ion injects be 3E14 to 4E15, energy range is that 2Kev is to 30Kev.
9. manufacture method as claimed in claim 1 is characterized in that, the angle control that described ion injects is at ± 40 °.
10. manufacture method as claimed in claim 1 is characterized in that, etching proceeds to etch rate at least and slows down and stop in the step of described etching oxidation layer.
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Cited By (3)
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| CN104733313A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| CN105097584A (en) * | 2014-05-15 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Detection method for ion implantation dosage |
| US10665514B2 (en) | 2018-06-19 | 2020-05-26 | International Business Machines Corporation | Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal |
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| US6835655B1 (en) * | 2001-11-26 | 2004-12-28 | Advanced Micro Devices, Inc. | Method of implanting copper barrier material to improve electrical performance |
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| CN104733313A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| CN104733313B (en) * | 2013-12-18 | 2018-02-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin formula field effect transistor |
| CN105097584A (en) * | 2014-05-15 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Detection method for ion implantation dosage |
| US10665514B2 (en) | 2018-06-19 | 2020-05-26 | International Business Machines Corporation | Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal |
| US10770361B2 (en) | 2018-06-19 | 2020-09-08 | International Business Machines Corporation | Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal |
| US10892193B2 (en) | 2018-06-19 | 2021-01-12 | International Business Machines Corporation | Controlling active fin height of FinFET device |
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Application publication date: 20130703 |