CN103199845A - Two-way buffer based on open-drain bus - Google Patents
Two-way buffer based on open-drain bus Download PDFInfo
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- CN103199845A CN103199845A CN2012100049625A CN201210004962A CN103199845A CN 103199845 A CN103199845 A CN 103199845A CN 2012100049625 A CN2012100049625 A CN 2012100049625A CN 201210004962 A CN201210004962 A CN 201210004962A CN 103199845 A CN103199845 A CN 103199845A
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Abstract
The invention discloses a two-way buffer based on an open-drain bus. The buffer comprises a reference voltage and reference current generating module, a source end data comparing machine, a source end data operation amplifier, a source end data choosing and driving machine, and a subordinate end data choosing and driving circuit, wherein the source end data comparing machine compares an input signal of a source end with a reference voltage, outputs a high level when the input signal of the source end is higher than the reference voltage and outputs a low level when the input signal of the source end is lower than the reference voltage, the source end data operation amplifier works in a closed loop mode and is used for helping subordinate end data to be accurately transmitted to the source end, the source end data choosing and driving machine is used for choosing source end data, transmitting to a subordinate end and conducting driving boost, and the subordinate end data choosing and driving circuit is used for choosing the subordinate end data, transmitting to the source end and conducting driving boost. The two-way buffer can not only work across voltage domains, but also avoid the latched problem of bus data transmission.
Description
Technical field
The present invention relates to CMOS integrated circuit (IC) design field, particularly relate to a kind of based on opening the Lou bidirectional buffer of bus.
Background technology
In opening the agreement of bus Lou, all comprise a data/address bus and a clock bus usually.I for example
2C bus (Inter-Integrated Circuit Bus), System Management Bus (System Managements Bus).Every bus is all by moving power supply on the pull-up resistor, and all there is parasitic capacitance in every bus.The speed of transfer of data relies on the size of resistance and electric capacity.
In order to increase the transmission rate of data, must reduce the bus parasitic capacitance.Therefore need to introduce buffer, bus is divided into multistage, thereby every section parasitic capacitance is obviously reduced.
When principal and subordinate's device of bus was operated in different voltage domain, bus must be introduced buffer, made bus data can stride the voltage domain transmission.Bus is two-way because open Lou again, and therefore the buffer of introducing must be bidirectional buffer.But general bidirectional buffer can produce the problem that latchs of data.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of based on opening the Lou bidirectional buffer of bus, can realize that bus data strides voltage domain transmission, avoids occurring latching of bus data transmission.
For solving the problems of the technologies described above, of the present invention based on opening the Lou bidirectional buffer of bus, comprising:
Reference voltage and reference current generation module adopt band-gap reference circuit commonly used, for source end data comparator and source end data operational amplifier provide accurate reference voltage and reference current;
Source end data comparator, data signal bus and reference voltage that the source end is imported compare; When the data signal bus of source end input was higher than reference voltage, described source end data comparator was output as high level (logical one); When the data signal bus of source end input was lower than reference voltage, described source end data comparator was output as low level (logical zero);
Source end data operational amplifier, closed loop work is used for assisting the bus data from end correctly to transmit to the source end;
The source end data is selected and driver, is connected with the output of source end data comparator, is used for selection source end bus data, it is transferred to from end, and drives reinforcement;
Select and drive circuit from end data, be used for selecting it being transferred to the source end, and driving reinforcement from the end bus data;
Described bidirectional buffer realizes striding voltage domain work, only source end data signal bus is detected and adjudicates, and has simplified circuit design; When by the source end to from end transfer bus data the time, can not open source end transmitter from the data signal bus that end feeds back to; When from end during to source end transfer bus data, source end data comparator output signal is constant, guarantees to close from the end transmitter.
Described bidirectional buffer is applicable to the opener electrode bus.Described bidirectional buffer is applicable to the unidirectional leakage bus of opening.Described bidirectional buffer adopts enable signal, and when opening that Lou bus is not worked, whole bidirectional buffer is closed.
Sometimes stride voltage domain work owing to open bus, (latch up) problem that latchs that general logic design method exists bus data to transmit with Louing.The present invention at generally opening the Lou defective of bus bidirectional buffer, adopts analog-and digital-combination to realize based on opening the Lou bidirectional buffer of bus according to opening the Lou application demand of bus; Open Lou bus cross voltage domain characteristic and the problem that latchs forms reason by analysis, utilize operational amplifier and comparator, will latch and form loop and disconnect, thereby make the bus can normal communication.Of the present inventionly can realize striding voltage domain work based on opening the Lou bidirectional buffer of bus, well solve bus data and striden the voltage domain transmission, can avoid occurring the problem that latchs of bus data transmission again.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the existing Lou bus bidirectional buffer Organization Chart of opening;
Fig. 2 is of the present invention based on opening the Lou bidirectional buffer one embodiment Organization Chart of bus;
Fig. 3 is based on out the bidirectional buffer circuit theory diagrams that leak bus.
Embodiment
At opening Lou bus cross voltage domain work, and general bidirectional bus buffer exists and latchs problem, and the present invention adopts the design of analog-and digital-circuit combination, realizes based on opening the Lou bidirectional buffer of bus.
Referring to shown in Figure 1, existing based on opening the Lou bidirectional buffer of bus, comprising: source terminal circuit 100 and from terminal circuit 200.When data signal bus by the source end to from when transmission end, this data signal bus arrives node 1 through the data buffer 110 of source terminal circuit 100 earlier, through deliver to the grid of second nmos pass transistor (from the end transmitter) 230 from terminal circuit 200 from the inverter 220 of terminal circuit 200, arrive from end by second nmos pass transistor 230 at last then.In like manner, by from end during to source end transfer bus data, this bus data arrives node 2 through the data buffer 210 from terminal circuit 200, deliver to the grid of first nmos pass transistor (source end transmitter) 130 of source terminal circuit 100 then through the inverter 120 of source terminal circuit 100, arrive the source end by first nmos pass transistor 130 at last.
In order to adapt to out the bus cross voltage domain work of leaking, source end and must satisfy the withstand voltage condition of voltage domain separately from nmos pass transistor and the data buffer of end.
But bidirectional buffer shown in Figure 1 has been introduced the problem of latching.Suppose current by the source end to from end transfer bus data, rectify at transmission logic 0 in the source, then node 1 be logical zero, through inverter 220 and second nmos pass transistor 230 from terminal circuit 200, is logical zero from end; Pass to node 2 from the logical zero of end through the data buffer 210 from terminal circuit 200, make node 2 be logical zero, through the inverter 120 of source terminal circuit 100, the grid that makes first nmos pass transistor 130 is high level, makes the source end keep logical zero.
When source end external circuit discharges when leaking bus, the source end should become logical one, but because first nmos pass transistor 130 of source terminal circuit 100 is still opened at present, so source end reality also remains logical zero, can not transmit the logical one signal of reality; Here it is latchs problem.
In order to solve the problem of latching, must stop the reverse transfer of data signal bus.Namely when by the source end to from end transfer bus data the time, can not pass to the source end from the bus data of end; When by from end to source end transmission data the time, the bus data of source end can not be transferred to from end.As shown in Figure 2, for this reason, introduce core circuit 300, data buffer 110 and the inverter 120 of source terminal circuit 100 among Fig. 1 saved, form source terminal circuit 400.By core circuit 300, stop the reverse transfer of data signal bus.
Vdd1 among Fig. 1, Fig. 2 is source end power supply, and vdd2 is from the end power supply.For convenience of explanation, first nmos pass transistor 130 of source terminal circuit 400 among Fig. 2 and core circuit 300 are merged, generate shown in Figure 3 based on opening the Lou bidirectional buffer circuit of bus.
In bidirectional buffer circuit shown in Figure 3, VIL_REF is the reference voltage that is input to source end data comparator (CMP) 350 reverse input ends.VOL_REF is the reference voltage that is input to source end data operational amplifier (AMP) 310 reverse input ends.Data signal bus reverse transfer in order to stop data signal bus when transmission to exist requires VIL_REF＜VOL_REF here.IBNin and IBNout are respectively the reference currents of source end data comparator (CMP) 350 and source end data operational amplifier (AMP) 310.
In order to save power consumption, introduce enable signal DDC_EN, when opening that Lou bus is not worked, whole bidirectional buffer circuit can be closed.
When enable signal DDC_EN is logical one, by the source end to from end transmission data the time, be higher than reference voltage VIL_REF if be input to the source end node voltage of source end data comparator (CMP) 350 positive inputs, the node n2 that then is positioned at source end data comparator (CMP) 350 outputs is logical one (high level).The logical one signal of node n2 be input to by or an input of the source end data selector 360 that constitutes of door, another input of source end data selector 360 is imported the first inner enable signal enb.When enable signal DDC_EN was logical one, the first inner enable signal enb was logical zero, and source end bus data can pass through, and the node SINK_TO_PAD that is positioned at source end data selector 360 outputs is logical one; When enable signal DDC_EN was logical zero, the first inner enable signal enb was logical one, and source end bus data can not pass through.Be positioned at from the inverter 220 of terminal circuit 200 when realizing signals reverse, as source end data driver, increase the driving force to subsequent conditioning circuit.
When node SINK_TO_PAD was logical one, node SINK_FROM_PAD was logical one.The logical one signal of node SINK_FROM_PAD through inverter 320 be input to by NAND gate constitute from end data selector 330 1 inputs, should import the second inner enable signal en from another input of end data selector 330.When the second inner enable signal en is logical one, can pass through from the end bus data, when the second inner enable signal en is logical zero, can not pass through from the end bus data.
When node SINK_FROM_PAD is logical one, being positioned at from the node n4 of end data selector 330 outputs is logical one, the 3rd nmos pass transistor 340 is opened, making the node n5 that is positioned at 340 drain electrodes of the 3rd nmos pass transistor and source end data operational amplifier (AMP) 310 outputs is logical zero, and first nmos pass transistor 130 is closed.The 3rd nmos pass transistor 340 is equivalent to from the end data driver, guarantees when node n4 is logical one, can draw node n5 to be logical zero.
If source end node voltage is lower than reference voltage VIL_REF, then node n2 is logical zero, and node SINK_TO_PAD is logical zero; Node SINK_FROM_PAD is logical zero, and node n4 is logical zero, and the 3rd nmos pass transistor 340 is closed.Because source end node voltage is lower than reference voltage VIL_REF, so source node voltage is lower than reference voltage VOL_REF, guarantee that like this node n5 is logical zero, first nmos pass transistor 130 is closed.
When the end node change in voltage of source, first nmos pass transistor 130 is in closed condition always, has blocked by the transmission of the reverse data from end to the source end.
When enable signal DDC_EN is logical one, by from end to the source end during transmission data, if be logical one from end node voltage, then node SINK_FROM_PAD is logical one, and node n4 is logical one, and the 3rd nmos pass transistor 340 is opened, node n5 is haled logical zero, and the source end node is output as logical one.When the source end node is logical one, its voltage is higher than reference voltage VIL_REF, the node n2 that is positioned at source end data comparator (CMP) 350 outputs is logical one, node SINK_TO_PAD is logical one, be logical zero from the grid of second nmos pass transistor 230 of end, second nmos pass transistor 230 is closed, do not influence the data that send from end.
When sending logical zero from end, then node SINK_FROM_PAD is logical zero, and node n4 is logical zero, and the 3rd nmos pass transistor 340 is closed.What source end data operational amplifier 310 and first nmos pass transistor 130 constituted is negative-feedback circuit.If the voltage of source end node is higher than reference voltage VOL_REF, then the voltage of node n5 raises, and first nmos pass transistor, 130 discharge capabilities are strengthened, and source end node voltage reduces.As long as first nmos pass transistor, 130 sizes are enough big, source end node voltage finally by clamped at reference voltage VOL_REF.If source end node voltage is lower than reference voltage VOL_REF, the voltage at node n5 place can reduce, and first nmos pass transistor, 130 ducting capacity weaken, and source end node voltage rises, and ultimate source end node voltage also equals reference voltage VOL_REF.In a word, when transmitting logical zero from end to the source end when low, source end node voltage by clamped at reference voltage VOL_REF.As long as reference voltage VOL_REF is in opening the voltage range that Lou bus logic 0 is stipulated, the source end is just handled according to logical zero.Because reference voltage VOL_REF is greater than reference voltage VIL_REF, so node n2 is output as logical one, the voltage at node SINK_TO_PAD place is logical one, making from the grid voltage of holding second nmos pass transistor 230 through the inverter 220 from end is logical zero, second nmos pass transistor 230 is closed, and does not influence the data signal bus that sends from end.
When from the end node change in voltage, be in closed condition from second nmos pass transistor of holding 230 always, blocked by the source end to the reverse data transmission from end.
In Fig. 3, enable signal DDC_EN produces the first inner enable signal enb through inverter 370, and the first inner enable signal enb produces the second inner enable signal en through inverter 380.Inverter 370 and inverter 380 have strengthened the driving of the first inner enable signal enb and the second inner enable signal en respectively.
If open Lou bus cross voltage domain work, namely source end power supply vdd1 is not equal to from end power supply vdd2, so the source end, must satisfy the withstand voltage condition of voltage domain separately from the nmos pass transistor of end, guarantee that bidirectional buffer finishes transmitted in both directions.
More than by embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. one kind based on opening the Lou bidirectional buffer of bus, it is characterized in that, comprising:
Reference voltage and reference current generation module are for source end data comparator and source end data operational amplifier provide reference voltage and reference current;
Source end data comparator, data signal bus and reference voltage that the source end is imported compare; When the data signal bus of source end input is higher than reference voltage, be output as high level; When the data signal bus of source end input is lower than reference voltage, be output as low level;
Source end data operational amplifier, closed loop work is used for assisting correctly transmitting to the source end from the end bus data;
The source end data is selected and driver, is connected with the output of described source end data comparator, is used for selection source end bus data, it is transferred to from end, and drives reinforcement;
Select and drive circuit from end data, be used for selecting it being transferred to the source end, and driving reinforcement from the end bus data;
Described bidirectional buffer realizes striding voltage domain work; Only source end data signal bus is detected and adjudicates; When the source end to from end transfer bus data the time, the data signal bus that feeds back to from end can not be opened the transmitter of source end; When from end during to source end transfer bus data, source end data comparator output signal is constant, guarantees to rectify normal transfer bus data to the source from end.
2. bidirectional buffer according to claim 1, it is characterized in that: described bidirectional buffer is applicable to the opener electrode bus.
3. bidirectional buffer according to claim 1, it is characterized in that: described bidirectional buffer is applicable to the unidirectional leakage bus of opening.
4. bidirectional buffer according to claim 1 is characterized in that: adopt enable signal, when opening that Lou bus is not worked, whole bidirectional buffer is closed.
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| CN201210004962.5A CN103199845B (en) | 2012-01-09 | 2012-01-09 | Bidirectional buffer based on open drain bus |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210004962.5A CN103199845B (en) | 2012-01-09 | 2012-01-09 | Bidirectional buffer based on open drain bus |
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| CN103199845A true CN103199845A (en) | 2013-07-10 |
| CN103199845B CN103199845B (en) | 2017-03-15 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639144A (en) * | 2013-11-08 | 2015-05-20 | 上海华虹集成电路有限责任公司 | Bidirectional analogue buffer circuit |
| CN107367697A (en) * | 2017-08-24 | 2017-11-21 | 武汉大学 | A kind of double detector lithium battery surface temperature detector and method |
| CN113131920A (en) * | 2021-04-09 | 2021-07-16 | 成都芯源系统有限公司 | Fast low bias voltage bi-directional buffer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5801549A (en) * | 1996-12-13 | 1998-09-01 | International Business Machines Corporation | Simultaneous transmission bidirectional repeater and initialization mechanism |
| US6037803A (en) * | 1997-12-12 | 2000-03-14 | Micron Electronics, Inc. | Integrated circuit having two modes of I/O pad termination |
| CN1497413A (en) * | 2002-09-25 | 2004-05-19 | 三星电子株式会社 | Simultaneous two-way input/output circuit |
-
2012
- 2012-01-09 CN CN201210004962.5A patent/CN103199845B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5801549A (en) * | 1996-12-13 | 1998-09-01 | International Business Machines Corporation | Simultaneous transmission bidirectional repeater and initialization mechanism |
| US6037803A (en) * | 1997-12-12 | 2000-03-14 | Micron Electronics, Inc. | Integrated circuit having two modes of I/O pad termination |
| CN1497413A (en) * | 2002-09-25 | 2004-05-19 | 三星电子株式会社 | Simultaneous two-way input/output circuit |
Non-Patent Citations (1)
| Title |
|---|
| 蒋俊华: "基于FPGA的I2C总线控制器的设计", 《中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639144A (en) * | 2013-11-08 | 2015-05-20 | 上海华虹集成电路有限责任公司 | Bidirectional analogue buffer circuit |
| CN104639144B (en) * | 2013-11-08 | 2018-02-13 | 上海华虹集成电路有限责任公司 | Bidirectional analog buffer circuits |
| CN107367697A (en) * | 2017-08-24 | 2017-11-21 | 武汉大学 | A kind of double detector lithium battery surface temperature detector and method |
| CN113131920A (en) * | 2021-04-09 | 2021-07-16 | 成都芯源系统有限公司 | Fast low bias voltage bi-directional buffer |
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| CN103199845B (en) | 2017-03-15 |
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