CN103259528A

CN103259528A - Integrated circuit of an isomerism programmable logic structure

Info

Publication number: CN103259528A
Application number: CN2012100381146A
Authority: CN
Inventors: 王潘丰; 崔运东; 王海力
Original assignee: Capital Microelectronics Beijing Technology Co Ltd
Current assignee: Capital Microelectronics Beijing Technology Co Ltd
Priority date: 2012-02-17
Filing date: 2012-02-17
Publication date: 2013-08-21

Abstract

The invention provides an integrated circuit. A basic unit of the integrated circuit comprises lookup tables of a first number and registers of a second number, wherein the first number is larger than the second number, and output of the lookup tables is coupled to data input ends of the registers through at least one first multiplexer. According to the integrated circuit, resources of the lookup tables are richer than resources of the registers, the area of a chip is saved, and the use ratio of the chip is improved.

Description

A kind of integrated circuit of isomery programmable logic structure

Technical field

The present invention relates to the FPGA field, relate in particular to a kind of isomery programmable logic structure.

Background technology

FPGA (Field-Programmable Gate Array), namely field programmable gate array has the advantages that to allow repeatedly to programme with quick finished product, therefore uses more and more widely.

The logic of main flow FPGA in the market all adopts the isomorphism structure, LUT4 (realization combinational logic) is 1: 1 with the ratio of register (realization sequential logic), the advantage of doing like this is that software is easy to deal with, does not need special algorithm process when place and route.

Figure 1 shows that the structure of the basic logic unit (CLB) of Xilinx Spartan3, the ratio that can see its LUT4 and register is 1: 1.F-LUT and G-LUT are LUT4 among the figure, and FFX and FFY are register.

Figure 2 shows that the structure of the basic logic unit (CLB) of Altera CycloneII, the ratio that can see its LUT4 and register is 1: 1.

But pass through the analysis discovery to the Benchmark (test case) of a large amount of FPGA, major applications for FPGA, it is not 1: 1 that its combinational logic is mapped to the ratio that quantity behind the LUT4 and sequential logic be mapped as the quantity behind the register, and combinational logic occupies higher ratio.In other words, under prior art, the ratio of combinational logic and register can not reflect the demand of practical application, causes the utilance of chip limited.

Summary of the invention

The embodiment of the invention provides the solution that can overcome the problems referred to above.

The embodiment of the invention provides a kind of integrated circuit.The elementary cell of this integrated circuit comprises the look-up table of first quantity and the register of second quantity, and first quantity is greater than second quantity; Wherein the data input pin of register is coupled in the output of look-up table by at least one first multiplexer.

Preferably, described integrated circuit comprises second multiplexer, is used for the output of register is coupled to the input of look-up table.

Preferably, the input signal of first multiplexer directly is coupled from the input signal of elementary cell.

Preferably, the look-up table of first quantity comprises the look-up table of being with carry chain.

In embodiments of the present invention the resource of look-up table than the aboundresources of register some, can save chip area, improve the utilance of chip simultaneously.

Description of drawings

Below by drawings and Examples, technical scheme of the present invention is described in further detail.In the accompanying drawing,

Figure 1 shows that the structure of the basic logic unit of Xilinx Spartan;

Figure 2 shows that the structure of the basic logic unit of Altera CycloneII;

Figure 3 shows that the basic composition structure chart of basic logic unit;

Fig. 4 is the basic structure of LE elementary cell LP.

Embodiment

Find by the analysis to the Bechmark (test case) of lot of F PGA, major applications for FPGA, it is not 1: 1 that its combinational logic is mapped to the ratio that quantity behind the LUT4 and sequential logic be mapped as the quantity behind the register, and combinational logic occupies higher ratio.

Table 1 is depicted as MCNC (Microelectronics Center of North Carolina, north Caro Linne microelectronics center) tabulation of the number of LUT4 and register in test case (benchmark) and some test cases of VPR (Versatile place and route, general layout and route).Can see that for most application the ratio of combinational logic is compared sequential logic and wanted high.15 times of the number average out to register number of the examples of applications LUT4 that this tabular goes out.

Table 1

Blif net table after the benchmark of attention: MCNC and VPR is comprehensively, in order to count the number of LUT4, to the mapping tool of all blif through VPR5.0, combinational logic is mapped to basic LUT4 unit, the numerical value of the LUT4 that can obtain obtaining in the above table and register then

Based on above-mentioned discovery, the present invention has designed a kind of fpga logic structure of isomery, and the ratio of LUT4 and register is not 1: 1, and the number of LUT4 is more than the number of register, can effectively save area of chip, and improve the ratio (lut density) of unit are LUT4.

Figure 3 shows that the basic composition structure chart of basic logic unit LE (logic element, logical block).LE forms LP0, LP1, LP2, LP3 by for example 4 LP (Logic parcel).

Each LP comprises 2 LUT4,1 LUT4C and 2 registers, and wherein, LUT4C is the LUT4 of band carry chain.LE has 12 LUT4 and 8 registers altogether, and the ratio of LUT4 and register is 3: 2.Ratio according to lot of F PGA benchmark combination logic resource and sequential logic resource in the table 1, the resource consumption of combinational logic part is bigger than the sequential logic part, the resource of LUT4 than the aboundresources of register some, can save chip area, improve the utilance of chip simultaneously.

It may be noted that in this manual logic chip only is a kind of segmentation of logical block.The present invention is not restricted to have the integrated circuit of logic chip, also should contain the integrated circuit with various logical units that embodies thinking of the present invention.

Fig. 4 is the basic structure of LE elementary cell LP (Logic parcel).(lut41) (reg0 reg1) forms LP with two registers for lut0, lut40 by three LUT4.Wherein, LUT4 is the look-up table of 4 inputs, and LUT4C is the LUT4 that brings a chain structure into.Certainly, also can adopt the look-up table of other input number, such as LUT6.Those skilled in the art will recognize that the quantity of LUT4 and LUT4C only belongs to for example, look-up table can all not brought a chain structure into, can all adopt carry chain structure yet, and perhaps other ratio form does not bring a chain structure into and bring the combination of a chain structure into.

Be in the middle of 3: 2 the heterogeneous structure at this LUT4 and register, by multiplexer, can guarantee that the output of any LUT4 can arrive the input of any one register, make things convenient for the layout of software.

The output signal of LUT41 can be passed through dy[0] directly export, also can be input to the data input pin of register reg0 by multiplexer mux_di4, can also be input to the data input pin of register reg1 by multiplexer mux_di0.

Equally, the output signal of LUT0 can be passed through dx[0] directly export, also can be input to the data input pin of register reg0 by multiplexer mux_di4, can also be input to the data input pin of register reg1 by multiplexer mux_di0.

The output signal of LUT40 can be passed through dx[4] directly export, also can be input to the data input pin of register reg0 by multiplexer mux_di4, can also be input to the data input pin of register reg1 by multiplexer mux_di0.

In the drawings, REG0 and REG1 have adopted two cover clock clock, and described clock can distribute as master clock with from clock.Certainly, in other scheme, REG0 can adopt different control clocks with REG1, perhaps adopts same clock.

Other control signal of REG0 and REG1 also can be identical, also can be different.Those skilled in the art can easily find the realization details of these control signals of register according to instruction of the present invention, does not give unnecessary details again at this.

It may be noted that, though the output signal of each LUT can be input to the data input pin of any one register REG in the preamble, but the output signal of certain or some LUT can be input to certain register selectively, but not whole data input pins of registers.

Be that the output of register has the fast feedback channel to LUT4 in the middle of 3: 2 the heterogeneous structure at this LUT4 and register.The output signal of register reg0 is by the input of multiplexer muxf3_141 input LUT41, by the input of multiplexer muxf2_140 input LUT40.Equally, the output signal of register reg1 is by the input of multiplexer muxf2_10 input LUT0.

It may be noted that the fast feedback channel that register outputs to LUT can select to be arranged between the combination in any of register and LUT.

Those skilled in the art will recognize that it is 3: 2 heterogeneous structure that the heterogeneous structure of the embodiment of the invention is not limited to LUT4 and register, the heterogeneous structure of other form also is feasible.

For above-mentioned heterogeneous structure, can adopt a kind of layout method of Logic Cluster.Said method comprising the steps of: the gate level netlist after reading in comprehensively is mapped as circuit meshwork list with described gate level netlist; From described circuit meshwork list read module information, described module information comprises look-up table, register; According to the annexation of described look-up table and described register, with described look-up table and the packing of described register, in order to set up a plurality of elementary cells; According to delay value information and crucial degree information, select a elementary cell in described a plurality of elementary cell as first element of Logic Cluster; According to the gain of other elementary cells except described first element in described a plurality of elementary cells, and whether described other elementary cells satisfy constraints, described first element carried out divergence process, in order to set up Logic Cluster; Described constraints comprises whether look-up table or the register in the described Logic Cluster satisfies specified coordinate constraint and capacity-constrained; According to the coordinate constraint of the elementary cell in the described Logic Cluster, the described elementary cell in the described Logic Cluster is carried out the step of layout.The denomination of invention that the details of described layout method are submitted to referring to the applicant is that " layout method of Logic Cluster ", attorney docket are the application for a patent for invention of " CP11395 ".

Above-described embodiment further describes purpose of the present invention, technical scheme and beneficial effect.Institute it should be understood that the above only is the specific embodiment of the present invention, and is not intended to limit the scope of the invention.Within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. integrated circuit, the elementary cell of this integrated circuit comprises the look-up table of first quantity and the register of second quantity, first quantity is greater than second quantity; Wherein the data input pin of register is coupled in the output of look-up table by at least one first multiplexer.

2. integrated circuit as claimed in claim 1 comprising second multiplexer, is used for the output of register is coupled to the input of look-up table.

3. integrated circuit as claimed in claim 1, wherein the input signal of first multiplexer directly is coupled from the input signal of elementary cell.

4. integrated circuit as claimed in claim 1, wherein the look-up table of first quantity comprises the look-up table of being with carry chain.