CN1033116C - 互补金属氧化物半导体集成电路 - Google Patents
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- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 4
- 230000002349 favourable effect Effects 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 17
- 238000009826 distribution Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- 239000010703 silicon Substances 0.000 description 1
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Abstract
大型集成电路中的重要问题是叠加到电源上的因触发器等开关元件的开关过程和输出级过负荷引起的噪音。这些元件造成电流峰值而使电压波动较大。在带标准元件或带定制的电路块的CMOS电路中,通过在走线通道中呈额外的阱的形式的附加去耦电容较有效地解决上述问题。紧靠开关元件设置去耦电容对抑制电源噪音有利。因为走线通道并不供电路元件使用,所以芯片的表面积不致因该额外电容而增加。
Description
本发明涉及一种COMS(互补金属氧化物半导体)集成电路,该集成电路包括一个半导体基片,该基片有一个基本上是第一导电型的层状区,该层状区毗邻着一个表面,该层状区中设有电路,该电路至少具有两个毗邻的电路块,它们被一个中间区所分隔,该电路特别地(但并非绝对)由成排的标准元件所构成,而且该电路块是由一些具有第二导电型沟道的MOS晶体管和一些具有第一导电型沟道的MOS晶体管组成,前一种MOS晶体管设在第一导电型层状区中,后一种MOS晶体管设在第二导电型的表面区(以下,称之为第一表面区)中,该表面上覆有电绝缘层,电绝缘层上形成有配线图形,配线图形由设在中间区上方的电源线和一条或多条信号线组成。
在由H.Veendrick编写、由荷兰Amerongen的Delta Press Bv出版社于1990年出版的《MOS集成电路—VLSI和ASIC介绍》一书,特别是在其第376-377页上,介绍了用标准元件制成的集成电路。标准元件可具有高度尺寸相同的各种逻辑电路。各元件成行排列,各行之间被无晶体管的间隔而隔开,这些间隔即用作配线通道。配线通道中形成有许多导线线路,用以将各元件互连起来,从而将信号从一个元件引到另一个元件。配线通道的宽度可随配线量而异。各电源线通常设在各元件的正上方,但有时也设在配线通道之中。
大型集成电路中的主要问题可能是叠加到电源噪音。这种噪间可以由例如某些元件(例如触发器)的开关操作过程而产生,特别是多个元件同时转换时,各电源线中就会局部出现相当大的电流,从而出现很高的电压峰值。噪音的另一个来源可能在是输出负荷大的情况下产生的。电源的峰值电流可能会使电路电压发生变化,这对例如速率和可靠性之类的参数有不利的影响。加拿大专利1,204,511提出了借助去耦电容减少电源噪音的作法,该去耦电容是由一个局部电容器构成的,局部电容则由与电源相连接的一个加有反向偏压的pn结组成。该电容器需要占据额外的空间,因而使晶片变得较大,从而提高电路的造价。此外,往往总希望将去耦电容器安置得比该已知电路相距引起所述电流峰值的元件更近一些。
显然,上述问题不仅仅出现在各标准元件中。本发明就由电路块组成的电路提出解决上述问题的辨法,各所述电路块由各电路部分组成,这些电路块在芯片上以大体上有规则的图形而形成,各电路块彼此之间为多个迂回通道所分隔。
本发明的目的是提供本说明书开头所述的那种器件,器件中无需另设额外的空间即可获得最大的去耦电容。本发明的另一个目的是将所述去耦电容安置得尽可能靠近各元件,从而使电流峰值实际上仅仅局部地出现,而不影响或基本上不对电路的其它部分形成串扰。
按照本发明,本发明书开头所述的那种CMOS集成电路的特征在于,第一导电型的层状区在各信号线底下的中间区部分另外配备有一个或多个第二导电型表面区,该表面区与电源线相连接。由于半导体基片配线通道底下的空间通常不是供电路元件用的,因而在配线通道底下另设去耦电容并不占额外的空间,因而表面积也不增加。此外,由于采用了本发明,去耦电容可以安置在距各开关元件很小的一段距离处。
本发明的一个特殊实施例具有这样的优点:所述第一表面区可同时设置有另外的表面区,该特殊实施例的特征在于,该另设的表面区的厚度和掺杂浓度与设有其通道为第一导电型的MOS晶体管的第一表面区相同。本发明器件的另一个实施例的另设的表面区无需独立分开的接触点,该实施例的特征在于,至少其中的一个另设的表面区与至少其中的一个第一表面区一起形成第二导电型的相关表面区域。另一个实施例则无需增加半导体基片的表面积就可以进一步增加去耦电容,该实施例的特征在于,电源线通过毗邻各电路块的导线线路而与一个焊接区相连接,第一导电型的层状区在该导线线路底下设有第二导电型的表面区,该表面区与导线线路相连接。
现在参照一些实施例和附图更详细地说明本发明的内容。附图中:
图1是本发明具有标准元件的集成电路的示意平面图;
图2示出了图1经过放大了的一部分;
图3是图2器件的一部分的剖面图;
图4是本发明第二实施例的集成电路的一部分的平面图。
应该指出的是,各附图仅仅是示意图,电路的各元件并没有按真实比例画出。
从图1-3的器件可以看到,CMOS集成电路1有一个例如硅或各种不同的适当的半导体材料制成的半导体基片2。半导体基片有一个基本上是第一导电型(在本实例中为P型)的层状区4,它毗邻着表面3。设在层状区4中的电路由标准元件组成。这类标准元件可以有各种不同的门电路,例如象倒相电路、“与”门、“或”门等之类的逻辑门,或象触发器之类的门电路,设计人员在设计集成电路过程中是可以从所谓程序库中选取到这些门电路的。本实例中各元件的高度(在Y方向上的尺寸)都相等,各元件的长度(在X方向上的尺寸)则取决于例如元件中各组件的数目,且可以彼此不同。各元件一个接一个地排列成行5而在X方向上延伸;各行依次在Y方向上配置,其长度可能不同。图1中所示出的行5其数目仅为三个,但实际的行数还要多得多。配线图形7呈导线线路的形式设在表面3上方,配线图形7与表面3之间为例如氧化硅之类的绝缘层6所间隔。配线图形除具有电源线(这下面即将进一步谈到)外,还有一些信号线供将电信号传送到各标准元件,并从一个标准元件传送到另一个标准元件,各信号线可能是在同一行上,也可能在另一行5上。各信号线7设在各行5之间的中间区8,该中间区只供敷设配线用,不含象晶体管之类的电路元件。在下面的叙述中,中间区8也叫配线通道或走线通道。图2中所示的电源线9和10工作时可加上正电压Vd或参考电压Vs,这些电源线也可以设在走线通道8中,但本实例中系配置在行5各标准元件的正上方。
各标准元件包括互补性MOS晶体管,图2中画出了这些晶体管中的P沟道MOST11和n沟道MOST12。晶体管11和12构成例如倒相器,输入信号加到倒相器互连的栅极电极上,输出信号则从倒相器互连的漏极上引出;晶体管11和12的源极分别接正电源线9和负电源线10。显然,图2中画出的元件中还可以包括其它电路元件。源极和漏极为P型的晶体管11设在其导电型与衬底4相反(因而为n型)的表面区13中。表面区13通常在文献中称之为“阱”或“穴”。源区和漏区为n型的n沟道MOST12可按周知的方式直接在P型衬底4上形成。
按照本发明(见图2),在标准元件各行5之间和配线7底下的是中间区的部位8,P型层状区或衬底4配备有一个或几个n型的附加表面区14,该区与电源线9电连接。该附加区14在图2中用点划线表示。由于这个区,衬底4与n型区域5之间的pn结所形成的附加大电容与电源9并联连接,在有大的局部电流峰值时起缓冲器的作用,从而减小了电源线9中电压的波动。表面区14可以在制造过程中在n型掺杂工序中形成。但出于制造工艺上的原因,区域14和阱13同时配置是有利的,这样,区域14与阱13的厚度和掺杂浓度就相同。区域14和阱13形成连续的n型区域,因而电源线9与区域14之间的连接是通过阱13进行的,而阱13由按一般方式在接触点16的部位与线19连接。
图1除示出了行5和走线通道8之外,还示出了许多焊接区17沿集成电路的周边配置,以供固定各导线之用。从图3的剖面图从左至右可以看到P沟道MOST11,其P型源极18和漏极19在n型区13中形成,且具有栅极20。源极18通过导线21接至电源线9,并通过电源接至n型阱13。漏极19则接至导线22,并通过导线22接至晶体管12的n型漏极(图3中未示出)。薄的栅极氧化物23将栅极20与晶体管隔开。从图3晶体管的右侧可以看到电源9与n型阱13之间的接线16,n型接触区域24处在场氧化物6的孔16中。于是n型阱13并入形成电源的额外去耦电容的附加n型区14中,如上面所述的那样。区14上覆盖有厚氧化层6,在氧化层6上或上方设有配线通道的导线线路7。
本发明的器件可按本技术领域的专业的人员熟知的一般方式制造,这里不再详述。在具体的实施例中,各标准元件的高度约为70微米,n型阱13的高度约为35微米。走线通道的宽度,即本实施例中行15之间的间距也约为70微米。将此附加区14填充到该间距中去,就可以使去耦电容实质上为标准阱的3倍。对于带有倒相器的标准元件(其长度即X方向上的尺寸,在本具体实施例中约为12.8微米),以上述方式提供了约为140fF的附加去耦电容。对于长约76.8微米的触发器元件提供了大845fF的额外去耦电容。这些大电容是在无需增加半导体基片表面积和无需改变工艺的前提下获取的。本发明的一个极其重要的方面是,去耦电容紧靠着电流传导电路元件配置,因而各元件在开关过程所产生的电流峰值实际上只是局部的,因而不影响或几乎不影响集成电路的其它部分。
图4是本发明集成电路第二实施例的一部分的示意图。图4中的各相应组件其编号与第一实施例中的一样。该集成电路也有许多标准元件行5,图中示出了其中三个。各行5彼此为走线通道8所隔开,为清楚起见,图中的配线没有画出来。各走线通道底下按前一实施例同样的方式形成有呈阱14的形式的去耦电容。
这些电容在图中是以连续的区域示出的,但显然并不是非如此不可的,各标准元件可以有独立的阱14。电源线9通过一个较宽的导线线路26与焊接区17相连接,导线线路26则基本上横切行5的纵向而在器件的表面上延伸。线路26可以在与导线线路9相同的配线层上形成,但往往是在不同的金属层上形成的。为进一步增加电源线的去耦合电容,在P型衬底的导线线路26底下增设了n型表面区27,图中以点划线表示。导线线路26在接触区28与区27相连接。区27可以形成单个的连续区,但也可将其如图中所示的那样再划分许多分区,各分区与导线线路26相连接。区27可与区14同时制造,并和各元件的n型阱同时制造。由于线路26底下的空间并不供设置开关元件用,因而可以上述方式进一步增加去耦电容而无需将电路扩大,这一点很重要。
显然,本发明并不局限于上述实施例,在不脱离本发明范围的前提下,熟悉本技术领域的人士是可以对上述实施例进行种种修改的。例如,可以将所述实例中的导电型互换,使衬底4为n型,阱13和附加区为P型。于是衬底与区13、14之间电压的极性当然也应相应对调。除MOS晶体管外,电路中还可以包括各种不同的电路元件,例如双极晶体管、电阻器、电容器、二极管等等。本发明既适用于数字电路也适用于模拟电路,还适用于具有模拟/数字混合功能的情况。本发明并不局限于含标准元件的电路,而且还可用于带定制的布线单元和在各布线单元间有走线通道的电路。
Claims (4)
1.一种CMOS集成电路,该集成电路有一个半导体基片,该基片有一个基本上是第一导电型并毗邻一个表面的层状区,层状区中设有电路,该电路至少具有两个毗邻的电路块,它们被一个中间区所分隔,并且该电路特别地但并非绝对地由成排的标准元件所构成,该电路块由沟道是第二导电型的MOS晶体管和沟道是第一导电型的MOS晶体管组成,前一种MOS晶体管设在第一导电型层状区中,后一种MOS晶体管设在第二导电型的表面区(以下称之为第一表面区)中,该表面上覆有电绝缘层,电绝缘层上形成有配线图形,该配线图形由设在中间区上方的电源线和一条或多条信号线组成,其特征在于,第一导电型层状区在各信号线底下的中间区部分另外配备有一个或多个第二导电型表面区,该表面区与电源线相连接,所述电源线通过毗邻各电路块的一个导线线路与一个焊接区相连接,所述第一导电型的层状区在该导线线路底下设有第二导电型的表面区,该表面区与该导线线路相连接。
2.如权利要求1所述的CMOS集成电路,其特征在于,所述另设的表面区的厚度和掺杂浓度与设有带第一导电型通道的MOS晶体管的第一表面区相同。
3.如权利要求2所述的CMOS集成电路,其特征在于,至少其中一个所述另设的表面区与至少其中一个所述第一表面区一起形成第二导电型的相关表面区域。
4.如上述任一权利要求所述的CMOS集成电路,其特征在于,所述层状区为P导电型,所述第一表面区和另设的表面区为n导电型。
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CN93101887A Expired - Fee Related CN1033116C (zh) | 1992-02-27 | 1993-02-24 | 互补金属氧化物半导体集成电路 |
Country Status (8)
Country | Link |
---|---|
US (1) | US5444288A (zh) |
EP (1) | EP0558133B1 (zh) |
JP (1) | JPH06132481A (zh) |
KR (1) | KR930018718A (zh) |
CN (1) | CN1033116C (zh) |
AT (1) | ATE154726T1 (zh) |
CA (1) | CA2090265A1 (zh) |
DE (1) | DE69311596T2 (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5656834A (en) * | 1994-09-19 | 1997-08-12 | Philips Electronics North America Corporation | IC standard cell designed with embedded capacitors |
US5887004A (en) * | 1997-03-28 | 1999-03-23 | International Business Machines Corporation | Isolated scan paths |
US7587044B2 (en) | 1998-01-02 | 2009-09-08 | Cryptography Research, Inc. | Differential power analysis method and apparatus |
ATE429748T1 (de) * | 1998-01-02 | 2009-05-15 | Cryptography Res Inc | Leckresistentes kryptographisches verfahren und vorrichtung |
CA2333095C (en) | 1998-06-03 | 2005-05-10 | Cryptography Research, Inc. | Improved des and other cryptographic processes with leak minimization for smartcards and other cryptosystems |
ATE360866T1 (de) | 1998-07-02 | 2007-05-15 | Cryptography Res Inc | Leckresistente aktualisierung eines indexierten kryptographischen schlüssels |
EP1104938A1 (fr) * | 1999-12-03 | 2001-06-06 | EM Microelectronic-Marin SA | Circuit intégré basse puissance ayant des capacité de découplage |
KR100351452B1 (ko) * | 1999-12-30 | 2002-09-09 | 주식회사 하이닉스반도체 | 디커플링 커패시터 구조를 갖는 반도체소자 |
JP2002083873A (ja) * | 2000-07-14 | 2002-03-22 | Internatl Business Mach Corp <Ibm> | 埋め込みデカップリング・キャパシタを有する半導体デバイス |
JP3526450B2 (ja) * | 2001-10-29 | 2004-05-17 | 株式会社東芝 | 半導体集積回路およびスタンダードセル配置設計方法 |
JP4205662B2 (ja) * | 2004-12-28 | 2009-01-07 | パナソニック株式会社 | 半導体集積回路の設計方法 |
US20080043406A1 (en) * | 2006-08-16 | 2008-02-21 | Secure Computing Corporation | Portable computer security device that includes a clip |
US10733352B2 (en) * | 2017-11-21 | 2020-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit and layout method for standard cell structures |
CN116110882B (zh) * | 2023-04-13 | 2023-09-15 | 长鑫存储技术有限公司 | 半导体结构 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54157092A (en) * | 1978-05-31 | 1979-12-11 | Nec Corp | Semiconductor integrated circuit device |
JPS56103448A (en) * | 1980-01-21 | 1981-08-18 | Hitachi Ltd | Semiconductor ic device |
CA1204511A (en) * | 1983-01-28 | 1986-05-13 | Storage Technology Partners | Cmos integrated circuit with high frequency power bus arrangement |
JPS6030170A (ja) * | 1983-07-29 | 1985-02-15 | Hitachi Ltd | 高集積読み出し専用メモリ |
US4833521A (en) * | 1983-12-13 | 1989-05-23 | Fairchild Camera & Instrument Corp. | Means for reducing signal propagation losses in very large scale integrated circuits |
JPS60233838A (ja) * | 1984-05-02 | 1985-11-20 | Toshiba Corp | 半導体集積回路装置 |
JPH079977B2 (ja) * | 1987-02-10 | 1995-02-01 | 株式会社東芝 | 半導体集積回路装置 |
JPH02210849A (ja) * | 1989-02-09 | 1990-08-22 | Matsushita Electron Corp | 半導体装置 |
-
1993
- 1993-02-19 DE DE69311596T patent/DE69311596T2/de not_active Expired - Fee Related
- 1993-02-19 EP EP93200478A patent/EP0558133B1/en not_active Expired - Lifetime
- 1993-02-19 AT AT93200478T patent/ATE154726T1/de not_active IP Right Cessation
- 1993-02-24 CA CA002090265A patent/CA2090265A1/en not_active Abandoned
- 1993-02-24 KR KR1019930002567A patent/KR930018718A/ko not_active Application Discontinuation
- 1993-02-24 CN CN93101887A patent/CN1033116C/zh not_active Expired - Fee Related
- 1993-02-25 JP JP5063517A patent/JPH06132481A/ja not_active Withdrawn
-
1994
- 1994-07-01 US US08/270,091 patent/US5444288A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5444288A (en) | 1995-08-22 |
CN1076549A (zh) | 1993-09-22 |
KR930018718A (ko) | 1993-09-22 |
EP0558133B1 (en) | 1997-06-18 |
JPH06132481A (ja) | 1994-05-13 |
DE69311596T2 (de) | 1998-01-02 |
DE69311596D1 (de) | 1997-07-24 |
ATE154726T1 (de) | 1997-07-15 |
CA2090265A1 (en) | 1993-08-28 |
EP0558133A1 (en) | 1993-09-01 |
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