CN103326722A - Self-adaption sample value estimating circuit and method - Google Patents

Abstract

The invention provides a self-adaption sample value estimating circuit and method. The circuit comprises a phase error detection module, a noise removing module, a digital control vibration module and a sample value estimating module, wherein the phase error detection module is used for figuring out a phase error U(k)according to an estimated sample value y(k)of an output signal of an ADC circuit and sending the U(k)to the noise removing module, k is larger than or equal to zero and is an integer, the noise removing module is used for filtering high-frequency noise components in the U(k), obtaining a stable phase error W(k)and sending the W(k)to the digital control vibration module, the digital control vibration module is used for figuring out an integer estimated pointer mk and a decimal estimated pointed Mu k according to the W(k)and sending the mk and the Mu k to the sample value estimating module, and the sample value estimating module is used for locating the output signal, participating in sample value estimation, of the ADC circuit according to the mk, determining the coefficient of the output signal according to the Mu k, utilizing the output signal to obtain an estimated sample value y(k) and sending the y(k)to the phase error detection module. According to the self-adaption sample value estimating circuit and method, the frequency error and the phase error of the signal output by the ADC sampling circuit are reduced.

Description

A kind of self adaptation sample value estimating circuit and method

Technical field

The present invention relates to the error concealment field of analog to digital conversion circuit sampled signal, relate in particular to a kind of self adaptation sample value estimating circuit and method.

Background technology

Using in (DWDM) transmission system based on the intensive multiplexed optical wave of palarization multiplexing difference quadrature phase shift keying (PM-DQPSK), signal is through the transmission of long distance and be subject to dispersion (CD), the impact of polarization mode dispersion (PMD) changes, thus the light signal gross distortion that causes receiving terminal to receive.Therefore, receiving terminal is carrying out light signal after photoelectric conversion module is converted to the signal of telecommunication, needs that also the signal of telecommunication is carried out filtering etc. and processes the correct reception that could realize information.

In Electric signal processing, Digital Signal Processing is one of processing means of commonly using, before Digital Signal Processing, need to utilize analog-to-digital conversion ADC sample circuit, but in the process of ADC sampling, because the ADC sampling clock is local oscillations, the signal that receives with ADC exists certain frequency error and phase error, if these errors are not realized adjusting, in the situation that constantly accumulation of error will directly cause the information of back to receive mistake.

In the prior art, receive frequency error and the phase error of signal for adjusting ADC sampled clock signal and ADC, usually the method that adopts is directly the ADC sampled clock signal to be adjusted, to reach the sampled clock signal effect synchronous with receiving signal, it realizes block diagram as shown in Figure 1, and ADC sample circuit output signal successively by phase error detection circuit, denoising circuit and Voltage-Controlled oscillation circuit VCO, is generated the ADC sampling clock, wherein, Voltage-Controlled oscillation circuit VCO is analog circuit.

The implementation method of above-mentioned sampling clock Circuit tuning generally has two kinds:

A kind of is that phase error detection circuit, denoising circuit and Voltage-Controlled oscillation circuit VCO are integrated in realizing on the chip piece.Because phase error detection circuit, denoising circuit are digital circuits, and Voltage-Controlled oscillation circuit VCO is analog circuit.In this digital analog mixed design, the noise jamming chance that analog circuit is subject to digital circuit is large, thereby the stability of whole chip is impacted.

Another kind is separately Voltage-Controlled oscillation circuit VCO to be made application-specific integrated circuit (ASIC) (Application Specified Integrated Circuit, ASIC), and namely the digital circuit with other separates realization.Although this scheme has reduced the interference of the digital circuit that VCO is subject to, and has additionally increased the design cost of whole sampling clock Circuit tuning and the complexity of circuit design.

Summary of the invention

For solving the problems of the technologies described above, the invention provides a kind of self adaptation sample value estimating circuit and method, to solve minimizing through the frequency error of the signal of ADC sample circuit output and the technical problem of phase error.

For solving the problems of the technologies described above, the invention provides a kind of self adaptation sample value estimating circuit, described circuit comprises phase error detection module, denoising module, digital control oscillation module and sample value estimation module, wherein,

Described phase error detection module, be used for calculating phase error U (k) according to the estimation sample value y (k) of analog-to-digital conversion (ADC) circuit output signal, and described phase error U (k) is sent to described denoising module, k is the integer more than or equal to 0;

Described denoising module is used for the high frequency noise components of the described phase error U of filtering (k), obtains stably phase error W (k), and with this stably phase error W (k) be sent to described digital control oscillation module;

Described digital control oscillation module is used for estimating pointer m according to described stably phase error W (k) computes integer _kEstimate pointer μ with decimal _k, and with described integer estimation pointer m _kEstimate pointer μ with decimal _kBe sent to described sample value estimation module;

Described sample value estimation module is used for estimating pointer m according to described integer _kThe location participates in the output signal of the described adc circuit of sample value estimation, estimates pointer μ according to decimal _kDetermine the coefficient of described output signal, utilize described output signal to obtain estimating sample value y (k), and should estimate that sample value y (k) was sent to described phase error detection module.

Further, described y (k) is the DQPSK signal of two-dimensional modulation

Further,

Described m _k=floor (W (k) * k), floor () expression rounds;

μ _k＝NCO _out(k)/W(k)；

NCO _out(k)＝[NCO _out(k-1)-W(k-1)]mod1；

NCO _out(0)＝0。

Further,

y(k)＝x(m _k+2)×C ₂(μ _k)+x(m _k+1)×C ₁(μ _k)+x(m _k)×C ₀(μ _k)+x(m _k-1)×C _-1(μ _k)；

$C_2\left({\mathrm{\μ}}_k\right)=\frac{1}{6}{\mathrm{\μ}}_k^3-\frac{1}{6}{\mathrm{\μ}}_k;$

$C_1\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{2}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="HDA0000144724870000021.png,HDA0000144724870000032.png"\; state="\{\{state\}\}">k</figure-callout>}}^2+{\mathrm{\&mu;}}_k;$

$C_0\left({\mathrm{\&mu;}}_k\right)=\frac{1}{2}{\mathrm{\&mu;}}_k^3-\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{2}{\mathrm{\&mu;}}_k+1;$

$C_{-1}\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{6}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{3}{\mathrm{\&mu;}}_k;$

Wherein, x (m _k+ 2), x (m _k+ 1), x (m _k), x (m _k-1) represents successively the m of adc circuit _k+ 2, m _k+ 1, m _kAnd m _k-1 output signal.

For solving the problems of the technologies described above, the present invention also provides a kind of self adaptation sample value method of estimation, and described method comprises:

Estimation sample value y (k) according to analog-to-digital conversion (ADC) circuit output signal calculates phase error U (k);

The high frequency noise components of the described phase error U of filtering (k) obtains stably phase error W (k);

Estimate pointer m according to described stably phase error W (k) computes integer _kEstimate pointer μ with decimal _k

Estimate pointer m according to described integer _kThe location participates in the output signal of the described adc circuit of sample value estimation, estimates pointer μ according to decimal _kDetermine the coefficient of described output signal, utilize described output signal to obtain estimating sample value y (k).

Further, be the DQPSK signal of two-dimensional modulation as y (k);

Further,

Described m _k=floor (W (k) * k), floor () expression rounds;

μ _k＝NCO _out(k)/W(k)；

NCO _out(k)＝[NCO _out(k-1)-W(k-1)]mod1。

Further,

y(k)＝x(m _k+2)×C ₂(μ _k)+x(m _k+1)×C ₁(μ _k)+x(m _k)×C ₀(μ _k)+x(m _k-1)×C _-1(μ _k)；

$C_2\left({\mathrm{\&mu;}}_k\right)=\frac{1}{6}{\mathrm{\&mu;}}_k^3-\frac{1}{6}{\mathrm{\&mu;}}_k;$

$C_1\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{2}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="HDA0000144724870000021.png,HDA0000144724870000032.png"\; state="\{\{state\}\}">k</figure-callout>}}^2+{\mathrm{\&mu;}}_k;$

$C_0\left({\mathrm{\&mu;}}_k\right)=\frac{1}{2}{\mathrm{\&mu;}}_k^3-\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{2}{\mathrm{\&mu;}}_k+1;$

$C_{-1}\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{6}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{3}{\mathrm{\&mu;}}_k;$

Wherein, x (m _k+ 2), x (m _k+ 1), x (m _k), x (m _k-1) represents successively the m of adc circuit _k+ 2, m _k+ 1, m _kAnd m _k-1 output signal.

Technique scheme no longer reduces frequency error and the phase error of the signal of exporting through the ADC sample circuit by adjusting the ADC sampling clock, but the signal through the output of ADC sample circuit is carried out frequency error and the phase error that the self adaptation sample value estimates to reduce the signal of exporting through the ADC sample circuit, whole self adaptation sample value estimating circuit is digital circuit, namely guarantee the stability of self adaptation sample value estimating circuit, also can not bring extra complexity for circuit design.

Description of drawings

Fig. 1 is the composition diagram of prior art sampling clock Circuit tuning;

Fig. 2 is the self adaptation sample value estimating circuit composition diagram of the present embodiment;

Fig. 3 is the electrical block diagram of the phase error detection module of the present embodiment;

Fig. 4 is the electrical block diagram of the denoising module of the present embodiment;

Fig. 5 is the electrical block diagram of the digital control oscillation module of the present embodiment;

Fig. 6 is the electrical block diagram of the sample value estimation module of the present embodiment;

Fig. 7 is the self adaptation sample value method of estimation flow chart of the present embodiment.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, hereinafter in connection with accompanying drawing embodiments of the invention are elaborated.Need to prove, in the situation that do not conflict, the embodiment among the application and the feature among the embodiment be combination in any mutually.

Fig. 2 is the self adaptation sample value estimating circuit composition diagram of the present embodiment.

This self adaptation sample value estimating circuit comprises phase error detection module, denoising module, digital control oscillation module and sample value estimation module, wherein,

The phase error detection module, be used for calculating phase error U (k) according to the estimation sample value y (k) of analog-to-digital conversion (ADC) circuit output signal, and described phase error U (k) is sent to described denoising module, k is the integer more than or equal to 0;

As, input estimates that sample value y (k) is the DQPSK signal of two-dimensional modulation,

Then $U\left(k\right)=I(k-\frac{1}{2})[I\left(k\right)-I(k-1)]+Q(k-\frac{1}{2})[Q\left(k\right)-Q(k-1)];$

Wherein, I, Q are respectively real part and the imaginary part of y (k); K,

K-1 is 3 continuous sampled point sequence numbers, and the electrical block diagram of this phase error detection module as shown in Figure 3.

There is not phase error, namely during the signal Complete Synchronization of ADC sampling clock and input ADC, if the polarity of sample value of the signal of input ADC changes, intermediate samples point then

With

Should be zero; If the polarity of the sample value of the signal of input ADC does not change, then [I (k)-I (k-1)] and [Q (k)-Q (k-1)] should be zero.Therefore, no matter how sample value changes, when not having phase error, the output U (k) of phase error detection circuit is zero.Otherwise when there was phase difference in the sample value of signal of sampling clock and input ADC, then the output U (k) of phase error detection circuit was non-vanishing.The size of U (k) absolute value represents the size of phase error, the direction of its symbolic representation phase error.

The denoising module is used for the high frequency noise components of the described phase error U of filtering (k), obtains stably phase error W (k), and with this stably phase error W (k) be sent to described digital control oscillation module;

Obtaining of phase error W (k) can be realized by following formula stably:

X _p(k)＝w ₁·U(k)；

X _i(k)＝w ₂·U(k)+X _i(k-1)；

W(k)＝X _p(k)+X _i(k)；

w ₁Be proportional gain, w ₂Be storage gain w ₂

X _p(k) expression proportional path, it is by phase error U (k) and proportional gain w ₁Multiplying each other obtains, and is used for the control self adaptation sample value estimating circuit phase error amplitude of accommodation each time.Such as: in the ideal case, if there is not phase error, i.e. U (k)=0, then proportional path X _p(k)=0, the phase error amplitude of accommodation of self adaptation sample value estimating circuit is zero.Along with proportional path X _p(k) increase, the phase error amplitude of accommodation also increases.

X _i(k) expression path of integration, it is cumulative errors.Since the current cumulative errors that obtain be prime cumulative errors and error current and, so even if error current and prime error have larger difference, react in the fluctuation of current cumulative errors value also less, namely obtain a stably phase error.

The electrical block diagram of denoising module as shown in Figure 4.

Digital control oscillation module is used for estimating pointer m according to described stably phase error W (k) computes integer _kEstimate pointer μ with decimal _k, and with described integer estimation pointer m _kEstimate pointer μ with decimal _kBe sent to described sample value estimation module;

When y (k) is the DQPSK signal of two-dimensional modulation,

Integer is estimated pointer m _kEstimate pointer μ with decimal _kCan obtain according to following formula:

m _k=floor (W (k) * k), floor () expression rounds;

μ _k＝NCO _out(k)/W(k)；

NCO _out(k)＝[NCO _out(k-1)-W(k-1)]mod1。

NCO _out(0)＝0。

From NCO _Out(k) see NCO on the computing formula _Out(k) be equivalent to a phase register, wherein the value of register is constantly adjusted according to W (k-1).Work as NCO _Out(k) be at 0 o'clock, there is not phase error in corresponding sampled point, at this moment the sampling clock of ADC and the signal Complete Synchronization of inputting ADC.

The electrical block diagram of digital control oscillation module as shown in Figure 5.

The sample value estimation module is used for estimating pointer m according to described integer _kThe location participates in the output signal of the adc circuit of sample value estimation, estimates pointer μ according to decimal _kDetermine the coefficient of described output signal, utilize described output signal to carry out sample value and estimate, obtain estimating sample value y (k), and the sample value y (k) that estimates is sent to described phase error detection module.

When y (k) is the DQPSK signal of two-dimensional modulation,

y(k)＝x(m _k+2)×C ₂(μ _k)+x(m _k+1)×C ₁(μ _k)+x(m _k)×C ₀(μ _k)+x(m _k-1)×C _-1(μ _k)；

$C_2\left({\mathrm{\&mu;}}_k\right)=\frac{1}{6}{\mathrm{\&mu;}}_k^3-\frac{1}{6}{\mathrm{\&mu;}}_k;$

$C_1\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{2}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="HDA0000144724870000021.png,HDA0000144724870000032.png"\; state="\{\{state\}\}">k</figure-callout>}}^2+{\mathrm{\&mu;}}_k;$

$C_0\left({\mathrm{\&mu;}}_k\right)=\frac{1}{2}{\mathrm{\&mu;}}_k^3-\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{2}{\mathrm{\&mu;}}_k+1;$

$C_{-1}\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{6}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{3}{\mathrm{\&mu;}}_k;$

Wherein, x (m _k+ 2), x (m _k+ 1), x (m _k), x (m _k-1) represents successively the m of adc circuit _k+ 2, m _k+ 1, m _kAnd m _k-1 output signal.

The electrical block diagram of sample value estimation module as shown in Figure 6.

The output y (k) of sample value estimation module has eliminated frequency and the phase error of this sampled signal with respect to the sampled signal through adc circuit output, and y (k) is the sampled value that follow-up Digital Signal Processing needs.

Fig. 7 is the self adaptation sample value method of estimation flow chart of the present embodiment.

S701 calculates phase error U (k) according to the estimation sample value y (k) of analog-to-digital conversion (ADC) circuit output signal;

When y (k) is the DQPSK signal of two-dimensional modulation,

$U\left(k\right)=I(k-\frac{1}{2})[I\left(k\right)-I(k-1)]+Q(k-\frac{1}{2})[Q\left(k\right)-Q(k-1)];$

Wherein, I, Q are respectively real part and the imaginary part of y (k); K,

K-1 is 3 continuous sampled point sequence numbers;

The high frequency noise components of the described phase error U of S702 filtering (k) obtains stably phase error W (k);

S703 estimates pointer m according to described stably phase error W (k) computes integer _kEstimate pointer μ with decimal _k

When y (k) is the DQPSK signal of two-dimensional modulation,

Described m _k=floor (W (k) * k), floor () expression rounds;

μ _k＝NCO _out(k)/W(k)；

NCO _out(k)＝[NCO _out(k-1)-W(k-1)]mod1。

S704 estimates pointer m according to described integer _kThe location participates in the output signal of the described adc circuit of sample value estimation, estimates pointer μ according to decimal _kDetermine the coefficient of described output signal, utilize described output signal to obtain estimating sample value y (k);

When y (k) is the DQPSK signal of two-dimensional modulation,

y(k)＝x(m _k+2)×C ₂(μ _k)+x(m _k+1)×C ₁(μ _k)+x(m _k)×C ₀(μ _k)+x(m _k-1)×C _-1(μ _k)；

$C_2\left({\mathrm{\&mu;}}_k\right)=\frac{1}{6}{\mathrm{\&mu;}}_k^3-\frac{1}{6}{\mathrm{\&mu;}}_k;$

$C_1\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{2}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="HDA0000144724870000021.png,HDA0000144724870000032.png"\; state="\{\{state\}\}">k</figure-callout>}}^2+{\mathrm{\&mu;}}_k;$

$C_0\left({\mathrm{\&mu;}}_k\right)=\frac{1}{2}{\mathrm{\&mu;}}_k^3-\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{2}{\mathrm{\&mu;}}_k+1;$

$C_{-1}\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{6}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{3}{\mathrm{\&mu;}}_k;$

Wherein, x (m _k+ 2), x (m _k+ 1), x (m _k), x (m _k-1) represents successively the m of adc circuit _k+ 2, m _k+ 1, m _kAnd m _k-1 output signal.

One of ordinary skill in the art will appreciate that all or part of step in the said method can come the instruction related hardware to finish by program, described program can be stored in the computer-readable recording medium, such as read-only memory, disk or CD etc.Alternatively, all or part of step of above-described embodiment also can realize with one or more integrated circuits, and correspondingly, each the module/unit in above-described embodiment can adopt the form of hardware to realize, also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.

Need to prove; the present invention also can have other various embodiments; in the situation that do not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.

Claims (8)

1. a self adaptation sample value estimating circuit is characterized in that, described circuit comprises phase error detection module, denoising module, digital control oscillation module and sample value estimation module, wherein,

Described phase error detection module, be used for calculating phase error U (k) according to the estimation sample value y (k) of analog-to-digital conversion (ADC) circuit output signal, and described phase error U (k) is sent to described denoising module, k is the integer more than or equal to 0;

Described denoising module is used for the high frequency noise components of the described phase error U of filtering (k), obtains stably phase error W (k), and with this stably phase error W (k) be sent to described digital control oscillation module;

Described digital control oscillation module is used for estimating pointer m according to described stably phase error W (k) computes integer _kEstimate pointer μ with decimal _k, and with described integer estimation pointer m _kEstimate pointer μ with decimal _kBe sent to described sample value estimation module;

Described sample value estimation module is used for estimating pointer m according to described integer _kThe location participates in the output signal of the described adc circuit of sample value estimation, estimates pointer μ according to decimal _kDetermine the coefficient of described output signal, utilize described output signal to obtain estimating sample value y (k), and should estimate that sample value y (k) was sent to described phase error detection module.

2. self adaptation sample value estimating circuit as claimed in claim 1 is characterized in that,

Described y (k) is the DQPSK signal of two-dimensional modulation.

3. self adaptation sample value estimating circuit as claimed in claim 2 is characterized in that:

Described m _k=floor (W (k) * k), floor () expression rounds;

μ _k＝NCO _out(k)/W(k)；

NCO _out(k)＝[NCO _out(k-1)-W(k-1)]mod1；

NCO _out(0)＝0。

4. self adaptation sample value estimating circuit as claimed in claim 2 or claim 3 is characterized in that:

y(k)＝x(m _k+2)×C ₂(μ _k)+x(m _k+1)×C ₁(μ _k)+x(m _k)×C ₀(μ _k)+x(m _k-1)×C _-1(μ _k)；

$C_2\left({\mathrm{\&mu;}}_k\right)=\frac{1}{6}{\mathrm{\&mu;}}_k^3-\frac{1}{6}{\mathrm{\&mu;}}_k;$

$C_1\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{2}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_k^2+{\mathrm{\&mu;}}_k;$

$C_0\left({\mathrm{\&mu;}}_k\right)=\frac{1}{2}{\mathrm{\&mu;}}_k^3-\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{2}{\mathrm{\&mu;}}_k+1;$

$C_{-1}\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{6}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{3}{\mathrm{\&mu;}}_k;$

Wherein, x (m _k+ 2), x (m _k+ 1), x (m _k), x (m _k-1) represents successively the m of adc circuit _k+ 2, m _k+ 1, m _kAnd m _k-1 output signal.

5. a self adaptation sample value method of estimation is characterized in that, described method comprises:

Estimation sample value y (k) according to analog-to-digital conversion (ADC) circuit output signal calculates phase error U (k);

The high frequency noise components of the described phase error U of filtering (k) obtains stably phase error W (k);

Estimate pointer m according to described stably phase error W (k) computes integer _kEstimate pointer μ with decimal _k

Estimate pointer m according to described integer _kThe location participates in the output signal of the described adc circuit of sample value estimation, estimates pointer μ according to decimal _kDetermine the coefficient of described output signal, utilize described output signal to obtain estimating sample value y (k).

6. method as claimed in claim 5 is characterized in that,

Described y (k) is the DQPSK signal of two-dimensional modulation.

7. method as claimed in claim 6 is characterized in that,

Described m _k=floor (W (k) * k), floor () expression rounds;

μ _k＝NCO _out(k)/W(k)；

NCO _out(k)＝[NCO _out(k-1)-W(k-1)]mod1。

8. such as claim 6 or 7 described methods, it is characterized in that,

y(k)＝x(m _k+2)×C ₂(μ _k)+x(m _k+1)×C ₁(μ _k)+x(m _k)×C ₀(μ _k)+x(m _k-1)×C _-1(μ _k)；

$C_2\left({\mathrm{\&mu;}}_k\right)=\frac{1}{6}{\mathrm{\&mu;}}_k^3-\frac{1}{6}{\mathrm{\&mu;}}_k;$

$C_1\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{2}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_k^2+{\mathrm{\&mu;}}_k;$

$C_0\left({\mathrm{\&mu;}}_k\right)=\frac{1}{2}{\mathrm{\&mu;}}_k^3-\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{2}{\mathrm{\&mu;}}_k+1;$

$C_{-1}\left({\mathrm{\&mu;}}_k\right)=-\frac{1}{6}{\mathrm{\&mu;}}_k^3+\frac{1}{2}{\mathrm{\&mu;}}_k^2-\frac{1}{3}{\mathrm{\&mu;}}_k;$

Wherein, x (m _k+ 2), x (m _k+ 1), x (m _k), x (m _k-1) represents successively the m of adc circuit _k+ 2, m _k+ 1, m _kAnd m _k-1 output signal.

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