CN103338174B - A kind of generating means of transponder data clock - Google Patents
A kind of generating means of transponder data clock Download PDFInfo
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- CN103338174B CN103338174B CN201310257643.XA CN201310257643A CN103338174B CN 103338174 B CN103338174 B CN 103338174B CN 201310257643 A CN201310257643 A CN 201310257643A CN 103338174 B CN103338174 B CN 103338174B
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- division counter
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Abstract
The invention discloses a kind of generating means of transponder data clock, comprise FPGA; FPGA is loaded with judging module, frequency division counter module and clock output module.The counting clock of the present invention using binary FSK signal as frequency division counter module, dynamic frequency division is realized by the count range adjusting frequency division counter module in conjunction with transponder message data dynamically, the data clock of stable 564KHz can be extracted from fsk signal, read the transponder message data in memory with this.Therefore data clock generating means of the present invention also can reduce the power consumption of whole transponder while reducing hardware spending.
Description
Technical field
The invention belongs to railway system's control technology field, be specifically related to a kind of generating means of transponder data clock.
Background technology
BisexualArtemiapopulations from China (ChineseTrainControlSystem, CTCS) standard is with reference to European Train Control System (EuropeanTrainControlSystem, ETCS) formulate, in this standard, railway transponder, as the key component of train operation control system, makes the automaticity of train control system improve further.The effect of railway transponder in locomotive monitoring equipment has: the absolute hi-Fix (precision can reach+1 meter) that can realize train, and without the need to manual intervention, the security incident that human error is caused reduces to minimum; Can to train transmitting line longitudinal data, bridge tunnel positional information, circuit speed-limiting messages, even temporary speed limitation information; Also the information of trackside electronic unit can be passed to train etc. fast.
The operation principle of transponder is: when train arrives ground transponder efficient working range, be that the vehicle-mounted power antenna of 27.095MHz activates transponder by the frequency be installed on bottom train, transponder starts to provide running information to train.These information are referred to as transponder message, by FSK(Frequency-shiftkeying, frequency shift keying) send after modulation; The correct traffic safety that reliably directly decide train of transponder message as can be seen here, and can the correctness of transponder data clock frequency directly determine transponder message and be correctly sent.
This railway transponder technology for a long time by external signal company of state (such as Siemens, Alstom etc.) monopolization, thus causes transponder expensive.Along with the develop rapidly of railway construction in China, be badly in need of the railway transponder with Intellectual Property in China.Needed for general construction circuit, mobile unit and transponder will spend tens million of RMB, and the transponder of independent research, can better for the development of China railways cause be contributed while saving a large amount of foreign exchange for China.
In transponder national standard (CTCS), two frequencies of the fsk signal that clear stipulaties transponder adopts are: 4.512MHz and 3.948MHz, and the data transfer rate of message is 564kbps.The energy obtained by electromagnetic coupled due to transponder is very limited, and the power consumption of whole transponder is just very strict.Generation at present about data clock mainly contains two kinds of methods: the first is the clock being produced 564KHz by high-frequency crystal oscillation fractional frequency, but the energy that crystal oscillator consumption rate is more, and this also becomes the maximum shortcoming of this technology.
Publication number is that the Chinese patent of CN101364816 discloses another kind of transponder technology, and its signal by the 27.095MHz in power antenna carries out the data clock that 48 frequency divisions obtain 564KHz; This technology does not need extra crystal oscillator, greatly saves power consumption, but will carry out 48 frequency divisions after all, and hardware spending and power consumption are still larger.
Summary of the invention
For the above-mentioned technical problem existing for prior art, the invention provides a kind of generating means of transponder data clock, while reducing hardware spending, also can reduce the power consumption of whole transponder.
A generating means for transponder data clock, comprises FPGA(field programmable gate array), described FPGA is loaded with judging module, frequency division counter module and clock output module; Wherein:
Described judging module, for receiving the message data of transponder, generates the count range of frequency division counter module according to described message data;
Described frequency division counter module is used for using fsk signal as counting clock, counts in described count range;
Described clock output module is used for frequency division counter module to export the highest order of count results as transponder data clock and exports.
Described judging module generates the count range of frequency division counter module process according to message data is as follows:
When frequency division counter module using fsk signal rising edge or trailing edge under the prerequisite of counting clock, if the message data that judging module receives is 1, then judging module export count range be 0 ~ 6; If the message data that judging module receives is 0, then the count range that judging module exports is 0 ~ 7;
When frequency division counter module using fsk signal rising edge and trailing edge jointly as under the prerequisite of counting clock, if the message data that judging module receives is 1, then the count range that judging module exports is 0 ~ 13; If the message data that judging module receives is 0, then the count range that judging module exports is 0 ~ 15.
Described judging module receives the count results that frequency division counter module exports, if count results reaches the maximum of count range, then after described count results being reset, frequency division counter module is counted again.
Described frequency division counter module adopts 3 digit counters or 4 digit counters; If using fsk signal rising edge or trailing edge as counting clock, then frequency division counter module adopts 3 digit counters; If using fsk signal rising edge and trailing edge jointly as counting clock, then frequency division counter module adopts 4 digit counters.
The present invention analyzes the fsk signal frequency (4.512MHz or 3.948MHz) and data rate (564kbps that specify in transponder relevant criterion, corresponding read data clock is 564KHz) find, fsk signal frequency is about 7 times (3.948MHz/564KHz) or 8 times (4.512MHz/564KHz) of data rate.With the counting clock of fsk signal as frequency division counter module, dynamic frequency division is realized by the count range producing frequency counter in conjunction with transponder message data dynamically, the data clock of stable 564KHz can be extracted from fsk signal, read the transponder message data in memory with this.
The present invention is the counting clock using the fsk signal of lower frequency as frequency counter, so the present invention at most only needs to carry out the 564KHz data clock that 16 frequency divisions (needs 4 frequency counters) can be met the requirement of transponder relevant criterion.Signal with respect to the 27.095MHz in power antenna carries out the method that 48 frequency divisions (needing 6 frequency counters) obtain the data clock of 564KHz, and data clock generating means of the present invention also can reduce the power consumption of whole transponder while reducing hardware spending.
Accompanying drawing explanation
Fig. 1 is the structural representation of generating means of the present invention.
Fig. 2 be with binary FSK signal rising edge for frequency division counter building block technique clock time, the simulation result under simulation software Modelsim.
Fig. 3 be with binary FSK signal trailing edge for frequency division counter building block technique clock time, the simulation result under simulation software Modelsim.
Fig. 4 be simultaneously with binary FSK signal rising edge and trailing edge for frequency division counter building block technique clock time, the simulation result under simulation software Modelsim.
Embodiment
In order to more specifically describe the present invention, below in conjunction with the drawings and the specific embodiments, technical scheme of the present invention and relative theory thereof are described in detail.
As shown in Figure 1, a kind of generating means of transponder data clock, comprises FPGA, and FPGA is loaded with judging module, frequency division counter module and clock output module; Judging module, frequency division counter module and clock output module all by passing through program code programming realization under FPGA platform; Wherein:
Judging module is used for from external memory storage, read the message data receiving transponder, generates the count range of frequency division counter module according to message data; Concrete operations code is as follows:
When frequency division counter module is using fsk signal rising edge or trailing edge as counting clock, if the message data that judging module receives is 1, then the count range that judging module exports is 0 ~ 6; If the message data that judging module receives is 0, then the count range that judging module exports is 0 ~ 7;
When frequency division counter module using fsk signal rising edge and trailing edge jointly as counting clock, if the message data that judging module receives is 1, then the count range that judging module exports is 0 ~ 13; If the message data that judging module receives is 0, then the count range that judging module exports is 0 ~ 15.
Frequency division counter module is used for, using the fsk signal of outside FSK oscillator generation as counting clock, counting in the count range that judging module generates; In present embodiment, if using fsk signal rising edge or trailing edge as counting clock, then frequency division counter module adopts 3 digit counters; If using fsk signal rising edge and trailing edge jointly as counting clock, then frequency division counter module adopts 4 digit counters.
The count results exported when frequency division counter module reaches the maximum of count range, and judging module makes frequency division counter module again count after then this count results being reset.
Clock output module is used for frequency division counter module to export the highest order of count results as transponder data clock and exports to peripheral storage.
In present embodiment, frequency division counter module is using binary FSK signal rising edge as counting clock; So this frequency division counter module is 3 digit counters, judging module root transponder message data produces the count range of frequency division counter module, if transponder message data is " 1 ", frequency division counter module count down to 6 from 0, if transponder message data is " 0 ", frequency division counter module count down to 7 from 0; Last using the result of frequency division counter module the 3rd as the data clock extracted.As shown in Figure 2, can find out that frequency division counter module adds 1 at each binary FSK signal rising edge.The data clock rate finally extracted is 564KHz, meets the requirement of transponder.
Frequency division counter module also can binary FSK signal trailing edge as counting clock, this frequency division counter module is also 3 digit counters, judging module root transponder message data adjudicates the count range of frequency division counter module, if transponder message data is " 1 ", frequency division counter module count down to 6 from 0, if transponder message data is " 0 ", frequency division counter module count down to 7 from 0; Last using the result of frequency division counter module the 3rd as the data clock extracted.As shown in Figure 3, can find out that frequency division counter module adds 1 at each binary FSK signal trailing edge.The data clock rate finally extracted is 564KHz, meets the requirement of transponder.
If frequency division counter module is simultaneously using binary FSK signal rising edge and trailing edge as counting clock, so this frequency division counter module is 4 digit counters, judging module root transponder message data adjudicates the count range of frequency division counter module, if transponder message data is " 1 ", frequency division counter module count down to 13 from 0, if transponder message data is " 0 ", frequency division counter module count down to 15 from 0; Last using the result of frequency division counter module the 4th as the data clock extracted.As shown in Figure 4, can find out that frequency division counter module adds 1 at each binary FSK signal rising edge and trailing edge.The data clock rate finally extracted is 564KHz, also meets the requirement of transponder.
Present embodiment is by analyzing the fsk signal frequency (4.512MHz or 3.948MHz) and data rate (564kbps that specify in transponder relevant criterion, corresponding read data clock is 564KHz) find, fsk signal frequency is about 7 times (3.948MHz/564KHz) or 8 times (4.512MHz/564KHz) of data rate.Therefore utilize fsk signal as the counting clock of frequency division counter module, dynamic frequency division is realized by the count range producing frequency counter in conjunction with transponder message data dynamically, the data clock of stable 564KHz can be extracted from fsk signal, read the transponder message data in memory with this.
The counting clock of present embodiment using the fsk signal of lower frequency as frequency division counter module, so only need at most to carry out the 564KHz data clock that 16 frequency divisions (needs 4 frequency counters) can be met the requirement of transponder relevant criterion.Signal with respect to the 27.095MHz in power antenna carries out the method that 48 frequency divisions (needing 6 frequency counters) obtain the data clock of 564KHz, and the data clock generating means of present embodiment also can reduce the power consumption of whole transponder while reducing hardware spending.
Claims (1)
1. a generating means for transponder data clock, comprises FPGA; It is characterized in that: described FPGA is loaded with judging module, frequency division counter module and clock output module; Wherein:
Described judging module, for receiving the message data of transponder, generates the count range of frequency division counter module according to described message data;
Described frequency division counter module is used for using fsk signal as counting clock, counts in described count range;
Described clock output module is used for frequency division counter module to export the highest order of count results as transponder data clock and exports;
When frequency division counter module using fsk signal rising edge or trailing edge under the prerequisite of counting clock, if the message data that judging module receives is 1, then judging module export count range be 0 ~ 6; If the message data that judging module receives is 0, then the count range that judging module exports is 0 ~ 7;
When frequency division counter module using fsk signal rising edge and trailing edge jointly as under the prerequisite of counting clock, if the message data that judging module receives is 1, then the count range that judging module exports is 0 ~ 13; If the message data that judging module receives is 0, then the count range that judging module exports is 0 ~ 15;
Described judging module receives the count results that frequency division counter module exports, if count results reaches the maximum of count range, then after described count results being reset, frequency division counter module is counted again;
Described frequency division counter module adopts 3 digit counters or 4 digit counters; If using fsk signal rising edge or trailing edge as counting clock, then frequency division counter module adopts 3 digit counters; If using fsk signal rising edge and trailing edge jointly as counting clock, then frequency division counter module adopts 4 digit counters.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5483193A (en) * | 1995-03-24 | 1996-01-09 | Ford Motor Company | Circuit for demodulating FSK signals |
| CN1313974A (en) * | 1998-06-22 | 2001-09-19 | 乔治·伦纳德·鲍威尔 | Anti-collision tag apparatus and system |
| CN101432758A (en) * | 2006-03-03 | 2009-05-13 | 威夫特伦德科技有限公司 | Apparatus and methods for electromagnetic identification |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5483193A (en) * | 1995-03-24 | 1996-01-09 | Ford Motor Company | Circuit for demodulating FSK signals |
| CN1313974A (en) * | 1998-06-22 | 2001-09-19 | 乔治·伦纳德·鲍威尔 | Anti-collision tag apparatus and system |
| CN101432758A (en) * | 2006-03-03 | 2009-05-13 | 威夫特伦德科技有限公司 | Apparatus and methods for electromagnetic identification |
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