CN103365976A

CN103365976A - Method for performing application-oriented test modification to circuit XDL level netlist description by using Perl (Practical Extraction and Reporting Language) and test method

Info

Publication number: CN103365976A
Application number: CN201310268650XA
Authority: CN
Inventors: 俞洋; 刘旺; 陈诚
Original assignee: Harbin Institute of Technology
Current assignee: Harbin Institute of Technology
Priority date: 2013-06-28
Filing date: 2013-06-28
Publication date: 2013-10-23
Anticipated expiration: 2033-06-28
Also published as: CN103365976B

Abstract

The invention discloses a method for performing application-oriented test modification to circuit XDL level netlist description by using Perl and a test method, and relates to a method for performing application-oriented test modification to circuit XDL level netlist description and a test method. The method for performing application-oriented test modification to circuit XDL level netlist description aims to solve the problems that the correctness and validity of a conventional method performing application-oriented test modification to the circuit XDL level netlist are poor. According to the method for performing the application-oriented test modification to the circuit XDL level netlist description and the test method, the XDL tool provided by the Xilinx is used for converting an NCD file into an XDL file, then the Perl suitable for text processing is used for modifying the XDL file, and finally the XDL file subjected to modification is converted into the NCD file through the XDL tool so as to obtain the final configuration file and achieve application-oriented test modification performed to the circuit XDL level netlist description. The method for performing application-oriented test modification to circuit XDL level netlist description and the test method are suitable for performing application-oriented test modification and test to the circuit XDL level netlist description.

Description

Use the Perl language that circuit XDL level net table is described and carry out application oriented test modifications method and method of testing

Technical field

The present invention relates to a kind of circuit XDL level net table is described and carry out application oriented test modifications method and method of testing.

Background technology

In general, the basic procedure of a FPGA design is divided into following a few step, as shown in Figure 1: in the above in several steps, by synthesis tool with the HDL language, the designs such as schematic diagram inputs translate into by with or, the logic gate such as non-is connected the logic that the basic logic unit such as trigger forms and is connected (net and show) with RAM, and according to target and the logic connection that is connected optimization to generate, thereby generate EDF file (EDA industrial standard file).Then carry out functional simulation, the function of checking design, after satisfying function, use (Implement) instrument of realization, the logic netlist of comprehensively output is translated into the hardware primitive of the bottom module of selected device, with design map to device architecture, carry out placement-and-routing, reach the purpose that realizes design at selected device.After this make design meet the requirements of temporal constraint by timing verification, generate at last the download programming file that can download to accordingly among the FPGA, realize chip programming.

Summary of the invention

The present invention carries out correctness and the poor problem of validity of application oriented test modifications in order to solve existing circuit XDL level net table is described, and carries out application oriented test modifications method thereby provide a kind of use Perl language that circuit XDL level net table is described.

Use the Perl language that circuit XDL level net table is described and carry out application oriented test modifications method, it is characterized in that: its method is:

The XDL instrument that uses Xilinx to provide is the XDL file with the NCD file conversion, then use the Perl language that is applicable to text-processing to revise the XDL file, by the XDL instrument amended XDL file is changed into the NCD file at last, obtain last configuration file, finish circuit XDL level net table described and carry out application oriented test modifications.

The XDL file is the readable documents of text formatting.

Using the Perl language that circuit XDL level net table is described carries out application oriented test modifications method and is specially:

Step 1, use ISE are readable XDL file with comprehensive rear net table NCD file conversion;

Step 2, Analysis of X DL file also extract the information of placement-and-routing, CLB configuration by the FPGAEditor instrument;

Step 3, make the user restraint file according to the information of placement-and-routing, that is: UCF file, the position of specifying CLB;

Step 4, circuit XDL level net table described make amendment, obtain finally to be used for the NCD file tested.

Based on the described use of said method Perl language circuit XDL level net table is described by the interconnecting test method of carrying out application oriented test modifications method,

The configuration of LUT in the circuit to be tested revised respectively help or logic complete with logical OR, and then realize interconnecting test.

Described interconnecting test method is specially:

The configuration of LUT in the circuit to be tested revised respectively helps and logic,

Use the XDL instrument that amended XDL file conversion is the NCD file, as the configuration file of test configurations for the first time in the interconnecting test;

Again the configuration of the LUT in the circuit to be tested is revised respectively and is helped or logic,

After having revised all LUT, convert the NCD file to, as the configuration file of the test configurations second time, and then circuit XDL level net table described carry out application oriented interconnecting test.

Based on use Perl language circuit XDL level net table is described by the logic test method that carries out application oriented test modifications method,

In untapped CLB, add test vector generator and response analysis device, and the output of test vector generator is connected to the input end of LUT to be measured, the output terminal of LUT is connected on the corresponding analysis device, and then circuit XDL level net table is described the programmable logic resource test of carrying out application oriented test modifications method.

LUT is for having n input end, and n is positive integer, and the method for circuit XDL level net table being described the programmable logic resource test of carrying out application oriented test modifications method is specially:

Adopt the counter of a n position as test vector generator, use the Verilog hardware design language to realize;

Being added in source code of counter added, and is specially:

To add in the source code with the module of Verilog code construction, and in former design code, increase a clock signal and a reset signal for counter;

Then compile comprehensively, counter is placed among the untapped slice; NCD file after comprehensive is converted into the XDL file, deletes the wiring of the input end of LUT to be measured;

Then by creating annexation, counter signals is connected on the LUT again, and revises the XDL file, create being connected between counter output and the LUT input end to be measured; And then realize circuit XDL level net table is described the programmable logic resource test of carrying out application oriented test modifications method.

The present invention has improved existing correctness and the validity of carrying out application oriented test modifications that circuit XDL level net table is described.

Description of drawings

Fig. 1 is the basic flow sheet of the FPGA design described in the background technology of the present invention;

Fig. 2 is the principle schematic of automatic PAR of the present invention;

Fig. 3 uses UCF to specify the principle schematic of slice position;

Fig. 4 is the principle schematic of adding counter;

Fig. 5 is the principle schematic of deletion LUT input end wiring;

Fig. 6 creates the catenation principle synoptic diagram between counter output and the LUT input;

Fig. 7 is the principle schematic that connects up between counter output and the LUT input;

Fig. 8 is the artificial circuit synoptic diagram;

Fig. 9 is the primary circuit Output rusults that fault is injected emulation;

Figure 10 is that 0 type fault Output rusults is fixed in the net4 injection of fault injection emulation;

Figure 11 is that 1 type fault Output rusults is fixed in the net4 injection of fault injection emulation;

Output rusults after the complete and configuration in the emulation of Figure 12 interconnecting test configuration;

Output rusults after the complete or configuration in the emulation of Figure 13 interconnecting test configuration;

" 0 " type fault Output rusults is fixed in detection on Figure 14 interconnection line in the fault detect;

" 1 " type fault Output rusults is fixed in detection on Figure 15 interconnection line in the fault detect;

Output rusults before fault in the test of Figure 16 FPGA (Field Programmable Gate Array) is injected;

Output rusults after fault in the test of Figure 17 FPGA (Field Programmable Gate Array) is injected.

Embodiment

Embodiment one, use Perl language are described circuit XDL level net table and are carried out application oriented test modifications method, and its method is:

Embodiment two, this embodiment and embodiment one described use Perl language are described the difference of carrying out application oriented test modifications method to circuit XDL level net table and are, use the Perl language that circuit XDL level net table is described and carry out application oriented test modifications method and be specially:

Step 2, Analysis of X DL file also extract the information of placement-and-routing, CLB configuration by FPGA Editor instrument;

Because former design document is not revised in test, does not change former design function, so in order to realize application oriented method of testing, so can only the performing step in the above step be operated.Realize mainly being divided into three steps, translation (Translate) logic netlist, mapping (Map) are to device cell and (the Place ﹠amp of placement-and-routing; Route).By order the first two main flow FPGA Xilinx company of manufacturer and the FPGA of altera corp and the instrument that provides thereof are provided, the present invention selects the FPGA of Xilinx company as research object, and reason is as follows:

(1) the FPGA structure of Xilinx is more open than the FPGA structure of Altera;

(2) FPGA of the Xilinx ISE that develops software can provide more FPGA information;

(3) the ISE software of Xilinx allows the user to revise as required configuration file and corresponding tool is provided;

(4) research platform of most of FPGA method of testings all is the FPGA of Xilinx, has comparability.

In the implementation procedure based on ISE, the Main Function of translation is fabric and the hardware primitive that the logic netlist of comprehensively output is translated as the Xilinx certain device, in translation process, design document and unbound document will be merged into the files such as NGD (initial form database) output file, wherein the NGD file including whole logical descriptions of current design.The Main Function of mapping is with design map (LUT, FF, Carry etc.) to the device of concrete model, in mapping process, to be mapped as the specific physical logic units of target devices by the NGD file of flow path switch generation, and remain in the NCD file, the physical mappings information that has comprised current design in the NCD file can be exported the files such as PCF (physical constraint file) that comprise belongings reason constraint information in addition.And placement-and-routing's step can be called Xilinx placement-and-routing device, according to user restraint and physical constraint, design module is carried out actual layout, and according to the design connection, the module after the layout is connected up, produce the FPGA configuration file, placement-and-routing's process is by reading the NCD file of current design, the physical logic units that generates after the mapping is placed and line in goal systems, and be extracted into corresponding time parameter, output file comprises the associated documents such as NCD and DLY (time-delay file).

In the method for testing that invention is used realized, main was exactly to obtain corresponding test configurations by revising the NCD file.The XDL instrument that uses Xilinx to provide is the XDL file with the NCD file conversion, and this file is the readable documents of text formatting, and the grammer of use is Xilinx design language.Then use the Perl language that is applicable to text-processing to revise on request the XDL file, by the XDL instrument amended XDL file is changed into the NCD file again, obtain last configuration file.

Explain take a simple example circuit as each step, this circuit is 5 inputs (i1, i2, i3, i4, i5), the combinational circuit of 2 outputs (o1, o2), and the logic of realization is

o1＝i1?&?i2|i3

o2＝o1?&?i4?&(！i5)

Circuit uses the Verilog language description, and the objective chip model is XC5VFX100T, encapsulation FF1738.

Embodiment three, based on the described use of embodiment one Perl language circuit XDL level net table is described by the interconnecting test method of carrying out application oriented test modifications method,

The described content of present embodiment is the realization of interconnecting test.

The difference that embodiment four, this embodiment and embodiment four described use Perl language are described the interconnecting test method of carrying out application oriented test modifications method to circuit XDL level net table is that described interconnecting test method is specially:

For the example circuit, the result after the comprehensive also automatic placement and routing of use ISE as shown in Figure 2.Real resource among the FPGA that different square frames are corresponding from left to right among the figure is respectively overall cross bar switch, local cross bar switch, impact damper, IO mouth and slice (programmable logic resource among the Xilinx).Wherein, the resource of the box indicating of dark blacking is the actual hardware FPGA resource of using in the design.Fine rule among the figure is the interconnection line that connects each function element that uses in the design in the actual FPGA, namely needs those interconnection lines of test this moment.

As can be seen from Figure 2 this circuit has used two LUT, be present in respectively among two slice, in order to prove that the user restraint file can effectively retrain the position of slice, use the UCF file that these two slice are assigned to the slice in the upper right corner of present position, as shown in Figure 3.

Then revise the configuration logic of LUT, realize the test of interconnection.Here will the circuit after specifying through the UCF file be operated, because in the practical application design, require all can use the UCF file that constraint is added in design in order to satisfy some sequential.Use the XDL instrument among the ISE, the NCD file conversion after the placement-and-routing (PAR) is become the XDL file of text formatting, in the XDL file, find corresponding slice.A slice who for example in this circuit, uses, its being described as in the XDL file:

For the configuration with LUT changes complete and logic into, with statement wherein

D6LUT:oLgc11:#LUT:O6＝((A2*A4)+A6)

Be revised as:

D6LUT:oLgc11:#LUT:O6＝((A2*A4)*A6)

In like manner the configuration modification with other LUT is complete and logic.Reusing the XDL instrument is the NCD file with amended XDL file conversion, as the configuration file of test configurations for the first time in the interconnecting test.For the configuration second time of interconnecting test, need to be complete or logic with the configuration modification of the LUT of use in the design, method is similar, for upper example, with statement

D6LUT:oLgc11:#LUT:O6＝((A2*A4)+A6)

Be revised as:

D6LUT:oLgc11:#LUT:O6＝((A2+A4)+A6)

After having revised all LUT, convert the NCD file to, as the configuration file of the test configurations second time.

In order to verify the validity of this amending method, can in FPGA Editor, open amended NCD file, check by the attribute view window.By above operation, just can finish the test configurations of interconnection.

Embodiment five, based on the described use of embodiment one Perl language circuit XDL level net table is described by the logic test method that carries out application oriented test modifications method,

The realization of the described FPGA (Field Programmable Gate Array) test of present embodiment.

The difference that embodiment six, this embodiment and embodiment five described use Perl language are described the logic test method that carries out application oriented test modifications method to circuit XDL level net table is that the method for circuit XDL level net table being described the programmable logic resource test of carrying out application oriented test modifications method is specially:

Adopt one 6 counter as test vector generator, use the Verilog hardware design language to realize;

Being added in source code of counter added, and is specially:

In order to test programmable logic resource, under the prerequisite of the CLB internal configurations logic that does not change former design use and position, need in design, add test vector generator and response analysis device among the untapped CLB, and the output of test vector generator is connected to the input end of LUT to be measured, the output terminal of LUT is connected on the corresponding analysis device.Here only describe the adding method of test vector generator, the adding method of response analysis device is similar.

Because the LUT of objective chip has 6 inputs, so use one 6 counter as test vector generator, use the Verilog hardware design language to realize.Counter be added with two kinds of methods, the form of in the source code of design, adding counter module add and after placement-and-routing the form with IP kernel add.Here use the method for in source code, adding.To add in the source code with the module of Verilog code construction, and in former design code, increase a clock signal and a reset signal for counter.Attention need to be added the KEEP constraint to counter module when adding, to guarantee it comprehensively is being not optimisedly to fall.Because just calling in source code, do not use counter module.

Then compiling is comprehensive, and counter is placed among the untapped slice, and as shown in Figure 4, two of the lower left corner slice are the main part of counter among the figure, and clock and reset signal do not show in the drawings.

Then the NCD file after this is comprehensive transfers the XDL file to, revise the wiring of the input end of deletion LUT to be measured, the result as shown in Figure 5, compare with Fig. 4, input end and the wiring between the chip input pin of two LUT to be measured in right side are all deleted, and the wiring of the LUT input end of the right upside and the right downside LUT output terminal is also deleted.Two LUT are the line between remaining separately output terminal and the chip output pin only.Just possessed the precondition of the output signal of counter being added to the LUT input end after disconnecting.

Then, in order to realize that counter signals is connected on the LUT, at first must create annexation, then realize wiring.Revise the XDL file, create being connected between counter output and the LUT input end to be measured.Fig. 6 has showed the result in this step, and the fly line among the figure represents between 2 annexation to be arranged but also not wiring.

In FPGA Editor instrument, use the self routing function to finish wiring between the connection that previous step creates, obtain the configuration file for the FPGA (Field Programmable Gate Array) test, Fig. 7 can be clearly seen that for the result after the wiring output terminal of counter has been connected to the input end of LUT to be measured by interconnect resource from figure.

So far, three configuration files that are used for whole test complete, and comprise the complete and logic configuration file that disposes for the first time for interconnection, and the complete or logic configuration file of for the second time configuration is for the configuration file of programmable logic resource test.

To sum up, can realize application oriented test to interconnect resource among the FPGA and programmable logic resource by above-mentioned steps.In the implementation procedure of method of testing, when design can be used sizable FPGA resource when very large, the workload of so manually revising on request the XDL file will quite huge, so in invention, use the Perl program to finish modification to the XDL file.

The below is with another one example circuit, the correctness of the mode validation test method by emulation:

In emulation, the circuit of use is 6 inputs, 2 outputs, has used the combinational circuit of 4 LUT.The logic function that each LUT realizes is as follows:

net1＝(iLgc1|iLgc4)^iLgc3

net2＝(iLgc4?&?iLgc5)|iLgc6

net3＝net4^net2

net4＝！net1

Wherein iLgc1～iLgc6 is the input of circuit, and net1～net4 is the output of each LUT, and as the output of whole circuit, circuit structure as shown in Figure 8 respectively for net2 and net3.

The simulating, verifying of interconnecting test and analysis:

The method of testing of using among the present invention is to test for fixing 0 type fault and fixing 1 type fault on the interconnection line, for the validity of validation test method, must artificially inject fault in circuit so.By the logic of artificial configuration LUT4, make net4 keep respectively " 0 " or " 1 " here always, can realize the injection of fault.

Make when occurring on the net4 fixing 0 type fault, with the configuration logic people of LUT4 for being revised as

net4＝net1?&(！net1)

So no matter why the input of LUT4 is worth, and the value of net4 all is fixed on " 0 ".In like manner injecting the method for fixing 1 type fault at net4 is that artificial logic configuration with LUT4 is

net4＝net1|(！net1)

Can realize so no matter why the input of LUT4 is worth, and the value on the net4 all is " 1 ".

To apply the simulation result that obtains behind the counter signals to 6 input ends of the circuit that uses in the experiment among Fig. 9, with as a reference.Figure 10 is the circuit output map after 0 type fault is fixed in the net4 injection, the input of circuit remains counter signals, as can be seen from the figure the result of oLgc1 is identical with primary circuit, and the result of output terminal oLgc2 is different with primary circuit, from the primary circuit structure analysis, output oLgc1 draws from net2, output oLgc2 draws from net3, output for LUT3, and the logic function that LUT3 realizes is the XOR of net2 and net4, the XOR result that can obviously find out oLgc1 and " 0 " from Figure 10 is the value of oLgc2 just, it can be said that to have injected on the net4 in the bright circuit and fixes 0 type fault.In like manner still apply counter signals at input end among Figure 11, the value of oLgc2 just is being the XOR result of oLgc1 and " 1 ", it can be said that to have injected on the net4 in the bright circuit and fixes 1 type fault.

Figure 12 to 13 provides is that circuit is carried out the Output rusults under counter signals after the test configurations.Figure 12 is the complete and logic configuration of fixing 0 type fault on the test interconnection line, the logic that realizes among the LUT all be the LUT input signal with.Can find out from the primary circuit structure, output oLgc1 for the input iLgc4～iLgc6 with, output oLgc2 for the input iLgc1～iLgc6 with.The result of Figure 12 is just corresponding with input, and oLgc1 only just is " 1 " when iLgc4～iLgc6 is " 1 ", and oLgc2 just is " 1 " when iLgc1～iLgc6 is " 1 ".The result of Figure 13 is also corresponding with input, and oLgc1 only just is " 0 " when iLgc4～iLgc6 is " 0 ", and oLgc2 just is " 0 " when iLgc1～iLgc6 is " 0 ".Figure 12 to 13 verified configuration help with complete or logic after result's correctness.

On net4, inject respectively and fix 0 type and fix 1 type fault, and use respectively corresponding method of testing to test, what provide among Figure 14 is that 0 type fault is fixed in the circuit injection, use complete and configuration, input end applies the all-1 test vector, as can be seen from the figure, after the 200ns place applies the all-1 test vector, output terminal oLgc1 is output as " 1 ", illustrate on the front-end circuit of oLgc1 and do not break down, oLgc2 is output as " 0 ", illustrate that detecting the circuit existence fixes 0 type fault, and this fault occurs on the circuit relevant with oLgc2.In Figure 15, circuit injects fixes 1 type fault, input end at circuit applies the all-0 test vector, as can be seen from the figure, after 200ns place test vector applied, oLgc1 was output as " 0 ", illustrated that the front-end circuit of oLgc1 is not normally fixed 0 type fault, and oLgc2 is output as " 1 ", illustrates on the front-end circuit of oLgc2 0 type fault has occured to fix.The position, position of net4 and the front end of oLgc2 in this circuit, and do not have influence on oLgc1 with oLgc1.

Simulating, verifying and the analysis of FPGA (Field Programmable Gate Array) test:

What Figure 16 provided is the front simulation result of injection logic fault, and the signal that the input end of each LUT adds is provided by the test vector generator that uses in counter and the emulation.The output of each LUT is guided to respectively on the IO of FPGA, and corresponding relation is that LUT1 is output as oLgc3, and LUT2 is output as oLgc1, and LUT3 is output as oLgc2, and LUT4 is output as oLgc4, with observations.In the emulation, ((oLgc1_R～oLgc4_R) compare, fault display signal are respectively (fault1～fault4) to the LUT Output rusults that oLgc1～oLgc4) and emulation obtain with the Output rusults of primary circuit LUT.By as can be seen from Figure 16, the primary circuit LUT output of not injecting fault is identical with the LUT output of emulation, and all fault display signals remain " 0 " always, namely do not break down.

Programmable logic resource in the primary circuit use injects fault for test, and in the emulation, the logic that realizes among the LUT3 was XOR originally, and the people has namely realized the fault injection on the programmable logic resource for being revised as or logic now.The input end of each LUT connects the output signal of corresponding excitation maker, and as can be seen from Figure 17, oLgc2 is different with oLgc2_R appearance behind about 2us, and fault display signal fault2 also becomes " 1 " simultaneously, shows that corresponding LUT3 has logic fault.Can illustrate by simulation result that this method of testing can detect the logic fault of LUT thus.

In this emulation, directly output signal is directly guided on the IO of FPGA, the benefit of tectonic response analyzer is to be simple and easy to realize like this, can compare very easily and directly obtain the position of the LUT that breaks down with simulation result.But IO belongs to scarce resource in practice, thus need the inner response analysis device of structure, correct result store is inner at FPGA, compare in FPGA inside, result is relatively compressed a small amount of IO output of rear use.Although reduce in the cost aspect the use IO, the complex structure of response analysis device implements difficulty, and can take a large amount of memory resources.Comprehensive balance, in this checking property emulation, the emphasis of emulation is correctness and the validity of the application oriented method of testing of checking chapter 2, the response analysis device is not the emphasis of emulation, and the circuit that emulation is adopted is simple, and the LUT of use is less, and the quantity of IO can satisfy, so in emulation, adopt direct output with LUT to be drawn out on the IO of FPGA, with the carrying out of convenient experiment.

Claims

1. use the Perl language that circuit XDL level net table is described and carry out application oriented test modifications method, it is characterized in that: its method is:

2. use Perl language according to claim 1 is described circuit XDL level net table and is carried out application oriented test modifications method, it is characterized in that using the Perl language that circuit XDL level net table is described and carries out application oriented test modifications method and be specially:

3. based on use Perl language claimed in claim 1 circuit XDL level net table is described the interconnecting test method of carrying out application oriented test modifications method, it is characterized in that:

4. use Perl language according to claim 4 is described the interconnecting test method of carrying out application oriented test modifications method to circuit XDL level net table, it is characterized in that described interconnecting test method is specially:

5. based on use Perl language claimed in claim 1 circuit XDL level net table is described the logic test method that carries out application oriented test modifications method, it is characterized in that:

6. the logic test method that carries out application oriented test modifications method described in use Perl language according to claim 5 to circuit XDL level net table, it is characterized in that LUT is for having n input end, n is positive integer, and the method for circuit XDL level net table being described the programmable logic resource test of carrying out application oriented test modifications method is specially:

Being added in source code of counter added, and is specially: