CN103367454A - Thin film transistor, manufacturing method thereof, and active matrix display panel - Google Patents
Thin film transistor, manufacturing method thereof, and active matrix display panel Download PDFInfo
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- CN103367454A CN103367454A CN2012100926928A CN201210092692A CN103367454A CN 103367454 A CN103367454 A CN 103367454A CN 2012100926928 A CN2012100926928 A CN 2012100926928A CN 201210092692 A CN201210092692 A CN 201210092692A CN 103367454 A CN103367454 A CN 103367454A
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Abstract
The invention discloses a thin film transistor which is arranged on a substrate. The thin film transistor comprises a grid electrode, an insulating layer, a metal-oxide semiconductor pattern, a source electrode, a drain electrode and a polyimide layer, wherein the grid electrode is arranged on the substrate, the insulating layer is covered on the grid electrode, the source electrode is arranged on the insulating layer, the metal-oxide semiconductor pattern is arranged on the substrate, and the polyimide layer is covered on the metal-oxide semiconductor pattern.
Description
Technical field
The present invention relates to a kind of thin-film transistor, its manufacture method and use its active matrix display panel, particularly relate to and a kind ofly utilize pi (polyimide) layer as thin-film transistor, its manufacture method of protective layer and use its active matrix display panel.
Background technology
Thin-film transistor has been widely used in the active matrix display panel as driving component, in order to drive liquid crystal molecule or organic electric exciting light-emitting diode.Wherein, because the metal oxide semiconductor films transistor has the electrical characteristic of high carrier mobility of low-temperature polysilicon film transistor and the high electrically uniformity of amorphous silicon film transistor, therefore the display floater of using metal oxide semiconductor thin-film transistor becomes the emphasis of industry development gradually.
Make in the transistorized method of metal oxide semiconductor films existing, grid system is formed on first on the substrate, and then gate insulator covers on grid and the substrate.Then, metal oxide semiconductor layer is formed on the gate insulator, and then source electrode and drain electrode are formed on the metal oxide semiconductor layer.Yet the material system of existing metal-oxide semiconductor (MOS) uses indium oxide gallium zinc (indium gallium zinc oxide, IGZO), and indium oxide gallium zinc is quite responsive to aqueous vapor and oxygen, and easy and both reactions cause electrical variation.And; owing to source electrode forms via the same metal level of etching with drain electrode system; therefore the surface of indium oxide gallium zinc also easily is subject to destroying for the etching solution of etching sheet metal or the plasma of dry etch process; even the plasma that is used to form protective layer also can be to the surperficial injury of indium oxide gallium zinc, and then produces electrically and change.In addition, because indium oxide gallium zinc easily produces photoelectric current under the irradiation of ultraviolet light, therefore cause existing metal oxide semiconductor films transistorized electrically not good and unstable.
In view of this, the target of avoiding indium oxide gallium zinc to cause the transistorized electrically not good situation of metal oxide semiconductor films to make great efforts for industry in fact because of the impact that is subject to aqueous vapor, oxygen, etching solution and ultraviolet light.
Summary of the invention
The active matrix display panel that main purpose of the present invention is to provide a kind of thin-film transistor, its manufacture method and uses it causes the transistorized electrically not good situation of metal oxide semiconductor films to avoid indium oxide gallium zinc because of the impact that is subject to aqueous vapor, oxygen, etching solution and ultraviolet light.
In order to achieve the above object, the invention provides a kind of thin-film transistor, be located on the substrate.Thin-film transistor comprises a grid, an insulating barrier, a metal-oxide semiconductor (MOS) pattern, one source pole, drain electrode and a polyimide.Grid is located on the substrate, and insulating barrier covers on the grid.The metal-oxide semiconductor (MOS) pattern is located on the substrate, and source electrode and drain electrode are located on the insulating barrier.Pi (polyimide) layer covers on the metal-oxide semiconductor (MOS) pattern.
In order to achieve the above object, the invention provides a kind of active matrix display panel, comprise a first substrate, a second substrate, a grid, an insulating barrier, a metal-oxide semiconductor (MOS) pattern, one source pole, drain electrode and a polyimide.Second substrate and first substrate are oppositely arranged, and grid is located between first substrate and the second substrate.Insulating barrier is located between grid and the first substrate.The metal-oxide semiconductor (MOS) pattern is located between first substrate and the second substrate.Source electrode and drain electrode are located between insulating barrier and the first substrate, and polyimide is located between metal-oxide semiconductor (MOS) pattern and the first substrate.
In order to achieve the above object, the invention provides a kind of manufacture method of thin-film transistor.At first, form a grid at a substrate.Then, cover an insulating barrier at grid.Then, form a metal-oxide semiconductor (MOS) pattern, one source pole and a drain electrode at insulating barrier.Subsequently, cover a polyimide in metal-oxide semiconductor (MOS) pattern, source electrode and drain electrode.
Thin-film transistor of the present invention utilizes polyimide to cover not only can intercept UV-irradiation in the metal-oxide semiconductor (MOS) pattern on the metal-oxide semiconductor (MOS) pattern, that also can utilize that polyimide makes the metal-oxide semiconductor (MOS) pattern electrically gets back to stable state, and then avoids electrically not good situation of thin-film transistor.
Description of drawings
Fig. 1 is to the manufacture method schematic diagram of the thin-film transistor that Figure 5 shows that the present invention's one first preferred embodiment.
Figure 6 shows that the schematic diagram that concerns of photon energy and wavelength.
The penetrance that Figure 7 shows that polyimide and the schematic diagram that concerns that shines in the wavelength of the light of polyimide.
Fig. 8 is to the manufacture method schematic diagram of the thin-film transistor that Figure 10 shows that the present invention's one second preferred embodiment.
Another of the manufacture method of Figure 11 and the thin-film transistor that Figure 12 shows that second preferred embodiment of the invention implemented aspect.
Figure 13 and the manufacture method schematic diagram that Figure 14 shows that the thin-film transistor of the present invention 1 the 3rd preferred embodiment.
The etching stopping pattern that Figure 15 shows that thin-film transistor is the schematic diagram that concerns of drain current in single layer structure and the double-deck situation and grid voltage.
Figure 16 shows that the situation that situation that protective layer is made of silica or silicon nitride, situation that protective layer is polyimide and channel region are made of amorphous silicon, the drain current of thin-film transistor and grid voltage concern schematic diagram.
Figure 17 shows that the generalized section of the thin-film transistor of the present invention 1 the 4th preferred embodiment.
Figure 18 shows that the generalized section of the thin-film transistor of the present invention 1 the 5th preferred embodiment.
Figure 19 shows that the generalized section of the active matrix display panel of one embodiment of the present invention.
Figure 20 shows that the generalized section of the active matrix display panel of another preferred embodiment of the present invention.
Wherein, description of reference numerals is as follows:
10 thin-film transistors, 12 substrates
14 grids, 16 insulating barriers
18 metal oxide semiconductor layer 18a metal-oxide semiconductor (MOS) patterns
22 drain electrodes of 20 source electrodes
24 polyimides, 26 first sections
28 second sections 30 the 3rd section
Final 32's degree scope 50 thin-film transistors
52 etching stop layer 52a etching stopping patterns
54 openings, 100 thin-film transistors
102 second etching stop layer 102a the second etching stopping pattern
104 first etching stop layer 104a the first etching stopping pattern
106 protective layers, 150 thin-film transistors
202 perforation of 200 thin-film transistors
204 protective layers, 300 active matrix display panel
302 first substrates, 304 second substrates
306 organic electric-excitation luminescent unit, 308 frame glue
400 active matrix display panel, 402 first substrates
404 second substrates, 406 pixel electrode layers
408 both alignment layers, 410 liquid crystal layers
412 frame glue C
1The first curve
C
2The second curve C
3The 3rd curve
C
4The 4th curve C
5The 5th curve
Embodiment
Have the knack of those skilled in the art and can further understand the present invention for making, hereinafter the spy enumerates the preferred embodiments of the present invention, and cooperate appended graphic, describe in detail constitution content of the present invention and the effect wanting to reach.
Please refer to Fig. 1 to Fig. 5, Fig. 1 is to the manufacture method schematic diagram of the thin-film transistor that Figure 5 shows that the present invention's one first preferred embodiment, and wherein Fig. 5 is the generalized section of the thin-film transistor of first preferred embodiment of the invention.At first, as shown in Figure 1, form a first metal layer at a substrate 12, then carry out a photoetching process and an etching technics, the patterning the first metal layer is to form a grid 14.Then, as shown in Figure 2, cover an insulating barrier 16 at grid 14.Subsequently, as shown in Figure 3, cover a metal oxide semiconductor layer 18 at insulating barrier 16.In the present embodiment, substrate 12 can be transparency carriers such as glass substrate or plastic base, but is not limited to this.And insulating barrier 16 is the gate insulator as thin-film transistor, and can comprise silica, silicon nitride or silicon oxynitride, but is not limited to this.In addition, metal oxide semiconductor layer 18 comprises indium oxide gallium zinc (indium gallium zinc oxide, IGZO).
Then, as shown in Figure 4, carry out another photoetching process and another etching technics, patterning metal oxide semiconductor layer 18, forming a metal-oxide semiconductor (MOS) pattern 18a, and metal-oxide semiconductor (MOS) pattern 18a be positioned at grid 14 directly over, with the channel region as thin-film transistor.Then, as shown in Figure 5, cover one second metal level at insulating barrier 16 with metal-oxide semiconductor (MOS) pattern 18a, then carry out another photoetching process and another etching technics, patterning the second metal level, drain 22 to form one source pole 20 and at metal-oxide semiconductor (MOS) pattern 18a, and source electrode 20 is to overlap with grid 14 with drain electrode 22.At last, at metal-oxide semiconductor (MOS) pattern 18a, source electrode 20, drain electrode 22 and insulating barrier 16 coating one polyamic acid (polyamic acid) solution, then carry out a heating steps, make polyamic acid solution produce a cross-linking reaction, cover source electrode 20, drain electrode 22, metal-oxide semiconductor (MOS) pattern 18a and insulating barrier 16 to form a pi (polyimide) layer 24, and polyimide 24 is to contact with metal-oxide semiconductor (MOS) pattern 24.So far finished the thin-film transistor 10 of the present embodiment.
It should be noted that, the present embodiment utilization coating has liquid polyamic acid solution can have good step coverage rate on metal-oxide semiconductor (MOS) pattern 18a, source electrode 20, drain electrode 22 and insulating barrier 16, to be used for as flatness layer, and can avoid having relatively poor coverage rate because utilizing depositing operation to make at vertical sidewall, and can solve the problem that on the corner produces the crack because of relatively poor coverage rate.And, but polyimide 24 wavelength-filtered of the present embodiment are less than the ultraviolet light of 315 nanometers, therefore the polyimide 24 that covers on the metal-oxide semiconductor (MOS) pattern 18a can effectively intercept UV-irradiation in metal-oxide semiconductor (MOS) pattern 18a, and then avoids the electrical not good situation of thin-film transistor 10.
Below will further specify the effect of the thin-film transistor 10 of the present embodiment.Please refer to Fig. 6 and Fig. 7, and in the lump with reference to figure 5.Figure 6 shows that the schematic diagram that concerns of photon energy and wavelength, the penetrance that Figure 7 shows that polyimide and the schematic diagram that concerns that shines in the wavelength of the light of polyimide.As shown in Figure 6, ultraviolet light (ultraviolet, UV) spectrum can be distinguished into the first section 26, the second section 28 and the 3rd section 30, and the first section 26, the second section 28 and the 3rd section 30 are called ultraviolet light A (UV-A), ultraviolet light B (UV-B) and ultraviolet light C (UV-C).The wave spread of the first section 26, the second section 28 and the 3rd section 30 is respectively 315～400 nanometers, 280～315 nanometers and 100～280 nanometers, therefore the photon energy of ultraviolet light A is the photon energy less than ultraviolet light B, and the photon energy of ultraviolet light B is less than the photon energy of ultraviolet light C.It should be noted that, the strength range 32 of chemical bond is to be distributed in 80～100 kilocalories/mole (kcal/mol), therefore the photon energy of ultraviolet light A is not sufficient to destroy chemical bonded refractory, only has the photon energy of ultraviolet light B and ultraviolet light C to have enough intensity and can destroy chemical bonded refractory.As shown in Figure 7, when wavelength shone in polyimide less than the light of 315 nanometers, penetrance was about zero, so polyimide can stop that wavelength is less than the light of 315 nanometers.By this, polyimide can effectively intercept ultraviolet light B and the ultraviolet light C that can destroy chemical bonded refractory.Hence one can see that, the present embodiment covers polyimide can effectively avoid the metal-oxide semiconductor (MOS) pattern to be subject to from the destruction of the ultraviolet light of metal-oxide semiconductor (MOS) pattern top irradiation on the metal-oxide semiconductor (MOS) pattern, be subject to UV-irradiation and produce electrically not good situation to solve thin-film transistor.
In addition, the pi molecule in the polyimide has the functional group of the two keys (C=O) of carbon oxygen, makes the hydrogen atom in the adsorbable metal-oxide semiconductor (MOS) pattern of oxygen atom, and forms hydrogen bond.By this, the oxygen atom of metal-oxide semiconductor (MOS) pattern can electrically be got back to stable state because of what the polyimide hydrogen ion adsorption made the metal-oxide semiconductor (MOS) pattern because producing too much hydrogen atom with aqueous vapor reaction in manufacturing process.Hence one can see that, and what the present embodiment utilized polyimide to contact with the metal-oxide semiconductor (MOS) pattern to make the metal-oxide semiconductor (MOS) pattern electrically gets back to stable state, and avoids the impact that electrically is subject to aqueous vapor of thin-film transistor.And, because polyimide is about 0.5% at 25 ℃ of lower water absorption rates of placing 24 hours of temperature, and its size does not change, therefore except having the characteristic that coefficient of linear expansion is little and dimensional stability is good, more can effectively intercept aqueous vapor and enter in the metal-oxide semiconductor (MOS) pattern, make the characteristic of metal-oxide semiconductor (MOS) pattern can not be subject to the aqueous vapor impact.In addition, polyimide has resistance to chemical reagents, good be electrically insulated characteristic and low-k, and can under the environment of 250～300 ℃ of temperature, use for a long time, and heat resisting temperature is higher than 400 ℃, even can up to 500 ℃, therefore more effectively promote the scope of application of the thin-film transistor of the present embodiment.
Thin-film transistor of the present invention is not limited with above-described embodiment.Hereinafter will continue to disclose other embodiments of the invention or change shape, so for the purpose of simplifying the description and highlight each embodiment or change difference between the shape hereinafter use same numeral mark same components, and no longer counterweight again part give unnecessary details.
Please refer to Fig. 8 to Figure 10, and in the lump referring to figs. 1 to Fig. 4.Fig. 8 wherein Figure 10 shows that the generalized section of the thin-film transistor of second preferred embodiment of the invention to the manufacture method schematic diagram of the thin-film transistor that Figure 10 shows that the present invention's one second preferred embodiment.To shown in Figure 4, compared to the first embodiment, the present embodiment is identical with the first embodiment in the step system that substrate 12 is made grid 14, insulating barrier 16 and metal-oxide semiconductor (MOS) pattern 18a such as Fig. 1.Then, as shown in Figure 8, carry out a depositing operation, for example physical gas-phase deposition or chemical vapor deposition method cover etching stop-layer 52, for example a silicon dioxide at insulating barrier 16 with metal-oxide semiconductor (MOS) pattern 18a.Then, as shown in Figure 9, carry out another photoetching process and another etching technics, patterning etching stop layer 52 is to form etching stopping pattern 52a directly over grid 14.That is etching stopping pattern 52a is on the metal-oxide semiconductor (MOS) pattern 18a that is positioned at as channel region.Subsequently, as shown in figure 10, cover one second metal level at insulating barrier 16, metal-oxide semiconductor (MOS) pattern 18a and etching stopping pattern 52a, then carry out another photoetching process and another etching technics, patterning the second metal level, forming source electrode 20 and to drain 22 at metal-oxide semiconductor (MOS) pattern 18a and etching stopping pattern 52a, and source electrode 20 has an opening 54 between 22 with draining, and exposes etching stopping pattern 52a.At last, form polyimide 24 at etching stopping pattern 52a, source electrode 20, drain electrode 22 and insulating barrier 16.So far finished the thin-film transistor 50 of the present embodiment.It should be noted that; the manufacture method of the present embodiment ties up to and forms source electrode 20 and drained before 22; form etching stopping pattern 52a at metal-oxide semiconductor (MOS) pattern 18a first; make etching stopping pattern 52a can protect metal-oxide semiconductor (MOS) pattern 18a as channel region, destroy to avoid metal-oxide semiconductor (MOS) pattern 18a to be subject to etching solution when patterning the second metal level.
The thin-film transistor of the present embodiment is not limited to above-mentioned manufacture method.Please refer to Figure 11 and Figure 12, and in the lump referring to figs. 1 to Fig. 3 and Fig. 9 to Figure 10.Another of the manufacture method of Figure 11 and the thin-film transistor that Figure 12 shows that second preferred embodiment of the invention implemented aspect.The difference of this enforcement aspect and above-mentioned the second preferred embodiment is, this enforcement aspect after forming metal oxide semiconductor layer 18 not immediately to metal oxide semiconductor layer 18 patternings, and first deposition-etch stop-layer 52, and form etching stopping pattern 52a, patterning metal oxide semiconductor layer 18 just then.As shown in figure 11, utilize first Fig. 1 to the step of Fig. 3 after substrate 12 is produced grid 14, insulating barrier 16 and metal oxide semiconductor layer 18, carry out a depositing operation, to cover an etching stop-layer 52 at metal oxide semiconductor layer 18.Subsequently, as shown in figure 12, carry out another photoetching process and another etching technics, patterning etching stop layer 52 is to form etching stopping pattern 52a.Subsequently, as shown in Figure 9, carry out another photoetching process and another etching technics, patterning metal oxide semiconductor layer 18 is to form a metal-oxide semiconductor (MOS) pattern 18a.The follow-up step of this enforcement aspect is identical with the step of above-mentioned second preferred embodiment Figure 10, therefore this do not give unnecessary details more.
Etching stop layer cording of the present invention has sandwich construction, and utilizes respectively different technology conditions to form, to reduce the destruction to the metal-oxide semiconductor (MOS) pattern.Please refer to Figure 13 and Figure 14, and in the lump referring to figs. 1 to Fig. 4.Figure 13 and the manufacture method schematic diagram that Figure 14 shows that the thin-film transistor of the present invention 1 the 3rd preferred embodiment, wherein Figure 14 is the generalized section of the thin-film transistor of third preferred embodiment of the invention.To shown in Figure 4, compared to the second embodiment, the present embodiment is identical with the second embodiment in the step system that substrate 12 is made grid 14, insulating barrier 16 and metal-oxide semiconductor (MOS) pattern 18a such as Fig. 1.Subsequently, as shown in figure 13, carry out a physical gas-phase deposition, to cover one second etching stop layer 102, for example silicon dioxide at metal-oxide semiconductor (MOS) pattern 18a and insulating barrier 16.Afterwards, carry out a chemical vapor deposition method, cover one first etching stop layer 104, for example silicon dioxide at the second etching stop layer 102.Then, as shown in figure 14, carry out another photoetching process and another etching technics, patterning the first etching stop layer 104 and the second etching stop layer 102, forming the first etching stopping pattern 104a and the second etching stopping pattern 102a, and the second etching stopping pattern 102 and the first etching stopping pattern 104 sequentially are stacked on the metal-oxide semiconductor (MOS) pattern 18a.Then, cover one second metal level at insulating barrier 16, metal-oxide semiconductor (MOS) pattern 18a and the first etching stopping pattern 104a, then carry out another photoetching process and another etching technics, patterning the second metal level, to form source electrode 20 and to drain 22 at metal-oxide semiconductor (MOS) pattern 18a and the first etching stopping pattern 104a, and the opening 54 between source electrode 20 and the drain electrode 22 exposes the first etching stopping pattern 104a.At last, form a protective layer 106 at the first etching stopping pattern 104a, source electrode 20, drain electrode 22 and insulating barrier 16.So far finished the thin-film transistor 100 of the present embodiment.
In the present embodiment, physical gas-phase deposition is sputtering process, and take silica as target, and utilize the argon ion bombardment target, silica is deposited on the metal-oxide semiconductor (MOS) pattern 18a, to form the second etching stop layer 102.But physical gas-phase deposition of the present invention is not limited to sputtering process, and the target material of the second etching stop layer 102 also is not limited to silica.In addition, the chemical vapor deposition method of the present embodiment can be plasma-assisted chemical vapour deposition (plasma-enhanced chemical vapor deposition, PECVD) technique, but is not limited to this.It should be noted that, the physical gas-phase deposition system that the present embodiment forms the second etching stop layer 102 imposes low-power, power less than chemical vapor deposition method, reducing in the physical gas-phase deposition argon ion to the destruction of metal-oxide semiconductor (MOS) pattern 18a, and reduce the subsequent chemistry gas-phase deposition to the destruction of metal-oxide semiconductor (MOS) pattern 18a.The first etching stopping pattern 104a has a first film density, and the second etching stopping pattern 102a has one second density of film, less than the first film density.And chemical vapor deposition method system imposes high power, makes the first etching stopping pattern 104a with the first film density can be used in protection as the metal-oxide semiconductor (MOS) pattern of channel region.In addition, the protective layer 106 of the present embodiment is a polyimide, but is not limited to this, also can be made of insulating material such as silica or silicon nitride.Etching stopping pattern of the present invention only for being made of the first etching stopping pattern and the second etching stopping pattern, also can be made of multilayer etching stopping pattern.
In other embodiments of the invention, also can be not immediately to the metal oxide semiconductor layer patterning after forming metal oxide semiconductor layer, and carry out first physical gas-phase deposition and chemical vapor deposition method, on metal oxide semiconductor layer, sequentially to deposit the second etching stop layer and the first etching stop layer, then form the first etching stopping pattern and the second etching stopping pattern, then patterning metal oxide semiconductor layer.
Below will further specify the effect of the thin-film transistor of above-mentioned the 3rd embodiment.Please refer to Figure 15, the etching stopping pattern that Figure 15 shows that thin-film transistor is the schematic diagram that concerns of drain current in single layer structure and the double-deck situation and grid voltage.As shown in figure 15, the first curve C
1The etching stopping pattern that is thin-film transistor is single layer structure, and the lower measurement of situation that consisted of by silica or silicon nitride of protective layer to drain current and the relation curve of grid voltage, and the second curve C
2Be the lower measurement of situation that consisted of by silica or silicon nitride of the protective layer of the thin-film transistor of above-mentioned the 3rd embodiment to drain current and the relation curve of grid voltage.And, the first curve C
1The subcritical amplitude of oscillation (subthreshold swing), that is the inverse of the slope of curve is greater than the second curve C
2The subcritical amplitude of oscillation.Hence one can see that, the manufacture method of the thin-film transistor of the 3rd embodiment utilizes first the lower physical gas-phase deposition of power to form the second etching stopping pattern, and then utilize the higher chemical vapor deposition method of power to form to have the first etching stopping pattern of larger density of film, can effectively promote the subcritical amplitude of oscillation of thin-film transistor, and highlight the switching characteristic of thin-film transistor.Please refer to Figure 16, Figure 16 shows that the situation that situation that protective layer is made of silica or silicon nitride, situation that protective layer is polyimide and channel region are made of amorphous silicon, the drain current of thin-film transistor and grid voltage concern schematic diagram.As shown in figure 16, the 3rd curve C
3Be the lower measurement of situation that consisted of by silica or silicon nitride of the protective layer of the thin-film transistor of above-mentioned the 3rd embodiment to drain current and the relation curve of grid voltage; The 4th curve C
4Be above-mentioned the 3rd embodiment thin-film transistor protective layer by the situation of polyimide lower the drain current that arrives of measurement and the relation curve of grid voltage; And the 5th curve C
5Be the lower measurement of situation that consisted of by amorphous silicon of the channel region of thin-film transistor to drain current and the relation curve of grid voltage.Because the 3rd curve C
3The subcritical amplitude of oscillation greater than the 5th curve C
5The subcritical amplitude of oscillation, therefore in the situation that protective layer is that the switching characteristic of thin-film transistor of polyimide is in the situation that the switching characteristic of the thin-film transistor that protective layer is made of silica or silicon nitride is good.And, the 4th curve C
4The subcritical amplitude of oscillation greater than the 5th curve C
5The subcritical amplitude of oscillation, therefore the thin-film transistor of above-mentioned the 3rd embodiment more can effectively improve the switching characteristic when the channel region of thin-film transistor is made of amorphous silicon in the situation that protective layer is polyimide.
Please refer to Figure 17, Figure 17 shows that the generalized section of the thin-film transistor of the present invention 1 the 4th preferred embodiment.As shown in figure 17, compared to the first embodiment, the step system of the present embodiment formation metal-oxide semiconductor (MOS) pattern 18a is carried out at the step that forms source electrode 20 and drain electrode 22 and forms between the step of polyimide 24.By this, the metal-oxide semiconductor (MOS) pattern 18a of the thin-film transistor 150 of the present embodiment is located between source electrode 20 and the polyimide 24 and between drain electrode 22 and polyimide 24, and extend in source electrode 20 and the opening of drain electrode between 22, and contact with insulating barrier 16.
Please refer to Figure 18, Figure 18 shows that the generalized section of the thin-film transistor of the present invention 1 the 5th preferred embodiment.Compared to the first embodiment, the thin-film transistor of the present embodiment is the thin-film transistor of a top grid (top gate) type.As shown in figure 18, the present embodiment system forms metal-oxide semiconductor (MOS) pattern 18a at substrate 12 first, then covers polyimide 24 at metal-oxide semiconductor (MOS) pattern 18a and substrate 12.Then, form grid 14 at polyimide 24, and cover insulating barrier 16 at grid 14 and polyimide 24.Subsequently, in the insulating barrier 16 of grid 14 both sides and polyimide 24, form respectively two perforation 202, and respectively bore a hole and 202 run through insulating barrier 16 and polyimide 24, and expose metal-oxide semiconductor (MOS) pattern 18a.Then, form source electrode 20 and drain electrode 22 at insulating barrier 16, insert respectively and respectively bore a hole 202.By this, source electrode 20 contacts with metal-oxide semiconductor (MOS) pattern 18a by each perforation 202 with drain electrode 22.Then, cover a protective layer 204 at source electrode 20, drain electrode 22 and insulating barrier 16.So far finished the thin-film transistor 200 of the present embodiment.
In addition, the present invention provides the active matrix display panel of the thin-film transistor of using above-described embodiment in addition.Please refer to Figure 19 and Figure 20, Figure 19 shows that the generalized section of the active matrix display panel of one embodiment of the present invention, and Figure 20 shows that the generalized section of the active matrix display panel of another preferred embodiment of the present invention.Below describe system take the thin-film transistor of above-mentioned the first embodiment as example, but be not limited to this, and the structure of thin-film transistor does not repeat them here.As shown in figure 19, the active matrix display panel 300 of the present embodiment is that an organic electric-excitation luminescent displaying panel comprises a first substrate 302, a second substrate 304, a thin-film transistor 10, an organic electric-excitation luminescent unit 306 and a frame glue 308.First substrate 302 is positioned opposite to each other with second substrate 304, and thin-film transistor 10 is located on the second substrate 304, and between first substrate 302 and second substrate 304.Organic electric-excitation luminescent unit 306 is located between the polyimide 24 and first substrate 302 of thin-film transistor 10, and can be made of an anode, an organic electric-excitation luminescent layer and a negative electrode, but is not limited to this.And frame glue 308 is located between first substrate 302 and the second substrate 304, and be used for binding first substrate 302 and second substrate 304, and frame glue 308 is not overlapping with polyimide 24.By this, the frame glue 24 of the present embodiment can be avoided occuring because of the not enough situation that causes frame glue 24 to come off of tackness with polyimide 24.As shown in figure 20, compared to above-described embodiment, the active matrix display panel 400 of the present embodiment is a display panels, comprises a first substrate 402, a second substrate 404, a thin-film transistor 10, a pixel electrode layer 406, a both alignment layers 408, a liquid crystal layer 410 and a frame glue 412.In the present embodiment, first substrate 402 can be colored filter substrate, but is not limited to this.First substrate 402 is positioned opposite to each other with second substrate 404, and liquid crystal layer 410 is located between first substrate 402 and the second substrate 404.And thin-film transistor 10 is located on the second substrate 404, and between first substrate 402 and second substrate 404.Pixel electrode layer 406 is located between the polyimide 24 and liquid crystal layer 410 of thin-film transistor 10, and both alignment layers 408 is located between the polyimide 24 and pixel electrode layer 406 and liquid crystal layer 410 of thin-film transistor 10.And frame glue 412 is located between first substrate 402 and the second substrate 404, and be used for binding first substrate 402 and second substrate 404, and frame glue 408 is not overlapping with polyimide 24.The present invention is not limited to the active matrix display panel of above-described embodiment, also can be the display floater of other kind.
In sum, thin-film transistor of the present invention utilizes polyimide to cover not only can intercept UV-irradiation in the metal-oxide semiconductor (MOS) pattern on the metal-oxide semiconductor (MOS) pattern, that also can utilize that polyimide makes the metal-oxide semiconductor (MOS) pattern electrically gets back to stable state, and then avoids electrically not good situation of thin-film transistor.In addition; thin-film transistor of the present invention utilizes lower powered depositing operation to form the second etching stopping pattern at the metal-oxide semiconductor (MOS) pattern in addition; recycle high-power depositing operation and form the first etching stopping pattern at the second etching stopping pattern; can reduce in the depositing operation argon ion to the destruction of metal-oxide semiconductor (MOS) pattern, and make the first etching stopping pattern can be used in protection as the metal-oxide semiconductor (MOS) pattern of channel region.By this, the switching characteristic of thin-film transistor more can be enhanced effectively.The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.All in the spirit and principles in the present invention, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (26)
1. a thin-film transistor is located on the substrate, and is it is characterized in that, described thin-film transistor comprises:
One grid is located on the described substrate;
One insulating barrier covers on the described grid;
One metal-oxide semiconductor (MOS) pattern is located on the described substrate;
One source pole and a drain electrode are located on the described insulating barrier; And
One polyimide covers on the described metal-oxide semiconductor (MOS) pattern.
2. thin-film transistor as claimed in claim 1 is characterized in that, described metal-oxide semiconductor (MOS) pattern comprises indium oxide gallium zinc.
3. thin-film transistor as claimed in claim 1 is characterized in that, described metal-oxide semiconductor (MOS) pattern is located between described gate insulator and the described source electrode and between described gate insulator and the described drain electrode.
4. thin-film transistor as claimed in claim 3 is characterized in that, also comprises one first etching stopping pattern, be located between described polyimide and the described metal-oxide semiconductor (MOS) pattern, and described the first etching stopping pattern has a first film density.
5. thin-film transistor as claimed in claim 4, it is characterized in that, also comprise one second etching stopping pattern, be located between described the first etching stopping pattern and the described metal-oxide semiconductor (MOS) pattern, and described the second etching stopping pattern has one second density of film, less than described the first film density.
6. thin-film transistor as claimed in claim 1, it is characterized in that, described metal-oxide semiconductor (MOS) pattern is located between described source electrode and the described polyimide and between described drain electrode and the described polyimide, and extends between described source electrode and the described drain electrode.
7. thin-film transistor as claimed in claim 1 is characterized in that, described grid is located on the described polyimide.
8. thin-film transistor as claimed in claim 7 is characterized in that, described insulating barrier and described polyimide have two perforation, and described source electrode contacts with described metal-oxide semiconductor (MOS) pattern by each described perforation respectively with described drain electrode.
9. an active matrix display panel is characterized in that, comprising:
One first substrate;
One second substrate is oppositely arranged with described first substrate;
One grid is located between described first substrate and the described second substrate;
One insulating barrier is located between described grid and the described first substrate;
One metal-oxide semiconductor (MOS) pattern is located between described first substrate and the described second substrate;
One source pole and a drain electrode are located between described insulating barrier and the described first substrate; And
One polyimide is located between described metal-oxide semiconductor (MOS) pattern and the described first substrate.
10. active matrix display panel as claimed in claim 9 is characterized in that, also comprises:
One liquid crystal layer is located between described first substrate and the second substrate;
One pixel electrode layer is located between described polyimide and the described liquid crystal layer; And
One both alignment layers is located between described pixel electrode layer and the described liquid crystal layer.
11. active matrix display panel as claimed in claim 9 is characterized in that, also comprises an organic electric-excitation luminescent unit, is located between described polyimide and the described first substrate.
12. active matrix display panel as claimed in claim 9 is characterized in that, described metal-oxide semiconductor (MOS) pattern comprises indium oxide gallium zinc.
13. active matrix display panel as claimed in claim 9 is characterized in that, described metal-oxide semiconductor (MOS) pattern is located between described gate insulator and the described source electrode and between described gate insulator and the described drain electrode.
14. active matrix display panel as claimed in claim 13, it is characterized in that, also comprise one first etching stopping pattern, be located between described polyimide and the described metal-oxide semiconductor (MOS) pattern, and described the first etching stopping pattern has a first film density.
15. active matrix display panel as claimed in claim 14, it is characterized in that, also comprise one second etching stopping pattern, be located between described the first etching stopping pattern and the described metal-oxide semiconductor (MOS) pattern, and described the second etching stopping pattern has one second density of film, less than described the first film density.
16. active matrix display panel as claimed in claim 9, it is characterized in that, described metal-oxide semiconductor (MOS) pattern is located between described source electrode and the described polyimide and between described drain electrode and the described polyimide, and extends between described source electrode and the described drain electrode.
17. active matrix display panel as claimed in claim 9 is characterized in that, described grid is located between described polyimide and the described first substrate.
18. active matrix display panel as claimed in claim 17 is characterized in that, described insulating barrier and described polyimide have two perforation, and described source electrode contacts with described metal-oxide semiconductor (MOS) pattern by each described perforation respectively with described drain electrode.
19. active matrix display panel as claimed in claim 9, it is characterized in that, also comprise a frame glue, be located between described first substrate and the described second substrate, and be used for binding described first substrate and described second substrate, and described frame glue not with described pi ply.
20. the manufacture method of a thin-film transistor is characterized in that, comprising:
On a substrate, form a grid;
On described grid, cover an insulating barrier;
On described insulating barrier, form a metal-oxide semiconductor (MOS) pattern, one source pole and a drain electrode; And
In described metal-oxide semiconductor (MOS) pattern, described source electrode and described drain electrode, cover a polyimide.
21. the manufacture method of thin-film transistor as claimed in claim 20 is characterized in that, the step that forms described metal-oxide semiconductor (MOS) pattern, described source electrode and described drain electrode comprises:
On described insulating barrier, form described metal-oxide semiconductor (MOS) pattern; And
On described metal-oxide semiconductor (MOS) pattern, form described source electrode and described drain electrode.
22. the manufacture method of thin-film transistor as claimed in claim 21, it is characterized in that, between the step of the step that forms described metal-oxide semiconductor (MOS) pattern and the described source electrode of formation and described drain electrode, described method also is included in and forms one first etching stopping pattern on the described metal-oxide semiconductor (MOS) pattern.
23. the manufacture method of thin-film transistor as claimed in claim 22, it is characterized in that, between the step of the step that forms described metal-oxide semiconductor (MOS) pattern and the described source electrode of formation and described drain electrode, described method also is included in and forms one second etching stopping pattern between described the first etching stopping pattern and the described metal-oxide semiconductor (MOS) pattern, wherein said the first etching stopping pattern has a first film density, and described the second etching stopping pattern has one second density of film, less than described the first film density.
24. the manufacture method of thin-film transistor as claimed in claim 23, it is characterized in that, the step that forms described the second etching stopping pattern comprises a physical gas-phase deposition, and the step that forms described the first etching stopping pattern comprises a chemical vapor deposition method.
25. the manufacture method of thin-film transistor as claimed in claim 21 is characterized in that, the step that forms described metal-oxide semiconductor (MOS) pattern comprises:
On described insulating barrier, sequentially form a metal oxide semiconductor layer and one first etching stop layer;
Described the first etching stop layer of patterning is to form one first etching stopping pattern; And
The described metal oxide semiconductor layer of patterning is to form described metal-oxide semiconductor (MOS) pattern.
26. the manufacture method of thin-film transistor as claimed in claim 20 is characterized in that, the step that forms described metal-oxide semiconductor (MOS) pattern, described source electrode and described drain electrode comprises:
On described insulating barrier, form described source electrode and described drain electrode; And
In described insulating barrier, described source electrode and described drain electrode, form described metal-oxide semiconductor (MOS) pattern.
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