CN103378830A - Power-on reset (POR) circuit - Google Patents
Power-on reset (POR) circuit Download PDFInfo
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- CN103378830A CN103378830A CN2012101127439A CN201210112743A CN103378830A CN 103378830 A CN103378830 A CN 103378830A CN 2012101127439 A CN2012101127439 A CN 2012101127439A CN 201210112743 A CN201210112743 A CN 201210112743A CN 103378830 A CN103378830 A CN 103378830A
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Abstract
The invention discloses a power-on reset (POR) circuit which comprises a band-gap reference circuit and a comparison circuit. The band-gap reference circuit includes a first branch circuit, a second branch circuit and an operational amplifier circuit. The first branch circuit, between a VDD and the ground, includes a first PMOS transistor and a first bias current module, which are sequentially arranged, and further includes a charging module that is connected in parallel with the first bias current module. The second branch circuit, between the VDD and the ground, includes a second PMOS transistor and a second bias current module which are sequentially connected. A drain electrode of the firs PMOS transistor is connected with a first input end of the operational amplifier circuit and a first input end of the comparison circuit. A drain electrode of the second PMOS transistor is connected with a second input end of the operational amplifier circuit and a second input end of the comparison circuit. An output end of the operational amplifier circuit is connected with a gate electrode of the first PMOS transistor and a gate electrode of the second PMOS transistor. During a work process, with the rise of the VDD, voltage values output to the comparison circuit by the first branch circuit and the second branch circuit become equal to each other, and the comparison circuit outputs a power-on reset signal when the two input voltage values are determined to be equal.
Description
Technical field
The present invention relates to integrated circuit, relate in particular to electrify restoration circuit.
Background technology
Electrify restoration circuit (Power-on Reset, POR) is widely used in various digital circuits and the system, and its Main Function is the correct startup that guarantees whole circuit power up.In system's power up, when supply voltage was higher than logic low and does not reach normal working voltage, improper upset can occur and cause logical miss in the circuit logic door.Electrify restoration circuit keeps low level exactly always in the supply voltage uphill process, until supply voltage just produces rapidly a high level after reaching the normal working voltage of system regulation, start whole system.In microwave radio identification (UHF RFID) system, because the particularity of system, requirement to electrify restoration circuit is higher, UHF rfid system power consumption is extremely low, therefore supply voltage is also lower, and power consumption also requires lower (1uA is following) to require electrify restoration circuit need to be operated under the lower voltage simultaneously.
Existing electrify restoration circuit generally has following several implementation:
Scheme one, as shown in Figure 1 realizes by the RC charging, POR output high level when the voltage Vc on the capacitor C reaches the turnover level of inverter, and release resets.
Scheme two, on the basis of scheme one, add the clamper electrify restoration circuit guarantee supply voltage be higher than the clamper tube threshold value and the time again to the capacitor C charging, cause the Problem of Failure that resets to improve slowly to power on.
Scheme three, based on the electrify restoration circuit of clock supervision, by power-on reset signal supervisory control system clock, design a RC oscillator and after the RC starting of oscillation, discharge reset signal, avoid system to be in nondeterministic statement.
If above scheme is applied to the UHF rfid system, then there is at least respectively following problem:
Scheme one: when supply voltage rises when slow, the electrify restoration circuit leaping voltage occurs seriously to offset downward, and reset function can occur and lose efficacy when power down powers on again fast; And in the situation that flow-route and temperature changes, it is also larger to detect voltage deviation, and reliability is low.
Scheme two: the clamp circuit of setting up can consume dc power, and then increases the power consumption of reset circuit, can not satisfy the requirement of low-power consumption; This circuit requirement supply voltage is higher than 2 times of threshold voltages at least in addition, is not suitable for low pressure applications.
Scheme three: although the resetting time of this circuit is flexible, need simulation that initial reset signal is provided, also need in addition to increase the RC oscillator, circuit is complicated, and area occupied is large, and use cost is higher.
Summary of the invention
The invention provides simple in structure, good reliability, electrify restoration circuit that power consumption is little.
The electrify restoration circuit that one embodiment of the invention provide comprises band-gap reference circuit and comparison circuit.Described band-gap reference circuit comprises the first branch road, the second branch road and discharge circuit; Described the first branch road comprises PMOS pipe, the first bias current module and charging module, the source electrode of a described PMOS pipe is connected with VDD, drain electrode is connected with the input of described the first bias current module, the output head grounding of described the first bias current module, described charging module is in parallel with described the first bias current module, the drain electrode of a described PMOS pipe also with the first input end of described discharge circuit be connected the first input end of comparison circuit and be connected, the output of described discharge circuit is connected with the grid of described the first metal-oxide-semiconductor; Described the second branch road comprises the 2nd POMS pipe, the second bias current module, and the source electrode of described the 2nd PMOS pipe is connected with VDD, and drain electrode is connected the output head grounding of described the second bias current module with the input of described the second bias current module; The drain electrode of described the 2nd PMOS pipe also with the second input of described discharge circuit be connected the second input of comparison circuit and be connected, the output of described discharge circuit also is connected with the grid of described the 2nd PMOS pipe; Described discharge circuit is used for adjusting according to the magnitude of voltage of described the first branch road and the input of described the second branch road the grid voltage of described PMOS pipe and described the 2nd PMOS pipe; Described comparison circuit is used for the magnitude of voltage of more described the first branch road and the input of described the second branch road, judges whether by output output power-on reset signal according to comparative result.
In an embodiment of the present invention, described the first bias current module comprises NMOS pipe, and the drain electrode of a described PMOS pipe is connected with the drain and gate of a described NMOS pipe, the source ground of a described NMOS pipe; Described the second bias current module comprises the 2nd NMOS pipe and resistance R, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe, the source electrode of described the 2nd NMOS pipe is by described grounding through resistance, and the grid of described the 2nd NMOS pipe is connected with the drain electrode of a described PMOS pipe.
In an embodiment of the present invention, described the first bias current module comprises a NPN type triode, and the drain electrode of a described PMOS pipe is connected with base stage with the collector electrode of a described NPN type triode, the grounded emitter of a described NPN type triode; Described the second bias current module comprises the 2nd NPN type triode and resistance R, the drain electrode of described the 2nd PMOS pipe is connected with an end of described resistance R, the other end of described resistance R is connected with base stage with the collector electrode of described the 2nd NPN type triode, the grounded emitter of described the 2nd NPN type triode.
In an embodiment of the present invention, described the first bias current module comprises the first positive-negative-positive triode, and the drain electrode of a described PMOS pipe is connected with the emitter of described the first positive-negative-positive triode, the collector electrode of described the first positive-negative-positive triode and base earth; Described the second bias current module comprises the second positive-negative-positive triode and resistance R, the drain electrode of described the 2nd PMOS pipe is connected with an end of described resistance R, the other end of described resistance R is connected with the emitter of described the second positive-negative-positive triode, collector electrode and the base earth of described the 2nd NPN type triode.
In an embodiment of the present invention, described charging module comprises electric capacity, and the two ends of described electric capacity are connected with ground with the drain electrode of a described PMOS pipe respectively.
In an embodiment of the present invention, also comprise delay circuit, the input of described delay circuit is connected with the output of described comparison circuit, is used for the power-on reset signal of described comparison circuit output is carried out exporting behind the delay disposal.
In an embodiment of the present invention, the described discharge circuit grid voltage of adjusting described PMOS pipe and described the 2nd PMOS pipe according to the magnitude of voltage of described the first branch road and described the second branch road input comprises:
Whether the magnitude of voltage of more described the first branch road of described discharge circuit input less than the magnitude of voltage of described the second branch road input, in this way, and described transmittal circuit outputs lower electrical level; If whether the magnitude of voltage of more described the first branch road input of described discharge circuit equals the magnitude of voltage of described the second branch road input, the intermediate level between output VDD and the VSS.
In an embodiment of the present invention, described comparison circuit judges whether to comprise by output output power-on reset signal according to described comparative result:
Described comparison circuit judges that whether the magnitude of voltage of described the first branch road input equates with the magnitude of voltage of described the second branch road input, in this way, then exports power-on reset signal.
The electrify restoration circuit that one embodiment of the invention provides in the course of the work, along with VDD rises, the first branch road and the second branch road conducting, and at ascent stage, because the first branch road includes charging module, cause the Current rise on the first branch road slow than the Current rise on the second branch road, and the magnitude of voltage that the first branch road inputs to discharge circuit is less than the magnitude of voltage that the second branch road inputs to discharge circuit, discharge circuit is then further adjusted the grid voltage of PMOS pipe and the 2nd PMOS pipe according to the comparative result of the two, make VDD when rising to the stabilization sub stage, electric current on the first branch road and the second branch road equates, the magnitude of voltage that two branch roads are exported to comparison circuit equates that also comparison circuit is exported power-on reset signal by output when two magnitudes of voltage of judging input equate.
The present invention possesses following advantage at least:
Electrify restoration circuit among the present invention comprise band-gap reference circuit can and system's (for example UHF rfid system) share, only need to set up a simple comparison circuit on this basis can realize the level detection function and then export accurately power-on reset signal, area simple in structure, that take is few, and use cost is low;
2. after the band-gap reference circuit of electrify restoration circuit only is operated in the stabilization sub stage among the present invention, the magnitude of voltage of the two branch roads output that it comprises just can equate, comparison circuit only in the situation that the output voltage values that detects two branch roads equates, just can be exported power-on reset signal.The voltage that is the electrify restoration circuit among the present invention is the electrical voltage point of band-gap reference circuit steady operation, therefore the speed of power vd D rise time can not affect the electrify restoration circuit leaping voltage, power-on reset signal release time and power supply electrifying speed are irrelevant, better reliability;
3. the band-gap reference stable operating voltage among the present invention lower (about 0.7V), electrify restoration circuit release voltage point is also lower, and the power consumption of the electrify restoration circuit among the present invention is also lower, its current sinking can well satisfy the requirement of UHF rfid system low pressure applications and low-power consumption in 1uA.
Description of drawings
Fig. 1 is the structural representation of existing electrify restoration circuit;
The structural representation of the electrify restoration circuit that Fig. 2 provides for one embodiment of the invention;
The structural representation of the electrify restoration circuit that Fig. 3 provides for one embodiment of the invention;
The structural representation of the electrify restoration circuit that Fig. 4 provides for one embodiment of the invention;
The structural representation of the electrify restoration circuit that Fig. 5 provides for one embodiment of the invention;
The structural representation of the electrify restoration circuit that Fig. 6 provides for one embodiment of the invention;
The structural representation of the amplifying circuit in the electrify restoration circuit that Fig. 7 provides for one embodiment of the invention;
The structural representation of the amplifying circuit in the electrify restoration circuit that Fig. 8 provides for one embodiment of the invention.
Embodiment
By reference to the accompanying drawings the present invention is described in further detail below by embodiment.
See also Fig. 2, the electrify restoration circuit that the technical program one embodiment provides comprises band-gap reference circuit 1 and comparison circuit 2; Band-gap reference circuit 1 comprises the first branch road 11, the second branch road 12 and discharge circuit 13, the first branch road 11 comprises the PMOS pipe that is connected successively between VDD and ground VSS, the first bias current module, also comprise the charging module in parallel with the first bias current module, concrete, the source electrode of the one PMOS pipe is connected with VDD, the drain electrode of the one PMOS pipe is connected with the input of the first bias current module, the output head grounding of described the first bias current module, the drain electrode of the one POMS pipe also with the first input end of described discharge circuit 13 be connected the input of comparison circuit 2 and be connected, the output of discharge circuit 13 is connected with the grid of a POMS pipe; The second branch road comprises the 2nd POMS pipe, the second bias current module that is connected successively between VDD and ground, concrete, the source electrode of the 2nd PMOS pipe is connected with VDD, the drain electrode of the 2nd PMOS pipe is connected with the input of the second bias current module, the output head grounding of the second bias current module, the drain electrode of the 2nd PMOS pipe also are connected with the second input that the second input of discharge circuit 13 is connected with comparison circuit; The output of discharge circuit 13 also is connected with the grid of the 2nd PMOS pipe.Rising along with VDD, band-gap reference circuit 1 enters stationary operational phase by the voltage ascent stage gradually, and at the voltage ascent stage, because the first branch road 11 has the charging module in parallel with the first bias current module, therefore the Current rise speed of the first bias current module on the first branch road 11 does not have Current rise fast on the second bias current module on the second branch road 12, and the magnitude of voltage that the first branch road 11 inputs to discharge circuit 13 and comparison circuit 2 also inputs to the magnitude of voltage of discharge circuit 13 and comparison circuit 2 less than the second branch road 12; Discharge circuit 13 is used for adjusting according to the magnitude of voltage of the first branch road 11 and 12 inputs of the second branch road the grid voltage of PMOS pipe and the 2nd PMOS pipe, when making band-gap reference circuit 1 be operated in the stabilization sub stage, the first branch road 11 that it comprises and the output current of the second branch road 12 equate, and then the magnitude of voltage of the first branch road 11 and the second branch road 12 input computing discharge circuits 13 and comparison circuit 2 are equated; 2 of comparison circuits are used for comparing the magnitude of voltage of the first branch road 11 and 12 inputs of the second branch road, judge whether by output output power-on reset signal according to comparative result, when being specially the magnitude of voltage of judging the input of two branch roads and equating, the output power-on reset signal, otherwise, do not export power-on reset signal.And as the above analysis, only after band-gap reference circuit 1 reaches stable operating voltage, the magnitude of voltage that the first branch road 11 and the second branch road 12 input to comparison circuit 2 just can equate, and the stable operating voltage of band-gap reference circuit 1 point is electrify restoration circuit voltage jump point, therefore the speed of power vd D rise time can not affect the electrify restoration circuit leaping voltage, after as long as the power supply vdd voltage reaches the stable operating voltage point of band-gap reference circuit 1, electrify restoration circuit discharges repositioning information, irrelevant with the power vd D speed that powers on, can not change because of leaping voltage and affect too greatly system works, better reliability.
For a better understanding of the present invention, on the basis of above-described embodiment, several circuit diagrams that more specifically are more readily understood and operation principle are provided, and the present invention will be further described.
See also Fig. 3, in the electrify restoration circuit that one embodiment of the invention provides, the PMOS pipe that the first branch road 11 comprises is the pipe of the P1 among Fig. 3, the first bias current module is NOMS pipe N1, the source electrode of P1 pipe is connected with power vd D, the drain electrode of P1 pipe is connected with the drain and gate of N1 pipe, it is the comparator C OMP shown in Fig. 3 that the drain electrode of P1 pipe also is connected with comparison circuit with the first input end of discharge circuit (be shown in Figure 3 operational amplifier OPA) 13) 2 first input end is connected the source ground VSS of N1 pipe; The charging module that the first branch road comprises is in parallel with the N1 pipe, and the input that is specially charging module is connected output head grounding with the drain electrode of N1 pipe; The output of discharge circuit is connected with the grid of P1 pipe.
In electrify restoration circuit shown in Figure 3, the 2nd PMOS pipe that the second branch road 12 comprises is the P2 pipe, the second bias current module is that the 2nd NOMS pipe N2 and resistance R form, the source electrode of P2 pipe is connected with power vd D, the drain electrode of P2 pipe is connected with the drain electrode of N2 pipe, and the drain electrode of P2 pipe also is connected with the second input that the second input of discharge circuit 13 is connected with comparison circuit, the source ground VSS of N2 pipe, the grid of N2 pipe is connected with the drain electrode of P1 pipe, and namely the grid voltage of N1 pipe equates with the grid voltage of N2 pipe; The output of discharge circuit is connected with the grid of P2 pipe.
The course of work of electrify restoration circuit shown in Figure 3 is as follows: just begun power vd D and powered on, band-gap reference circuit starts, discharge circuit 13 output output low levels in the start-up course, and namely its output is dragged down; Its implementation that drags down can be selected according to actual working environment, for example under some operational environment, when electrify restoration circuit also is provided with start-up circuit, can realize by the start-up circuit that arranges, see also 13 shown parts among Fig. 3, netA voltage is that 0, N41 grid voltage is VDD when VDD starts, N41 opens, VBP moves low level to, and netA voltage raises after stablizing, and the N4 grid voltage reduces, N4 closes, and start-up circuit cuts out.Power vd D powers on, P1, P2 manages unlatching, two branch currents slowly start, in the start-up course, because the first branch road 11 comprises the charging module in parallel with the N1 pipe, in start-up course, charging module can charge first part energy is stored, cause the speed (i.e. electric current on the first branch road) of the Current rise on the N1 pipe in parallel with it slow than the electric current on the N2 pipe (i.e. electric current on the second branch road), according to the relation between electric current and metal-oxide-semiconductor gate source voltage and the leakage primary voltage as can be known, this moment, the N1 pipe was identical with N2 pipe gate source voltage, namely the current conducting resistance of two pipes is identical, and the drain-source current of N2 pipe is greater than the drain-source current of N1 pipe, the voltage of discharge circuit 13 input netB (i.e. the magnitude of voltage of the second branch road input) is higher than the voltage (i.e. the magnitude of voltage of the first branch road input) of input netA at this moment, in like manner, the magnitude of voltage of the second branch road input comparison circuit 2 is also inputted the magnitude of voltage of comparison circuit 1 greater than the first branch road, the magnitude of voltage of comparison circuit 2 the two input of comparison is also unequal, does not therefore discharge power-on reset signal; And discharge circuit 13 compares the magnitude of voltage of the second branch road input greater than the magnitude of voltage of the first branch road input at this moment, its output low level, and the electric current on the first branch road 11 continues increase; To adjust the grid voltage of P1 pipe and P2 pipe, along with vdd voltage rises, because the feedback effect of discharge circuit 13, after vdd voltage arrives certain phase (namely reaching the band-gap reference stable operating voltage), the drain-source electrode current of N1 pipe, N2 pipe is identical, that is to say that the first branch road is identical with the electric current of the second branch road, this moment, the output current of the first branch road and the second branch road was PTPA (proportional to absolute temperature with supply independent, be directly proportional with absolute temperature) electric current, concrete derivation is as follows:
Behind the band-gap reference circuit working stability, N1 pipe and N2 pipe are operated in sub-threshold region, produce bias current, relation by sub-threshold region gate source voltage and metal-oxide-semiconductor electric current can obtain the band-gap reference output current for PTAT (the proportional to absolute temperature of supply independent, be directly proportional with absolute temperature) electric current, specific as follows:
Be operated in the metal-oxide-semiconductor electric current I of sub-threshold region
DAnd V
GSRelation be:
Wherein,
Be the breadth length ratio of metal-oxide-semiconductor, I
D0Be the parameter relevant with technique; N is the imperfect factor, and its representative value is 1.5;
Wherein, k/q=0.086mV/K, V are (voltage), and K is temperature unit Kelvin, and T is temperature, and q is the unit amount of electrons).
Because there is following relation in the grid voltage of N1 and N2 behind the band-gap reference circuit working stability:
V
GS1=V
GS2+ I
Out* R can obtain this formula substitution following formula:
Wherein,
With
Be respectively the breadth length ratio of NI pipe and N2 pipe, by following formula as can be known, behind the band-gap reference circuit working stability, the output current Iout of the first branch road 11 and the second branch road 12 namely is an electric current with supply independent.And further the suitable resistance R temperature coefficient of choosing also can further obtain zero a warm electric current, and this zero warm electric current can be for other circuit.The breadth length ratio that suitably designs the value of resistance R and N1 pipe and N2 pipe can then can obtain the bias current of nA level, so the electrify restoration circuit among the present invention is low in energy consumption, can satisfy the requirement of low-power consumption.
This moment is because the output current of the first branch road 11 and the second branch road 12 is equal, according to above-mentioned analysis as can be known, the voltage of the at this moment netA input of discharge circuit 13 and netB input input also equates, the magnitude of voltage of discharge circuit 13 comparisons this moment the second branch road input equals the magnitude of voltage of the first branch road input, it exports VDD/2, and the electric current on the first branch road 11 continues to increase; The magnitude of voltage that the first branch road 11 is input to discharge circuit 13 and comparison circuit 2 equates with the magnitude of voltage that the second branch road 12 is input to discharge circuit 13 and comparison circuit 2.Comparison circuit 2 judges that by comparing the magnitude of voltage of two branch roads input the magnitude of voltage of the current input of two branch roads equates, the output high level namely discharges power-on reset signal; Otherwise output low level.
Comparison circuit output high level discharged power-on reset signal when the magnitude of voltage of exporting to comparison circuit 2 by two branch roads of band-gap reference circuit among the present invention equated, comparison circuit 2 output low levels when the magnitude of voltage of the two output differs larger, the voltage fluctuation that can avoid the first branch road and the second branch road in the power vd D power up to export to comparison circuit 2 causes exporting the situation of reset signal mistake upset, and only behind the band-gap reference working stability, comparison circuit 2 is just exported high level and is discharged power-on reset signal, therefore power-on reset signal release time and power supply electrifying speed are irrelevant, better reliability.
The first bias current module and the second bias current module also can be comprised of other intimate elements, for example: as shown in Figure 4: the PMOS pipe that the first branch road 11 comprises is the pipe of the P1 among Fig. 4, the first bias current module is a NPN type triode Q1, the source electrode of P1 pipe is connected with power vd D, the drain electrode of P1 pipe is connected with base stage with the collector electrode of Q1 pipe, it is the comparator C OMP shown in Fig. 4 that the drain electrode of P1 pipe also is connected with comparison circuit with the first input end of discharge circuit (be shown in Figure 4 operational amplifier OPA) 13) 2 first input end is connected the grounded emitter VSS of Q1 pipe; The charging module that the first branch road comprises is in parallel with the Q1 pipe, and the input that is specially charging module is connected output head grounding VSS with the collector electrode of Q1 pipe; The output of discharge circuit is connected with the grid of P1 pipe.
In electrify restoration circuit shown in Figure 4, the 2nd PMOS pipe that the second branch road 12 comprises is the P2 pipe, the second bias current module is that the 2nd NPN type triode Q2 and resistance R form, the source electrode of P2 pipe is connected with power vd D, the end of the drain electrode contact resistance R of P2 pipe connects, the other end of resistance R is connected with base stage with the collector electrode of Q2 pipe, the grounded emitter VSS of the 2nd NPN type triode Q2.The drain electrode of P2 pipe also is connected with the second input that the second input of discharge circuit 13 is connected with comparison circuit, and the output of discharge circuit is connected with the grid of P2 pipe.
Again for example as shown in Figure 5: the PMOS pipe that the first branch road 11 comprises is the pipe of the P1 among Fig. 5, the first bias current module is the first positive-negative-positive triode Q3, the source electrode of P1 pipe is connected with power vd D, the drain electrode of P1 pipe is connected with the emitter of Q3 pipe, the drain electrode of P1 pipe also is connected with the first input end that the first input end of discharge circuit 13 is connected with comparison circuit, the emitter of Q3 pipe and base earth VSS; The charging module that the first branch road comprises is in parallel with the Q3 pipe, and the input that is specially charging module is connected output head grounding VSS with the emitter of Q3 pipe; The output of discharge circuit is connected with the grid of P1 pipe.
In electrify restoration circuit shown in Figure 5, the 2nd PMOS pipe that the second branch road 12 comprises is the P2 pipe, the second bias current module is that the second positive-negative-positive triode Q4 and resistance R form, the source electrode of P2 pipe is connected with power vd D, the end of the drain electrode contact resistance R of P2 pipe connects, the other end of resistance R is connected with the emitter of Q2 pipe, the collector electrode of the second positive-negative-positive triode Q4 and base earth VSS.The drain electrode of P2 pipe also is connected with the second input that the second input of discharge circuit 13 is connected with comparison circuit, and the output of discharge circuit is connected with the grid of P2 pipe.
As from the foregoing, Fig. 4 compares with reset circuit shown in Figure 3 with electrify restoration circuit shown in Figure 5, difference is, the former two has replaced the NMOS pipe among Fig. 3 with NPN type triode and positive-negative-positive triode respectively, the operation principle of Fig. 4 and electrify restoration circuit shown in Figure 5 is identical with the operation principle of electrify restoration circuit shown in Figure 3, does not repeat them here.
Charging module set-up mode among the present invention can specifically be selected according to actual conditions, for example can directly select capacitor C as charging module, see also electrify restoration circuit shown in Figure 6, the charging module of the first branch road 11 is capacitor C, one end of capacitor C is connected with the drain electrode of N1 pipe, other end ground connection is in parallel with the N1 pipe.
The specific implementation of comparison circuit 2 of the present invention also can comprise multiple, as long as can realize exporting high level or low level according to the comparative result selection of the magnitude of voltage of the first branch road 11 and the input of the second branch road 12, do simple explanation as an example of the dual mode of specific implementation example in the present embodiment:
See also Fig. 7, it is a kind of specific implementation of the comparison circuit 2 among Fig. 6, and the tail current of comparator is obtained by N1 mirror image N5, and voltage netA and the netB of the first branch road 11 and 12 inputs of the second branch road form respectively the two-way electric current I
AAnd I
B, and respectively mirror image to NMOS manage N7, the N8 electric current is m*I
A, I
A, PMOS pipe P6, P7 electric current are I
B, n*I
B, N7, N8, P6, P7 form respectively two comparators, work as I
B＜m＜I
AThe time C point output low level, the N9 pipe is closed, as n＞I
B＞I
AThe time, OUT exports high level, so comparator is exported high level when electric current satisfies, other situation output low level reaches the requirement of comparator, can carry out certain filter function simultaneously.
See also Fig. 8, Figure 8 shows that the another kind of implementation of comparison circuit, the difference of itself and comparison circuit shown in Figure 7 is to replace the N9 among Fig. 7 to realize comparing function with logical device.
In addition, for discharging, the power-on reset signal that guarantees the stable rear electrify restoration circuit output of supply voltage opens again other circuit, further the assurance system works normally, electrify restoration circuit among the present invention also can further comprise delay circuit, the output of the comparison circuit 2 in delay circuit and the electrify restoration circuit shown in above-mentioned each figure is connected, the power-on reset signal of comparison circuit 2 outputs is exported through after certain delay, guaranteeing that VDD powers on opens other functional circuits behind the rear wait certain hour again, and then the assurance system sequence, the reliability of raising system works.
Above content is the further description of the present invention being done in conjunction with concrete execution mode, can not assert that implementation of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (8)
1. an electrify restoration circuit comprises band-gap reference circuit and comparison circuit, and described band-gap reference circuit comprises the first branch road, the second branch road and discharge circuit; Described the first branch road comprises PMOS pipe, the first bias current module and charging module, the source electrode of a described PMOS pipe is connected with VDD, drain electrode is connected with the input of described the first bias current module, the output head grounding of described the first bias current module, described charging module is in parallel with described the first bias current module, the drain electrode of a described PMOS pipe also with the first input end of described discharge circuit be connected the first input end of comparison circuit and be connected, the output of described discharge circuit is connected with the grid of described the first metal-oxide-semiconductor; Described the second branch road comprises the 2nd POMS pipe, the second bias current module, and the source electrode of described the 2nd PMOS pipe is connected with VDD, and drain electrode is connected the output head grounding of described the second bias current module with the input of described the second bias current module; The drain electrode of described the 2nd PMOS pipe also with the second input of described discharge circuit be connected the second input of comparison circuit and be connected, the output of described discharge circuit also is connected with the grid of described the 2nd PMOS pipe; Described discharge circuit is used for adjusting according to the magnitude of voltage of described the first branch road and the input of described the second branch road the grid voltage of described PMOS pipe and described the 2nd PMOS pipe; Described comparison circuit is used for the magnitude of voltage of more described the first branch road and the input of described the second branch road, judges whether by output output power-on reset signal according to comparative result.
2. electrify restoration circuit as claimed in claim 1 is characterized in that, described the first bias current module comprises NMOS pipe, and the drain electrode of a described PMOS pipe is connected with the drain and gate of a described NMOS pipe, the source ground of a described NMOS pipe; Described the second bias current module comprises the 2nd NMOS pipe and resistance R, the drain electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe, the source electrode of described the 2nd NMOS pipe is by described grounding through resistance, and the grid of described the 2nd NMOS pipe is connected with the drain electrode of a described PMOS pipe.
3. electrify restoration circuit as claimed in claim 1, it is characterized in that, described the first bias current module comprises a NPN type triode, and the drain electrode of a described PMOS pipe is connected with base stage with the collector electrode of a described NPN type triode, the grounded emitter of a described NPN type triode; Described the second bias current module comprises the 2nd NPN type triode and resistance R, the drain electrode of described the 2nd PMOS pipe is connected with an end of described resistance R, the other end of described resistance R is connected with base stage with the collector electrode of described the 2nd NPN type triode, the grounded emitter of described the 2nd NPN type triode.
4. electrify restoration circuit as claimed in claim 1, it is characterized in that, described the first bias current module comprises the first positive-negative-positive triode, and the drain electrode of a described PMOS pipe is connected with the emitter of described the first positive-negative-positive triode, the collector electrode of described the first positive-negative-positive triode and base earth; Described the second bias current module comprises the second positive-negative-positive triode and resistance R, the drain electrode of described the 2nd PMOS pipe is connected with an end of described resistance R, the other end of described resistance R is connected with the emitter of described the second positive-negative-positive triode, collector electrode and the base earth of described the 2nd NPN type triode.
5. such as each described electrify restoration circuit of claim 1-4, it is characterized in that described charging module comprises electric capacity, the two ends of described electric capacity are connected with ground with the drain electrode of a described PMOS pipe respectively.
6. such as each described electrify restoration circuit of claim 1-4, it is characterized in that, also comprise delay circuit, the input of described delay circuit is connected with the output of described comparison circuit, is used for the power-on reset signal of described comparison circuit output is carried out exporting behind the delay disposal.
7. such as each described electrify restoration circuit of claim 1-4, it is characterized in that the grid voltage that described discharge circuit is adjusted described PMOS pipe and described the 2nd PMOS pipe according to the magnitude of voltage of described the first branch road and the input of described the second branch road comprises:
Whether the magnitude of voltage of more described the first branch road of described discharge circuit input less than the magnitude of voltage of described the second branch road input, in this way, and described transmittal circuit outputs lower electrical level; If whether the magnitude of voltage of more described the first branch road input of described discharge circuit equals the magnitude of voltage of described the second branch road input, the intermediate level between output VDD and the VSS.
8. such as each described electrify restoration circuit of claim 1-4, it is characterized in that described comparison circuit judges whether to comprise by output output power-on reset signal according to described comparative result:
Described comparison circuit judges that whether the magnitude of voltage of described the first branch road input equates with the magnitude of voltage of described the second branch road input, in this way, then exports power-on reset signal.
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| CN201210112743.9A CN103378830B (en) | 2012-04-17 | 2012-04-17 | Electrification reset circuit |
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| CN201210112743.9A CN103378830B (en) | 2012-04-17 | 2012-04-17 | Electrification reset circuit |
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| CN103378830A true CN103378830A (en) | 2013-10-30 |
| CN103378830B CN103378830B (en) | 2016-08-24 |
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| CN103997323A (en) * | 2014-06-09 | 2014-08-20 | 上海华力微电子有限公司 | Reset circuit low in power consumption and high in stability |
| CN106356098A (en) * | 2015-07-13 | 2017-01-25 | 爱思开海力士有限公司 | Voltage level shifter, and embedded nonvolatile memory and system using the same |
| WO2018014493A1 (en) * | 2016-07-20 | 2018-01-25 | 珠海全志科技股份有限公司 | Comparator and relaxation oscillator |
| CN108023581A (en) * | 2016-10-28 | 2018-05-11 | 亚德诺半导体集团 | Small area low-power electrification reset circuit |
| CN108370216A (en) * | 2015-10-26 | 2018-08-03 | 戴洛格半导体公司 | Switch power converter with zero current when startup |
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| CN113437955A (en) * | 2020-03-23 | 2021-09-24 | 意法半导体股份有限公司 | Power-on reset circuit and corresponding electronic equipment |
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| CN106356098B (en) * | 2015-07-13 | 2020-10-30 | 爱思开海力士有限公司 | Voltage level shifter and embedded non-volatile memory and system using the same |
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| CN112104349A (en) * | 2019-06-17 | 2020-12-18 | 国民技术股份有限公司 | Power-on reset circuit and chip |
| CN112104349B (en) * | 2019-06-17 | 2024-01-26 | 国民技术股份有限公司 | Power-on reset circuit and chip |
| CN113437955A (en) * | 2020-03-23 | 2021-09-24 | 意法半导体股份有限公司 | Power-on reset circuit and corresponding electronic equipment |
| CN111781984A (en) * | 2020-08-29 | 2020-10-16 | 深圳市爱协生科技有限公司 | POR circuit and design method thereof |
| CN115603709A (en) * | 2022-11-21 | 2023-01-13 | 成都本原聚能科技有限公司（Cn） | Oscillation starting circuit, integrated circuit and chip |
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