CN103390544A - Method for forming hard mask layer - Google Patents
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- CN103390544A CN103390544A CN2012101470522A CN201210147052A CN103390544A CN 103390544 A CN103390544 A CN 103390544A CN 2012101470522 A CN2012101470522 A CN 2012101470522A CN 201210147052 A CN201210147052 A CN 201210147052A CN 103390544 A CN103390544 A CN 103390544A
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Abstract
The invention discloses a method for forming a hard mask layer. The method comprises providing a substrate and preforming a photoresist layer with patterns; expandingly distributing a RELACS material layer on the surface of the substrate and the surface and the side walls of the photoresist layer; performing heat treatment to form a non-water-soluble material layer on the mixing boundary between the RELACS material layer and photoresist; performing back etching to remove the RELACS material layer and the non-water-soluble material layer on the top surface of the photoresist layer to at least expose the top surface of the photoresist layer and accordingly to simply reserve part of the non-water-soluble material layer on the sides walls of the photoresist layer; removing the photoresist layer and the RELACS material layer and only reserving the part of the non-water-soluble material layer on the side walls of the photoresist layer as the hard mask layer. The method for forming the hard mask layer overcomes the problems due to utilization of PR (photoresist) masks or non-uniform-height hard masks and accordingly improves the CD (critical dimension) uniformity of subsequently-formed patterns, and meanwhile, can be compatible with traditional processes and accordingly reduces the cost.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and particularly, relate to a kind of be used to utilizing chemical shrinkage to assist resolution enhancement lithography (RELACS, Resolution Enhancement lithographyAssisted by Chemical Shrink) material to form the method for hard mask layer in semiconductor fabrication.In addition, the invention still further relates to and utilize this hard mask layer to carry out the method for the dual composition of autoregistration (SADP, Self-Aligned Double Patterning).
Background technology
Along with dimensions of semiconductor devices is constantly dwindled, photoetching critical size (CD, CriticalDimension) moves closer to the physics limit that has even surpassed optical lithography, has proposed stern challenge more to semiconductor fabrication especially photoetching technique thus.And dual composition technology also in good time and extremely, and its basic thought is that targeted graphical is divided into two, and by double exposure, obtains the photolithography limitation that single exposure can not obtain.
Dual composition technology mainly comprises following three kinds at present: the dual composition of SADP(autoregistration), LELE(photoetching-etching-photoetching-photoetching) DP and LLE(photoetching-photoetching-etching) DP.
LELE DP technology is followed photoetching-etching-photoetching-etched process sequence, its cardinal principle is: at first form first's pattern by exposure imaging on the ground floor photoresist, then by etching, this partial pattern is transferred on lower floor's hard mask material layer, and then spin coating second layer photoresist and by exposure imaging, form the second portion pattern, by etching, two parts pattern is finally transferred on target material layer finally.The embodiment of this technology is disclosed in No. 20100136784 U.S. Patent application.
LLE DP technology is also referred to as dual photoetching technique, it follows photoetching-photoetching-etched process sequence, cardinal principle is: at first utilize first mask exposure, form first's pattern on the ground floor photoresist, then spin coating second layer photoresist, then utilize second mask exposure, forms the second portion pattern on second layer photoresist, carry out finally etching and cleaning, the pattern that double exposure obtains is transferred on target material layer simultaneously.
The cardinal principle of SADP technology is: at first in preformed photoetching agent pattern both sides, form clearance wall (spacer), then remove photoetching agent pattern, and spacer pattern is transferred on target material layer, thereby make the number of patterns that can form in unit are double, namely the minimum spacing between pattern (pitch) can be decreased to 1/2nd of CD.
In above-mentioned three kinds of technology, LELE DP technology and LLE DP technology make with photoresist due to twice, thus very high to the linearity of photoresist, and therefore also make manufacturing cost improve, so that its application is limited to.And the SADP technology makes with photoresist due to single only, and can break through the physics limit of CD and make minimum spacing be decreased to 1/2nd of CD, thereby is particularly useful for making the semiconductor fabrication process of CD below 32nm.
The 6th, 383, a kind of dual composition technology of autoregistration of the RELACS of utilization material is disclosed in No. 952 United States Patent (USP)s.This technology comprises: form photoresist layer on substrate; This photoresist layer is carried out composition; Expand the cloth polymer material layer on the photoresist layer after composition; Remove the partial polymer material layer by comprehensive etch-back (blanketch back) technique, only to provide polymer (below be called as the polymer clearance wall) on the sidewall of the photoresist layer after composition; Photoresist layer after the removal composition, and keep described polymer clearance wall, as being used for further etched hard mask layer.Wherein, the polymer clearance wall forms by the RELACS technology.Particularly, the RELACS technology refers to utilize acid ingredient in photoresist and polymeric material generation cross-linking reaction and is forming one deck organic material (below be called as the RELACS material) between photoresist and polymeric material.The RELACS material is a kind of polymer that can be dissolved in deionized water, thereby, utilizing after it carries out composition as hard mask layer to target material layer, can use deionized water (for example, by rinsing (rinse) technique) with its removal.Yet, although this technology has plurality of advantages, owing to having adopted comprehensive etch back process when removing unnecessary polymeric material, so the polymer clearance wall top that obtains is taper, as shown in Figure 1.Utilize this hard mask layer with taper top to carry out composition to target material layer, can cause the height homogeneity of pattern in the target material layer after composition poor, and then cause the final performance of semiconductor device of making to reduce.
In view of the foregoing, need the dual patterning process of a kind of improved autoregistration, expectation the method can overcome the above-mentioned defect of traditional handicraft, and can be easily and the traditional cmos process compatibility.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
For solving above-mentioned problems of the prior art, the invention provides a kind of method that is used to form hard mask layer, comprising: substrate is provided, has been pre-formed the figuratum photoresist layer of tool on described substrate; Expand the auxiliary resolution of cloth chemical shrinkage and strengthen the photoetching material layer on the surface of described substrate and the surface of described photoresist layer and sidewall; Carry out heat treatment, with the compound boundary place that strengthens between photoetching material layer and described photoresist in the auxiliary resolution of described chemical shrinkage, form the non-water soluble material layer; Carry out etch-back, the auxiliary resolution of described chemical shrinkage that removal is positioned at the top surface top of described photoresist layer strengthens photoetching material layer and described non-water soluble material layer, to expose at least the top surface of described photoresist layer, thereby only keep a part in described non-water soluble material layer on the sidewall of described photoresist layer; And remove the auxiliary resolution of described photoresist layer and described chemical shrinkage and strengthen the photoetching material layer, only keep the part on the sidewall that is positioned at described photoresist layer of described non-water soluble material layer, as described hard mask layer.
Preferably, the total surface of the auxiliary resolution enhancing of described chemical shrinkage photoetching material layer is the surface higher than described photoresist layer.
Preferably, described heat treatment is processed for mixing baking, and baking temperature is that 70 ℃ ~ 130 ℃ and stoving time are 20 ~ 90 seconds.
Preferably, to strengthen the photoetching material layer be to expand cloth on the surface of the surperficial and described photoresist layer of described substrate and the sidewall by spin coating proceeding to the auxiliary resolution of described chemical shrinkage.
Preferably, the auxiliary resolution enhancing of described photoresist layer and described chemical shrinkage photoetching material layer is to remove by the photoetching process that comprises exposure, development and rinsed with deionized water step.
Preferably, described rinsed with deionized water step comprises single or twice rinsing.
Preferably, the time of each rinsing is 20 ~ 90 seconds.
Preferably, be pre-formed target material layer between described substrate and described photoresist layer.
Preferably, described method comprises and uses the hard mask layer of method formation as described in any one in claim 1 ~ 8 to shelter to carry out subsequent technique.
Preferably, described subsequent technique is etch process, ion implantation technology or selective epitaxial growth process.
The present invention further provides a kind of integrated circuit that comprises the semiconductor device of making by method as above, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
The present invention further provides a kind of electronic equipment that comprises the semiconductor device of making by method as above, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
The method according to this invention can overcome as mentioned above in the prior art due to the problem that adopts PR mask or highly inconsistent hard mask to exist, and by Twi-lithography and once can form to twice etch process little spacing (pattern of CD≤32nm), thus can reduce manufacturing cost.In addition, the method according to this invention can also be utilized traditional process equipment, for example, uses and has the lithographic equipment of the KrF excimer laser of 248nm wavelength as light source, form the little pitch pattern of CD below 32nm, thus easy and traditional cmos process compatibility.In addition, the method according to this invention is due to simple, thereby can realize reliably online technology controlling and process.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention., shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings:
Fig. 1 shows the schematic cross sectional view of existing problem in existing SADP technology;
Fig. 2 A-2E shows the schematic cross sectional view of each step in the method that is used to form according to an exemplary embodiment of the present invention hard mask layer;
Fig. 3 shows the flow chart of the exemplary embodiment of the method that is used to form according to an exemplary embodiment of the present invention hard mask layer; And
Fig. 4 A-4B shows and utilizes hard mask layer of the present invention target material layer to be carried out the schematic cross sectional view of autoregistration composition technique.
Should be noted in the discussion above that these figure are intended to illustrate the general characteristic according to the method for using in certain exemplary embodiments of the present invention, structure and/or material, and the written description that provides is below supplemented.Yet, these figure not draw in proportion, thereby may can accurately not reflect precision architecture or the characteristic of property of any given embodiment, and these figure should not be interpreted as limiting or limit the numerical value contained by exemplary embodiment according to the present invention or the scope of attribute.For example, for the sake of clarity, can dwindle or amplify relative thickness and the location of molecule, layer, zone and/or structural detail.In the accompanying drawings, use similar or identical Reference numeral to represent similar or identical element or feature.
Embodiment
Now, describe in more detail according to exemplary embodiment of the present invention with reference to the accompanying drawings.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and zone, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
Should be understood that, when element was known as " connection " or " combination " to another element, this element can directly connect or be attached to another element, perhaps can have intermediary element.Different is when element is known as " directly connection " or " directly combination " to another element, not have intermediary element.In whole accompanying drawings, identical Reference numeral represents identical element all the time.As used herein, term " and/or " comprise the combination in any of one or more relevant Listed Items and all combinations.Should explain in an identical manner for other words of describing the relation between element or layer (for example, " and ... between " and " directly exist ... between ", " with ... adjacent " and " with ... direct neighbor ", " ... on " and " directly exist ... on " etc.).
In addition, it is to be further understood that, although can use term " first ", " second " etc. to describe different elements, assembly, zone, layer and/or part here, these elements, assembly, zone, layer and/or part should not be subjected to the restriction of these terms.These terms are only that an element, assembly, zone, layer or part and another element, assembly, zone, layer or part are made a distinction.Therefore, in the situation that do not break away from instruction according to exemplary embodiment of the present invention, the first element discussed below, assembly, zone, layer or part also can be known as the second element, assembly, zone, layer or part.
For convenience of description, here can the usage space relative terms, as " ... under ", " ... on ", " following ", " in ... top ", " top " etc., be used for describing the spatial relation as element as shown in figure or feature and other elements or feature.Should be understood that, the space relative terms is intended to comprise the different azimuth in using or operating except the orientation that device is described in the drawings.For example,, if the device in accompanying drawing is squeezed, be described as being positioned as " above other elements or feature " or " on other elements or feature " after the element of " below other elements or feature " or " under other elements or feature ".Thereby exemplary term " in ... below " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and the space relative descriptors of using is here made respective explanations.
Here the term that uses is only in order to describe specific embodiment, but not the intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative also is intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
, at this, with reference to the schematic cross sectional view of the preferred embodiment (and intermediate structure) as exemplary embodiment, describe according to exemplary embodiment of the present invention.Like this, for example estimate there will be the variation of the shape that illustrates that is caused by manufacturing technology and/or tolerance.Therefore, exemplary embodiment should not be interpreted as only limiting to the concrete shape in the zone shown in this, but can also comprise for example by making the form variations that causes.For example, the injection zone that is depicted as rectangle can have rounding or the feature of bending and/or the graded of implantation concentration at its edge, and the binary of being not only from injection zone to the non-injection regions territory changes.Equally, the buried regions that forms by injection can cause at this buried regions and also can there be some injections in the zone of injecting between the surface pass through.Therefore, scheming shown zone is in fact that schematically their shape is not intended to illustrate each the regional true form in device, and is not intended to limit the scope according to exemplary embodiment of the present invention.
Unless otherwise defined, otherwise the whole terms that use here (comprising technical term and scientific terminology) all have the meaning equivalent in meaning of usually understanding with those skilled in the art.It will also be understood that, unless clearly definition here, otherwise should be interpreted as having the meaning consistent with they meanings in the association area linguistic context such as this class term of the term that defines in general dictionary, and with desirable or too formal implication, not explain them.
[exemplary embodiment]
Below, describe the method that is used for forming at semiconductor fabrication according to an exemplary embodiment of the present invention hard mask layer in detail with reference to Fig. 2 A to 2E and Fig. 3.
, with reference to Fig. 2 A to 2E, wherein show the schematic cross sectional view of each step in the method that is used to form according to an exemplary embodiment of the present invention hard mask layer.
At first, provide substrate 210.As shown in Figure 2 A, be pre-formed target material layer 220 on substrate 210, and be pre-formed the figuratum photoresist layer 230 of tool on target material layer 220.The constituent material of substrate 210 can be not doped monocrystalline silicon, the monocrystalline silicon doped with N-type or p type impurity, polysilicon, germanium silicon or silicon-on-insulator (SOI) etc.Target material layer 220 can be formed in interconnection wiring layer, gate material layers or the hard mask layer on substrate.The constituent material of described interconnection wiring layer is selected from least a in tungsten, tungsten silicide, aluminium, titanium and titanium nitride.The constituent material of described gate material layers is selected from a kind of in polysilicon and aluminium.The constituent material of described hard mask layer is selected from least a in oxide, undoped silicon glass, silicon-on-glass, SiON, SiN, SiBN, BN and high-k (k) material.Need to prove, target material layer 220 is optional but not essential, can be accepted or rejected according to actual conditions.
Then, expand auxiliary resolution enhancement lithography (RELACS) material layer 240 of cloth (spread) chemical shrinkage on the surface of the surface of target material layer 220 and photoresist layer 230 and sidewall, as shown in Fig. 2 B.Preferably, the total surface of RELACS material layer 240 is the surfaces higher than photoresist layer 230.The method that expands cloth can adopt conventional spin coating (spin coat) or spraying (spray coat).
RELACS material layer 240 consists of a kind of water-soluble polymer, and this water-soluble polymer can be modified as the non-soluble polymer material lower with photoresist generation heat cross-linking, the reaction of heat-treat condition (for example, baking condition).But need be recognized, here the RELACS material layer that uses comprises the other materials that can produce a desired effect existing or that occur in the future, as long as this material is water-soluble material and can be modified as non-water soluble material with the reaction of photoresist generation heat cross-linking under certain condition.
Then, the semiconductor structure that forms in Fig. 2 B is carried out heat treatment, make the compound boundary between RELACS material layer 240 and photoresist layer 230 that modification partly occur, thereby for example form non-water soluble material layer 234(, be insoluble in deionized water), as shown in Figure 2 C.This modification technology is known to those skilled in the art, is commonly called " RELACS technology ", therefore at this, no longer describes concrete technology method and the condition of this technology.Need explanation a bit, the heat treatment of adopting is preferably and mixes baking (mixing bake) and process, and baking temperature is that 70 ℃ ~ 130 ℃ and stoving time are 20 ~ 90 seconds.But need be recognized, the heat treatment of adopting here also can be adopted other Technologies for Heating Processing that can produce a desired effect existing or that occur in the future.
Then, carry out etch-back, removal is positioned at RELACS material layer 240 and the non-water soluble material layer 234 of the top surface top of photoresist layer 230, to expose at least the top surface of photoresist layer 230, thereby only keep a part of 234a in non-water soluble material layer 234 on the sidewall of photoresist layer 230, as shown in Fig. 2 D.The technique that etch-back adopts can be plasma etching (RIE) technique conventional in field of semiconductor manufacture.
Here, what need draw attention to is, schematic cross sectional view can be known and finds out from Fig. 2 D, and the top of a part of 234a in the non-water soluble material layer 234 that keeps is very straight, is not as shown in Figure 1 taper.
Finally, remove unmodified photoresist layer 230 and RELACS material layer 240, only keep a part of 234a in non-water soluble material layer 234.Removing method can for example make the photoresist layer modification by the blanket exposure step in conventional photoetching process, afterwards by the photoresist after the removal of the development step in conventional photoetching process modification, then remove water-soluble RELACS material layer by the rinsed with deionized water step in conventional photoetching process, thereby only keep a part of 234a in non-water soluble material layer 234 finally, as shown in Figure 2 E, as the hard mask layer that is used for subsequent technique.Wherein, in the rinsed with deionized water step, the rinsing number of times can be single or twice, and the time of each rinsing can be 20 ~ 90 seconds.In addition, those skilled in the art will be appreciated that, in order to reach the purpose of removing the water-soluble RELACS material that the heat cross-linking reaction does not occur fully, rinsed with deionized water step rinsing number of times also can be more than twice, even and each rinsing time can for 90 seconds longer, by this with the CD homogeneity of the pattern of guaranteeing follow-up formation.
Here, what need be explained is that above-mentioned every procedure all can adopt common process of the prior art, thereby need not to develop new technique, only in conjunction with prior art and legacy equipment, just can implement the method that is used to form hard mask layer according to of the present invention.In addition, the method according to this invention is due to simple, thereby can realize reliably online technology controlling and process.
, with reference to Fig. 3, wherein show the flow chart of method according to an exemplary embodiment of the present invention.
At first, in step 301, provide substrate, be pre-formed the figuratum photoresist layer of tool on described substrate.In one example, be pre-formed target material layer between described substrate and described photoresist layer.
Then, in step 302, expand cloth RELACS material layer on the surface of described substrate and the surface of described photoresist layer and sidewall.In one example, the surface of described RELACS material layer can be always higher than the surface of described photoresist layer.Described RELACS material layer can consist of water-soluble material, and described water-soluble material can be modified as non-water soluble material with photoresist generation cross-linking reaction under the process of thermal treatment condition.
Then, in step 303, carry out heat treatment, with the compound boundary place between described RELACS material layer and described photoresist, form the non-water soluble material layer.
Then, in step 304, carry out etch-back, removal is positioned at described RELACS material layer and the described non-water soluble material layer of the top surface top of described photoresist layer, to expose at least the top surface of described photoresist layer, thereby only keep a part in described non-water soluble material layer on the sidewall of described photoresist layer.
Finally, in step 305, remove the auxiliary resolution of described photoresist layer and described chemical shrinkage and strengthen the photoetching material layer, only keep the part on the sidewall that is positioned at described photoresist layer of described non-water soluble material layer, as described hard mask layer.
[beneficial effect of the present invention]
Below, the beneficial effect that is used to form the method for hard mask layer according to the present invention is described further combined with concrete application with reference to Fig. 4 A to 4B.Fig. 4 A to 4B has schematically shown and has utilized the autoregistration composition processing step of target material layer being carried out according to the hard mask layer of the inventive method formation.
As shown in Fig. 4 A, at first, form as mentioned above hard mask layer 434a by the method according to this invention on target material layer 420.
Then, use hard mask layer 434a to shelter, etching target material layer 420, with the design transfer with hard mask layer to target material layer.The technique that etching is adopted is well known in the art, does not repeat them here.
Here, need be understood that, can be formed grid structures, bit line and/or active area in target material layer 420 by the way, as the part of the semiconductor device of follow-up formation.As an example, will form the grid structure plan in target material layer 420, in this case, target material layer 420 can be conductive layer (for example, polysilicon layer) or metal level (for example, tungsten layer or tungsten silicide layer).As another example, will form bit line pattern in target material layer 420, in this case, target material layer 420 can be metal level (for example, tungsten or aluminium lamination).Need to draw attention to, also can utilize hard mask layer of the present invention to be formed with the source region pattern in target material layer 420, in this case, target material layer 420 can be Semiconductor substrate, the masking layer when this moment, hard mask layer 434a was as the active area Implantation.In addition, also can utilize the masking layer of hard mask layer of the present invention as selective epitaxial growth, and can use it for any technique that needs masking layer that occurs in the future.
Can find out, because the hard mask layer top of adopting method of the present invention to form is very straight and highly have better homogeneity, so be transferred to the height of the pattern in target material layer, also can have better homogeneity from the schematic cross sectional view of Fig. 4 B.Therefore, method of the present invention can overcome the poor problem of CD homogeneity that existing technique exists, and then can improve the performance of the semiconductor device of final formation.
[industrial applicibility of the present invention]
Can be applicable in multiple integrated circuit (IC) according to the semiconductor device of embodiment manufacturing as above.For example memory circuitry according to IC of the present invention, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in described scope of embodiments.In addition, it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. method that is used to form hard mask layer comprises:
Substrate is provided, has been pre-formed the figuratum photoresist layer of tool on described substrate;
Expand the auxiliary resolution of cloth chemical shrinkage and strengthen the photoetching material layer on the surface of described substrate and the surface of described photoresist layer and sidewall;
Carry out heat treatment, with the compound boundary place that strengthens between photoetching material layer and described photoresist in the auxiliary resolution of described chemical shrinkage, form the non-water soluble material layer;
Carry out etch-back, the auxiliary resolution of described chemical shrinkage that removal is positioned at the top surface top of described photoresist layer strengthens photoetching material layer and described non-water soluble material layer, to expose at least the top surface of described photoresist layer, thereby only keep a part in described non-water soluble material layer on the sidewall of described photoresist layer; And
Remove the auxiliary resolution of described photoresist layer and described chemical shrinkage and strengthen the photoetching material layer, only keep the part on the sidewall that is positioned at described photoresist layer of described non-water soluble material layer, as described hard mask layer.
2. method according to claim 1, wherein, the total surface that the auxiliary resolution of described chemical shrinkage strengthens the photoetching material layer is the surface higher than described photoresist layer.
3. method according to claim 1 and 2, wherein, described heat treatment is processed for mixing baking, and baking temperature is that 70 ℃ ~ 130 ℃ and stoving time are 20 ~ 90 seconds.
4. method according to claim 1, wherein, it is to expand cloth on the surface of the surperficial and described photoresist layer of described substrate and the sidewall by spin coating proceeding that the auxiliary resolution of described chemical shrinkage strengthens the photoetching material layer.
5. method according to claim 1, wherein, it is to remove by the photoetching process that comprises exposure, development and rinsed with deionized water step that the auxiliary resolution of described photoresist layer and described chemical shrinkage strengthens the photoetching material layer.
6. method according to claim 5, wherein, described rinsed with deionized water step comprises single or twice rinsing.
7. method according to claim 6, wherein, the time of each rinsing is 20 ~ 90 seconds.
8. method according to claim 1, wherein, be pre-formed target material layer between described substrate and described photoresist layer.
9. method that is used for the dual composition of autoregistration, described method comprises uses the hard mask layer of method formation as described in any one in claim 1 ~ 8 to shelter to carry out subsequent technique.
10. method according to claim 9, wherein, described subsequent technique is etch process, ion implantation technology or selective epitaxial growth process.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681429A (en) * | 2013-11-27 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN105988284A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Double-mask self-aligning patterning method |
| CN106611699A (en) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | A dual composition method and a manufacturing method for a semiconductor device |
| CN113130383A (en) * | 2020-01-16 | 2021-07-16 | 芯恩（青岛）集成电路有限公司 | Semiconductor structure and manufacturing method thereof |
| WO2022205665A1 (en) * | 2021-03-29 | 2022-10-06 | 长鑫存储技术有限公司 | Mask structure and manufacturing method therefor, and semiconductor structure and manufacturing method therefor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431680A (en) * | 2002-01-10 | 2003-07-23 | 旺宏电子股份有限公司 | Method for forming structure of fine sizes |
| US20080063986A1 (en) * | 2006-09-12 | 2008-03-13 | Hynix Semiconductor Inc. | Method of forming fine pattern of semiconductor device |
| US20080064213A1 (en) * | 2006-09-12 | 2008-03-13 | Hynix Semiconductor Inc. | Method for forming a fine pattern of a semiconductor device |
| US20100130016A1 (en) * | 2008-11-24 | 2010-05-27 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
| CN102037543A (en) * | 2008-05-22 | 2011-04-27 | 美光科技公司 | Methods of forming structures supported by semiconductor substrates |
-
2012
- 2012-05-11 CN CN201210147052.2A patent/CN103390544B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431680A (en) * | 2002-01-10 | 2003-07-23 | 旺宏电子股份有限公司 | Method for forming structure of fine sizes |
| US20080063986A1 (en) * | 2006-09-12 | 2008-03-13 | Hynix Semiconductor Inc. | Method of forming fine pattern of semiconductor device |
| US20080064213A1 (en) * | 2006-09-12 | 2008-03-13 | Hynix Semiconductor Inc. | Method for forming a fine pattern of a semiconductor device |
| CN102037543A (en) * | 2008-05-22 | 2011-04-27 | 美光科技公司 | Methods of forming structures supported by semiconductor substrates |
| US20100130016A1 (en) * | 2008-11-24 | 2010-05-27 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
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| CN104681429A (en) * | 2013-11-27 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN104681429B (en) * | 2013-11-27 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN105988284A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Double-mask self-aligning patterning method |
| CN106611699A (en) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | A dual composition method and a manufacturing method for a semiconductor device |
| CN113130383A (en) * | 2020-01-16 | 2021-07-16 | 芯恩（青岛）集成电路有限公司 | Semiconductor structure and manufacturing method thereof |
| WO2022205665A1 (en) * | 2021-03-29 | 2022-10-06 | 长鑫存储技术有限公司 | Mask structure and manufacturing method therefor, and semiconductor structure and manufacturing method therefor |
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