CN103390646B - Semiconductor element and manufacture method thereof - Google Patents
Semiconductor element and manufacture method thereof Download PDFInfo
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- CN103390646B CN103390646B CN201210141509.9A CN201210141509A CN103390646B CN 103390646 B CN103390646 B CN 103390646B CN 201210141509 A CN201210141509 A CN 201210141509A CN 103390646 B CN103390646 B CN 103390646B
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Abstract
The present invention discloses a kind of semiconductor element and manufacture method thereof, and this semiconductor element comprises: semiconductor settled layer, is formed on an insulation system and a substrate; Semiconductor element more comprises a grid, is formed on the zone of action between first and second injection region of semiconductor deposition; First injection region and the 2nd injection region all have one first conductivity type, and grid has one the 2nd conductivity type; Semiconductor element more can comprise a second gate pole, is formed under semiconductor deposition.
Description
Technical field
The present invention about a kind of semiconductor technology, particularly about a kind of junction field-effect transistor (JunctionFieldEffectTransistor, JEFT) element and manufacture method thereof.
Background technology
Known junction field effect transistor element has structure as shown in Figure 1. It is such as on the semi-conductive substrate 102 of Silicon Wafer that the junction field effect transistor element 100 that Fig. 1 illustrates is formed in. Substrate 102 by being such as the injection technology such as diffusing, doping (diffusiondoping), ion implantation (ionimplantation) or in-situ doped (in-situdoping) modify, to introduce P type hotchpotch. One N trap 104 is formed in substrate 102, it is provided that make the passage that electric charge flows between source electrode end and drain electrode end. N trap 104 is introduced N-type dopant by known injection technology and is formed. Junction field effect transistor element 100 more comprises multiple first injection region 106 and multiple 2nd injection region 108. This little first injection region respectively comprises the N-type dopant of a high density, and each first injection region can be used as source electrode or drain electrode. This little 2nd injection region 108 respectively comprises P type hotchpotch, and each 2nd injection region can be used as grid.
During operation, a drain electrode being just worth is to source voltage (drain-sourcevoltage, VDS) order about the electric charge in N trap 104 by source electrode flow direction drain electrode. The conductance of N trap 104 by the grid of a negative value to source voltage (gate-sourcevoltage, VGS) control, the V of this negative valueGSThe induction of each PN junction is made to form exhaustion region (depletionregion). Grid is to source voltage VGSValue can tune to the passage of exhaustion region pinching (pinchoff) flow of charge, to close junction field effect transistor element 100. This voltage reaching pinching is called pinching voltage (pinchoffvoltage, VP). When junction field effect transistor element is integrated in a unicircuit, the impact of semiconducter substrate noise can change VP, cause the inconsistent and defect of multiple junction field effect transistor element. Therefore, for allowing more accurate VP, have and need to insulate junction field effect transistor element.
Summary of the invention
One first one exemplary embodiment discloses a kind of semiconductor element, comprises a substrate, and an insulation system is formed on substrate; And semiconductor settled layer, it is formed on insulation system and substrate, semiconductor deposition has one first conductivity type. Disclosed semiconductor element more comprises one first injection region, is formed in semiconductor deposition, and the first injection region has the first conductivity type and the doping content that relatively semiconductor deposition is high; And one the 2nd injection region, it is formed in semiconductor deposition, the 2nd injection region has the first conductivity type and the doping content that relatively semiconductor deposition is high. Disclosed semiconductor element more comprises a metal contact layer, it is formed on the zone of action between the first injection region of semiconductor deposition and the 2nd injection region of semiconductor deposition, using and form a junction between the zone of action of metal contact layer and semiconductor deposition, wherein this junction is a Schottky barrier (Schottkybarrier).
One the 2nd one exemplary embodiment discloses a kind of semiconductor element, comprises a substrate, and one first insulation system is formed on substrate, and one first semiconductor deposition is formed on the first insulation system. Disclosed semiconductor element more comprises one the 2nd insulation system and is formed in the first semiconductor deposition, and one the 2nd semiconductor deposition is formed on the 2nd insulation system, and the 2nd semiconductor deposition has a conductivity type. Disclosed semiconductor element can comprise one first injection region and be formed in the 2nd semiconductor deposition, and the first injection region has conductivity type and the doping content high compared with the 2nd semiconductor deposition; And one the 2nd injection region be formed in the 2nd semiconductor deposition, the 2nd injection region has conductivity type and the doping content high compared with the 2nd semiconductor deposition. One metal contact layer is formed on the zone of action between the first injection region of the 2nd semiconductor deposition and the 2nd injection region of the 2nd semiconductor deposition, using and form a junction in the zone of action of metal level and the 2nd semiconductor deposition, wherein this junction is a Schottky barrier.
Disclosed by the relative manufacturing process of the semiconductor element that the present invention discloses also has.
Accompanying drawing explanation
Fig. 1 illustrates the sectional view of a kind of tradition junction field effect transistor element.
Fig. 2 illustrates the sectional view of a kind of junction field effect transistor element disclosed according to the present invention.
Fig. 3 illustrates the local view of the ad hoc structure of the junction field effect transistor element of Fig. 2.
Fig. 4 illustrates the front view of the junction field effect transistor element 300 of tool three-dimensional gate structure.
Fig. 5 illustrates the local view of an embodiment of the junction field effect transistor element of Fig. 4.
Fig. 6 illustrates the local view of another embodiment of the junction field effect transistor element of Fig. 4.
Fig. 7 illustrates the traditional circuit that comprises resistance.
Fig. 8 illustrates an embodiment of the circuit comprising the junction field effect transistor element that the present invention discloses.
Fig. 9 illustrates in an embodiment of Fig. 8, and the source electrode of junction field effect transistor element is to the relation of grid voltage and the drain electrode voltage of MOS element.
[main element nomenclature]
100,200,300: junction field effect transistor element
102,202,302: substrate
104:N trap 106: the first injection region
108: the two injection regions
204: insulation system
206,306: field oxide
208: high temperature oxide layer
210: the first trap districts
212: semiconductor deposition 214, S: source electrode
216, D: drain electrode
218,324: metal contact layer
220,326: zone of action
304: the first insulation systems
308: grid oxic horizon
310: the first semiconductor deposition
312: the two insulation systems
314: the two semiconductor deposition
316: the first injection regions, source electrode
318: the two injection regions, drain electrode
320: the first major axis
322: the two major axis
400,500: circuit
410: resistance
420,550: electric capacity
430,520: PWM circuit
530:HVdepletionMOS
540: diode
ID: from the electric current of MOS
IIC: charging current
IAUX: auxiliary current
VZ: voltage breakdown
VCC: service voltage
VS: source electrode is to grid voltage
Vss: source voltage
Vgg: grid voltage
Embodiment
Fig. 2 illustrates the sectional view of a junction field effect transistor element 200, its sharp keen degree (sharpness) that can reduce noise and increase pinching. Junction field effect transistor element 200 comprises substrate 202 and an insulation system 204, and insulation system 204 is formed on the substrate 202.Insulation system 204 can in order to substantially to protect the structure on it to avoid influence of noise and the interference of its lower substrate. Insulation system 204 can comprise a field oxide 206 (fieldoxide, FOX), formed on the substrate 202, in certain embodiments, more can comprise a high temperature oxide layer 208 (hightemperatureoxide, HTO) to be formed on field oxide 206. Field oxide 206 and high temperature oxide layer 208 can be known standard mask and thermal oxidation technique formed. For example, it is possible to local silicon oxidation (1ocaloxidationofsilicon, LOCOS) technique forms field oxide 206. Identical technique can be repeated to form high temperature oxide layer 208. The exemplary technique of LOCOS comprises shallow trench isolation (shallowtrenchisolation, STI) or silicon-on-insulator (silicononinsulator, SO1). Although numerical value may change, field oxide can have the thickness between scope 1000 dust (angstrom)-10000 dust, and the best is about 5000 dusts, and high temperature oxide layer 208 can have the thickness between 120 dust-400 dusts, and the best is about 300 dusts.
Below insulation system 204, one first trap district 210 can be formed in the substrate 210 below insulation system 204. In the embodiment that Fig. 2 illustrates, substrate 202 comprises P type hotchpotch, but in another embodiment, substrate 202 can comprise N-type dopant. In any embodiment, the first trap district 210 can be a P trap or a N trap.
Above insulation system 204, form semiconductor settled layer 212 on insulation system 204 by a depositing operation. Semiconductor deposition 212 can have one first conductivity type, makes electric charge flow to drain electrode 216 by source electrode 214. The conductance of semiconductor deposition 212 controls by grid 218. The structure of junction field effect transistor element 200 will be described more in detail with Fig. 3 below.
Fig. 3 is the local view of junction field effect transistor element 200. Semiconductor deposition 212 can be the polysilicon layer manufactured by standard technology, and as above-mentioned discussion, semiconductor deposition 212 is modified by injection technology to have one first conductivity type, and this first conductivity type can be N-type or P type. In one embodiment, semiconductor deposition 212 is formed by deposit spathic silicon, the N-type dopant being such as phosphorus oxychloride (phosphorylchloride, POCl) can when polysilicon deposition by in-situ doped (in-situdoping) introducing. In one embodiment, POCl3Concentration be approximately 1 �� 1011/cm2. Also can example other the N-type dopant such as phosphorus (phosphorous, P) in this way. In another embodiment, by diffusing, doping (diffusiondoping) or the in-situ doped introducing N-type dopant of ion implantation (ionimplantation). In an embodiment again, technique that can also be identical with introducing N-type dopant introduces P type hotchpotch in semiconductor deposition 212. The example of one P type hotchpotch is boron (boron, B).
One first injection region 214 can be formed in semiconductor deposition 212, this first injection region have the first conductivity type and doping content relatively semiconductor deposition 212 for high. First injection region 214 is signable is source electrode 214. One the 2nd injection region 216 can be formed in semiconductor deposition 212, this 2nd injection region have the first conductivity type and doping content relatively semiconductor deposition 212 for high. 2nd injection region 216 is signable is drain electrode 216.
In the exemplary embodiment of figure 3, the first conductivity type is N-type, and semiconductor deposition 212 can operate provide a N channel electric charge is flowed between a N+ injection region 214 and the 2nd N+ injection region 216.In another embodiment, the first conductivity type can be P type, and semiconductor deposition 212 can operate provide a P channel electric charge is flowed between a P+ doped region 214 and the 2nd P+ doped region 216.
Except semiconductor deposition 212, junction field effect transistor element 200 more can comprise a metal contact layer 218, is formed on a zone of action 220 of semiconductor deposition 212, and this zone of action 220 is positioned between the first injection region 214 and the 2nd injection region 216. Metal contact layer 218 can comprise a metal being applicable to, and makes the junction between the zone of action 220 of metal contact layer 218 and semiconductor deposition 212 as Schottky barrier (Schottkybarrier). Foundation semiconductor deposition 212 comprises N-type or P type hotchpotch, and Schottky barrier can be used as P-type grid electrode respectively or N-type grid uses. Metal contact layer 218 as above is signable is grid 218. For forming a P-type grid electrode, metal contact layer 218 can comprise suitable metal such as titanium, tungsten, nickel, platinum, aluminium, gold or cobalt. For forming a N-type grid, metal contact layer 218 can comprise suitable metal such as platinum (Pt).
Grid 218 can be operated to control the conductance of the passage of semiconductor deposition 212. During operation, the drain electrode being just worth is to source voltage (drain-sourcevoltage, VDS) make electric charge flow into drain electrode 216 by the source electrode 214 of semiconductor deposition 212. The conductance of semiconductor deposition 212 by the grid of negative value to source voltage (gate-sourcevoltage, VGS) control, the V of this negative valueGSIn zone of action 220 or around it, induction forms exhaustion region (depletionregion). VGSValue can tune to the passage of exhaustion region pinching (pinchoff) flow of charge, to close junction field effect transistor element 200. Thickness according to semiconductor deposition, this pinching voltage (pinchoffvoltage, VP) may change. In an exemplary embodiment, the scope of semiconductor deposition layer thickness can make VPBetween 0.7-30 volt. In another embodiment, the thickness range of semiconductor deposition can between 500 dust-6000 dusts.
By forming metal contact layer 218 and semiconductor deposition 212 on insulation system 204, substantially reduce the noise and interference that are derived from substrate 202, again by grid 218 and more accurate VP, promote the control of the conductance to semiconductor deposition 212. Another advantage of disclosed structure is, is arranged in the first trap district 210 under insulation system 204 and may be used for holding other space may do not had to form the element of PN junction at junction field-effect transistor.
Fig. 4 illustrates the front view of the junction field effect transistor element 300 of tool three-dimensional gate structure. Junction field effect transistor element 300 comprises a substrate 302 and one first insulation system 304, first insulation system 304 is formed on substrate. Insulation system 204, first insulation system 304 being similar to Fig. 2 and Fig. 3 discussion can in order to substantially to protect the structure on it to avoid influence of noise and the interference of its lower substrate 302. First insulation system 304 can comprise a field oxide 306, is formed on substrate 302. In certain embodiments, the first insulation system 304 more can comprise a grid oxic horizon 308, is arranged on field oxide 306. Field oxide 306 and grid oxic horizon 308 can be known standard mask and thermal oxidation technique formed.
Junction field effect transistor element 300 more comprises one first semiconductor deposition 310 being formed on the first insulation system 304, one the 2nd insulation system 312 being formed in the first semiconductor deposition 310, and one the 2nd semiconductor deposition 314 being formed on the 2nd insulation system 312.Fig. 5 is in junction field effect transistor element 300, is formed at the part view of structure on the first insulation system 304. In one embodiment, the first semiconductor deposition 310 and the 2nd semiconductor deposition 314 can as shown in Figure 5, extend respectively to the first major axis 320 and the 2nd major axis 322. In an exemplary embodiment, the first major axis 320 is substantially orthogonal to the 2nd major axis 322, but in another embodiment, the first major axis 320 and the 2nd major axis can be harmonized at an angle. First semiconductor deposition 310 can comprise any one of N-type or P type hotchpotch, with provide form three-dimensional gate structure time required conductance, below will describe in detail. In one embodiment, the first semiconductor deposition can deposit with silication tungsten WSi and silication cobalt CoSi, to form the silicide that can reduce the first semiconductor deposition 310 resistance. Insulation system 312 can be the high temperature oxide layer 208 as described in the embodiment of Fig. 2 and Fig. 3.
In addition, the 2nd semiconductor deposition 314 can substantially be similar to the semiconductor deposition 212 described in embodiment of Fig. 2 and Fig. 3. 2nd semiconductor deposition 314 can be a polysilicon layer manufactured by standard technology, and modifies by injection technology to have one first conductivity type, and this first conductivity type can be N-type or P type. In the one exemplary embodiment that Fig. 6 illustrates, 2nd semiconductor deposition 314 is formed on the first insulation system 304 and the 2nd insulation system 312 by deposit spathic silicon, and N-type dopant when deposit spathic silicon, can be infused in the 2nd semiconductor deposition 314 by in-situ doped. In another embodiment, by diffusing, doping or the in-situ doped introducing N-type dopant of ion implantation. In an embodiment again, available P type hotchpotch replaces N-type dopant, introduces in the 2nd semiconductor deposition 314 with identical technique.
Please refer to Fig. 4 to Fig. 6, one first injection region 316 can be formed in the 2nd semiconductor deposition 314, and this first injection region 316 has the conductivity type identical with the 2nd semiconductor deposition 314 and the doping content high compared with the 2nd semiconductor deposition 314. First injection region 316 is signable is source S. One the 2nd injection region 318 can be formed in the 2nd semiconductor deposition 314, and this 2nd injection region 318 has the conductivity type identical with the 2nd semiconductor deposition 314 and the doping content high compared with the 2nd semiconductor deposition 314. 2nd injection region 318 is signable is drain D.
Junction field effect transistor element 300 comprises a metal contact layer, is formed on a zone of action 326 of the 2nd semiconductor deposition 314, and this zone of action 326 is positioned between the first injection region 316 and the 2nd injection region 318. Being similar to metal contact layer 218, metal contact layer 324 can comprise a suitable metal, makes the junction between the zone of action 326 of metal contact layer 324 and the 2nd semiconductor deposition 314 as a Schottky barrier. Metal contact layer 324 around the 2nd semiconductor deposition 314, and can not contact with the first semiconductor deposition. Comprise N-type or P type hotchpotch according to the 2nd semiconductor deposition 314, Schottky barrier can be used as P-type grid electrode respectively or N-type grid uses. Metal contact layer 324 as above is signable is grid 324.
After injecting N-type or P type hotchpotch, the conductance of the 2nd semiconductor deposition 314 allows that electric charge flows to drain electrode 318 from source electrode 316. The conductance of the 2nd semiconductor deposition 314 controls by both grid 324 and the first semiconductor deposition 310.When independently performing, grid 324 can the first grid best source voltage V of a negative valueGS1Control the conductance of the 2nd semiconductor deposition 314, this VGS1One first exhaustion region is responded in zone of action 326 or around it. VGS1Value can tune to the passage of exhaustion region pinching (pinchoff) flow of charge, to close junction field effect transistor element 300. But, the first semiconductor deposition 300 and the 2nd insulation system 312 can be used as a second gate pole, operate to form one the 2nd exhaustion region in the 2nd semiconductor deposition 314. 2nd exhaustion region is by, on the electrode (not illustrating) being connected with the first semiconductor deposition 310, applying the second gate best source voltage V of a negative value in additionGS2Formed. Except the improvement that the first insulation system 304 causes, the first exhaustion region and the 2nd exhaustion region can act on mutually, control V that not only can be betterP, more can promote the tolerance range (precision) of pinching.
By promoting control and the tolerance range of pinching voltage, the junction field effect transistor element that the present invention discloses can reach more how different improvement on unicircuit (IC). For example, in recent years, it is contemplated that the high conversion efficiency of junction field effect transistor element disclosed to the present invention and low standby power loss, particularly suitable is in the development of green science and technology. The power supply IC of one suitching type comprises an integrated starting circuit and PWM (PulseWidthMoldulation, a PWM) circuit. Fig. 7 illustrates a traditional high-voltage starting circuit 400, and after it starts, resistance 410 still continues to produce power consumption. The optional self energy of resistance 410 provides charging current (chargingcurremt, IIC) to electric capacity 420, and PWM circuit can be made to start the kind of running. PWM circuit 430 continues running until its voltage VCCLower than minimum operating voltage, a then auxiliary current IauxApply in PWM circuit. PWM circuit 430 is general to be operated between 10V-30V. For reducing power consumption, the resistance 410 starting circuit can replace by HVdepletionMOS or HVJEFT element. But, a HVdepletionNMOS has big leakage current (> 100 �� A) at threshold voltage place (<-4V). One HVJEFT needs big floating district (driftregion) to reduce surface field (reducedsurfacefield, RESURF) to be formed, and therefore the pinching feature of HVJEFT lacks accuracy.
Fig. 8 illustrates the demonstrative circuit 500 comprising the junction field effect transistor element 510 that the present invention discloses. Junction field effect transistor element 510 can be any junction field-effect transistor configuration disclosing principle according to the present invention. Except junction field effect transistor element 510, circuit 500 more comprises a PWM circuit 520, HVdepletionMOS530, and diode 540. During operation, the source electrode between the starting period is to grid voltage VSIt is less than the pinching voltage V of junction field effect transistor elementP, and junction field effect transistor element presents low resistance. One exemplary pinching voltage VPIt is about 15 volts. When junction field effect transistor element presents low resistance, there is exemplary threshold voltage (thresholdvoltage, a Vth) HVdepletionMOS530 of-3V, the electric current that PWM circuit 520 operates and electric capacity 450 charges and needs can be provided, until the V of junction field effect transistor element 510SReach pinching voltage Vp. Work as VSHigher than pinching voltage VPTime, what the resistance of junction field effect transistor element 510 can be a large amount of increases, and drains to source voltage simultaneously and still keeps and pinching voltage VPIdentical.Work as VSHigher than pinching voltage VPOne threshold voltage VthTime, MOS530 will close. Such as in an exemplary embodiment, pinching voltage VPIt is about 15V and threshold voltage VthFor-3V. The chart of Fig. 9 illustrates, and in this embodiment, works as VSHigher than pinching voltage VPAbout during 15V, because the resistance of junction field effect transistor element 510 increases, from the electric current (I of MOS530D) start to reduce. Work as VSWhen reaching 18V, also it is exactly higher than pinching voltage VPOne threshold voltage Vth, from the electric current I of MOS530DTo stop. Please refer to Fig. 8, after PWM starts, IauxCan in order to charging capacitor 550. Therefore, can accurately control pinching voltage VPJunction field effect transistor element 510, can reduce HVdepletionMOS530 leakage current and increase efficiency.
Although the present invention with embodiment disclose as above, so itself and be not used to limit the present invention. Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations. Therefore, it is intended that the invention not be limited to disclosed specific embodiment, and the change and retouching done within the spirit and scope of the present invention should be comprised, protection scope of the present invention is when depending on being as the criterion that the right enclosed defines.
Claims (8)
1. a semiconductor element, comprising:
One substrate;
One first insulation system, is formed over the substrate;
One first semiconductor deposition, is formed on this first insulation system, and this first semiconductor deposition is an electrode;
One the 2nd insulation system, is formed in this first semiconductor deposition;
One the 2nd semiconductor deposition, is formed on the 2nd insulation system, and the 2nd semiconductor deposition has one first conductivity type;
One first injection region, is formed in the 2nd semiconductor deposition, and this first injection region has this first conductivity type and the doping content that relatively the 2nd semiconductor deposition is high;
One the 2nd injection region, is formed in the 2nd semiconductor deposition, and the 2nd injection region has this first conductivity type and the doping content that relatively the 2nd semiconductor deposition is high; And
One metal contact layer, it is formed on a zone of action of the 2nd semiconductor deposition, this zone of action is between this first injection region and the 2nd injection region, one junction is formed between this zone of action of this metal contact layer and the 2nd semiconductor deposition, and wherein this junction is a Schottky barrier (Schottkybarrier).
2. semiconductor element according to claim 1, wherein this first insulation system comprises a field oxide (fieldoxidelayer).
3. semiconductor element according to claim 2, wherein this first insulation system more comprises a grid oxic horizon, is arranged on this field oxide.
4. semiconductor element according to claim 1, more comprises one first trap district, is formed in this substrate, and wherein this first trap district is positioned at the lower section of this first insulation system, and this first trap district has this first conductivity type or one the 2nd conductivity type.
5. semiconductor element according to claim 1, wherein the 2nd semiconductor deposition comprises a polysilicon layer.
6. semiconductor element according to claim 1, wherein this first conductivity type is N-type, and this Schottky barrier can be used as a P-type grid electrode.
7. semiconductor element according to claim 1, wherein this first conductivity type is P type, and this Schottky barrier can be used as a N-type grid.
8. a manufacture method for semiconductor element, comprising:
A substrate is formed one first insulation system;
Forming one first semiconductor deposition on this first insulation system, this first semiconductor deposition is an electrode;
This first semiconductor deposition is formed one the 2nd insulation system;
Forming one the 2nd semiconductor deposition on the 2nd insulation system, the 2nd semiconductor deposition has one first conductivity type;
Forming one first injection region in the 2nd semiconductor deposition, this first injection region has this first conductivity type and doping content that relatively the 2nd semiconductor deposition is high;
Forming one the 2nd injection region in the 2nd semiconductor deposition, the 2nd injection region has this first conductivity type and doping content that relatively the 2nd semiconductor deposition is high;
A zone of action of the 2nd semiconductor deposition forms a metal contact layer, this zone of action is between this first injection region and the 2nd injection region, and then form a junction between this metal contact layer and this zone of action of the 2nd semiconductor deposition, wherein this junction is a Schottky barrier.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0623949A1 (en) * | 1993-01-25 | 1994-11-09 | Telefonaktiebolaget Lm Ericsson | A dielectrically isolated semiconductor device and a method for its manufacture |
| US5973341A (en) * | 1998-12-14 | 1999-10-26 | Philips Electronics North America Corporation | Lateral thin-film silicon-on-insulator (SOI) JFET device |
| TW201131759A (en) * | 2010-03-10 | 2011-09-16 | Macronix Int Co Ltd | Junction-field-effect-transistor devices and methods of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8120072B2 (en) * | 2008-07-24 | 2012-02-21 | Micron Technology, Inc. | JFET devices with increased barrier height and methods of making same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0623949A1 (en) * | 1993-01-25 | 1994-11-09 | Telefonaktiebolaget Lm Ericsson | A dielectrically isolated semiconductor device and a method for its manufacture |
| US5973341A (en) * | 1998-12-14 | 1999-10-26 | Philips Electronics North America Corporation | Lateral thin-film silicon-on-insulator (SOI) JFET device |
| TW201131759A (en) * | 2010-03-10 | 2011-09-16 | Macronix Int Co Ltd | Junction-field-effect-transistor devices and methods of manufacturing the same |
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