CN103412253A - Interconnection structure modeling method and interconnection resource allocation vector automatic generation method - Google Patents
Interconnection structure modeling method and interconnection resource allocation vector automatic generation method Download PDFInfo
- Publication number
- CN103412253A CN103412253A CN2013103365101A CN201310336510A CN103412253A CN 103412253 A CN103412253 A CN 103412253A CN 2013103365101 A CN2013103365101 A CN 2013103365101A CN 201310336510 A CN201310336510 A CN 201310336510A CN 103412253 A CN103412253 A CN 103412253A
- Authority
- CN
- China
- Prior art keywords
- pip
- layer
- ndp
- fpga
- model
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses an interconnection structure modeling method and an interconnection resource allocation vector automatic generation method, and belongs to an FPGA technology. The interconnection structure modeling method comprises the following steps that firstly, metal wires in a chip are classified, the metal wires of a kind are collectively known as a layer, two metal wires can be connected through a programmable interconnect point PIP in a switch box, and the PIPs between the metal wires of the same kind are called intra-PIPs, the PIPs between the metal wires of the different kinds are called inter-PIPs; then all the layers are used as points, the connected relations of the PIPS are called edges, and a graph is set up. According to the method, test configuration can be automatically generated, and testing efficiency is high. The interconnection resource test coverage rate, especially the coverage of the PIPs is high, The interconnection structure modeling method and the interconnection resource allocation vector automatic generation method do not aim at an FPGA of a certain type, can be used for testing the FPGA of an SRAM type, and are good in universality, and transplantation is convenient. More precise fault location and diagnosis can be achieved.
Description
Technical field
The invention belongs to the FPGA technology.
Background technology
SRAM type field programmable gate array (Field Programmable Gate Array, hereinafter to be referred as FPGA) mainly by array of programmable logic cells, input/output module, intellectual property core and a large amount of interconnect resources (Interconnect Resource, hereinafter to be referred as IR), formed.
In FPGA interconnect resources test based on SRAM, because the interconnect resources kind is many, annexation is complicated and changeable, and interconnection line and tie point able to programme (Programmable Interconnect Point, hereinafter to be referred as PIP) all at chip internal, occupy chip area very large, its test is very scabrous problem always.
Along with the development of modern FPGA, interconnect resources becomes increasingly complex, and its proportion in FPGA inside constantly increases, and even near 90%, so its probability broken down is more much bigger than other resources in the FPGA of current up to ten million gate leves.
Traditional method of testing is for the able to programme and concrete design feature of FPGA, by the manual placement-and-routing of FPGA_Editor, completes test configurations (Test Configuration, hereinafter to be referred as TC).Traditional chip testing technology efficiency is low, can only be for the chip of concrete structure, and can not realize automatic configuration, no longer applicable.Document (Modeling of FPGA Local/Global Interconnect Resource and Derivation of Minimal Test Configurations) and document (the local interconnected method of testing [P] of a kind of FPGA based on Greedy strategy. patent of invention, CN102116840A, 2011-07-06) method be only applicable to the test of local interconnect resources.Document (Application-Independent Testing of FPGA Interconnects) and document (Shenyang Inst of Automation, Chinese Academy of Sciences. a kind of method of testing of FPGA based on the max-flow method [P]. patent of invention, CN102116839A, method 2011-07-06) can only be done global test, can not local test, and very low to the test coverage of PIP.
Summary of the invention
Technical matters to be solved by this invention is to propose the vectorial automatic generation method of a kind of high efficiency interconnect resources configuration.
The technical scheme that the present invention solve the technical problem employing is that the vectorial automatic generation method of interconnect resources configuration, is characterized in that, comprises the steps:
1) switch box structure of the concrete fpga chip of basis, set up the interconnect resources model of this FPGA: at first the metal wire in chip is classified, of a sort metal wire is referred to as a layer, between two metal line, only have by the PIP in switch enclosure and just can connect, PIP between similar metal wire is called intra-PIP, and the PIP between the dissimilar metals line is called inter-PIP; Each layer is a little, and all layer have formed point set, and the annexation of PIP, as the limit collection, is set up the IR model;
2) by the IR model conversion, be adjacency matrix A, each element in matrix A is corresponding to be encircled or directed edge in the IR model;
3) but according to matrix A, find the cloth path of one group of optimum, but each cloth path all corresponding the TC of one group of same type;
4) each paths obtained in step 3) is converted into to digraph Gp, the every line of each layer in path is expressed as the point in Gp, and each PIP comprised in path is expressed as the limit in Gp;
5) from graph theory model Gp, obtaining node-disjoint paths (Node Disjoint Paths, hereinafter to be referred as NDP), adopt the edge coloring algorithm based on locally optimal solution to carry out edge coloring to Gp, obtain the solution of optimum or near-optimization; The limit of same color forms one group of NDP, test configurations that one group of NDP is namely corresponding, and the number of NDP equals the test configurations number of times;
6) repeating step 4) and step 5), until calculate NDP corresponding to all paths, obtain the test configurations set of this fpga chip.
Beneficial effect of the present invention:
1, the present invention can generate test configurations automatically, and testing efficiency is high.
2, the present invention is high to the interconnect resources test coverage, especially to the covering of PIP.
3, the present invention, not for the FPGA of concrete a certain model, can be used in the FPGA test of SRAM type, and versatility is good, the convenient transplanting.
4, the present invention can accomplish more accurate localization of fault and diagnosis.
The accompanying drawing explanation
Fig. 1 is the technical solution of the present invention process flow diagram;
Fig. 2 is IR universal model figure;
Fig. 3 is IR universal model adjacency matrix;
Fig. 4 is the edge coloring algorithm schematic diagram based on locally optimal solution;
Embodiment
The specific embodiment of the invention step is as follows:
Step 1), according to the switch box structure of concrete fpga chip, is set up the IR model of this FPGA.At first the metal wire in chip is classified, of a sort metal wire is referred to as a layer.Between two metal line, only have by the PIP in switch enclosure and just can connect.PIP between similar metal wire is called intra-PIP, and the PIP between the dissimilar metals line is called inter-PIP.Each layer is a little, and all layer have formed point set V, and the annexation of PIP is limit, sets up the IR model;
Step 2) by the IR model conversion, be adjacency matrix A.Each element in matrix A is corresponding ring or directed edge in the IR model, the element Di correspondence of the capable i row of i the ring Di of layer_i in the model, the element Di-j correspondence of the capable j row of i in the model, connect the directed edge Di-j of layer_i and layer_j;
But step 3) is found the cloth path of one group of optimum according to matrix A.But each cloth path is all corresponding TC of one group of same type.One group of path finding out must meet some specific conditions, in order to next can therefrom obtain available optimal T C;
But step 4) is converted into digraph Gp by each the cloth path obtained in step 3), and the every line of each layer in path is expressed as the point in Gp, and each PIP comprised in path is expressed as the limit in Gp;
Step 5) is from obtaining NDP graph theory model Gp.Employing is carried out edge coloring based on the edge coloring algorithm of locally optimal solution to Gp, can obtain the solution of optimum or near-optimization.The limit of same color forms one group of NDP, test configurations that one group of NDP is namely corresponding, and the number of NDP equals the test configurations number of times;
Step 6) repeating step 4) and step 5), until calculate NDP corresponding to all paths, obtain the test configurations set of this fpga chip, by the result output automatically generated.
Described IR illustraton of model is an oriented non-negative weighted graph D.
The described algorithm of edge coloring based on locally optimal solution: often, after selected a kind of color, all allow maximum limits be colored so that the color sum that uses as far as possible little; This algorithm comprises two parts: the bigraph colouring algorithm 1, mated based on maximum; 2, find the NDP algorithm of the oriented chain n figure of section.
Described bigraph colouring algorithm based on the maximum coupling: from bigraph Gb, start to find a maximum coupling M1, and then find the maximum coupling M2 of Gb-M1, so continuation can be decomposed into Gb n coupling M1, M2 ..., Mn, each is mating a kind of color, is one group of color rendering intent.
The NDP algorithm of the oriented chain n figure of section of described searching comprises:
At first the chain n figure of section is decomposed into to n-1 bigraph, then n-1 bigraph is carried out respectively to the bigraph colouring algorithm based on the maximum coupling, limit corresponding to same color is one group of NDP.
Embodiment is referring to Fig. 1 more specifically, Fig. 1 technical solution of the present invention process flow diagram, and step is as follows:
Step 1), according to the switch box structure of concrete fpga chip, is set up the IR model of this FPGA.At first the metal wire in chip is classified, of a sort metal wire is referred to as a layer.Between two metal line, only have by the PIP in switch enclosure and just can connect.PIP between similar metal wire is called intra-PIP, and the PIP between the dissimilar metals line is called inter-PIP.Therefore the switch enclosure in fpga chip is divided into: 1, several layer of all kinds of metal wires formation; 2, intra-PIP corresponding to each layer; 3, the inter-PIP between different layer.As shown in Figure 2, we have adopted the concept of oriented non-negative weighted graph in the graph theory, set up general purpose I R illustraton of model G{V, E}, and the point in figure represents each layer, and ring represents a class intra-PIP, and directed edge represents a class inter-PIP.All layer have formed point set V, V={layer_1, and layer_2, layer_3, layer_4, layer_5 ..., layer_n}, PIP forms limit collection E, sets up the IR model.
Step 2) by the IR model conversion, be adjacency matrix A.As shown in Figure 3, each element in matrix A is corresponding to be encircled or directed edge in the IR model, the element Di correspondence of the capable i of i row the ring Di of layer_i in the model, the element Di-j correspondence of the capable j of i row in the model, connect the directed edge Di-j of layer_i and layer_j, element 0 means that the corresponding coordinate place does not exist and encircles or directed edge.；
But step 3) is found the cloth path of one group of optimum according to matrix A.But each cloth path is all corresponding TC of one group of same type.For example, (L1L1) → (L1L2) → (L2L3) → ... → (Li Ln) but be exactly a cloth path, (Li Ln) is illustrated in the adjacency matrix of IR model, there is element " Di-n " in the capable n of i row.But one group of cloth path finding out must meet some specific conditions, in order to next can therefrom obtain available optimal T C;
Step 4) is converted into digraph Gp by each paths obtained in step 3), the every line of each layer in path is expressed as the point in Gp, each PIP comprised in path is expressed as the limit in Gp, but has all comprised a small amount of intra-PIP and a large amount of inter-PIP in each cloth path.For example path (L1L1) → (L1L2) → (L2L3) → ... in → (Li Ln), (L1L1) mean intra-PIP, and (L1L2), (L2L3) ..., (Li Ln) represented a large amount of inter-PIP.Because these two kinds of PIP need to adopt diverse ways to cover, so Gp is decomposed into to Gp1 and two subgraphs of Gp2, Gp1 means the part (being decomposed into the union of all directions bigraph) of intra-PIP, and Gp2 means the part (being decomposed into the figure of chain n section) of inter-PIP.
Step 5) is from obtaining NDP graph theory model Gp.Adopt approximate colouring algorithm to carry out edge coloring to Gp, can obtain the solution of optimum or near-optimization.The limit of same color forms one group of NDP, test configurations that one group of NDP is namely corresponding, and the number of NDP equals the test configurations number of times;
Step 6) repeating step 4) and step 5), until calculate NDP corresponding to all paths, obtain the test configurations set of this fpga chip, by the result output automatically generated.
Described IR illustraton of model is an oriented non-negative weighted graph D.
But the specified conditions of described searching cloth path: in D, the point of selected all bands is starting point, and layer_n is terminal.From these starting points, start the Add one by one directed edge to form directed walk until reach home, but finally obtain some cloth paths, but all limits of the union of these some cloth paths in can coverage diagram D, namely cover all PIP, and the weights summation minimum in all paths.
But described searching cloth path algorithm: after obtaining the IR illustraton of model of a fpga chip, at first the point of mark existence ring is starting point S, and the layer_n point is terminal T.According to the order of ordering to layer_n-1 from the layer_1 point, select S point wherein according to certain rule, to add the directed edge pathway successively as starting point, until the T that reaches home.In fact, select the rise initial line of starting point ring as path, the weights of ring are as the initial weight W in path.In the process that generates directed walk, the terminal of current path is called as operating point.After arriving an operating point, must select next to go out limit according to certain criterion, thus generation pass arrive next operating point.If the situation of directed walk occurs can't continue to generate in certain operating point, return to previous operating point, ignore the limit between these 2, according to criterion, regenerate path.By adjacency matrix, but the cloth path of one group of optimum can be generated automatically by computer program.
The described algorithm of edge coloring based on locally optimal solution: often, after selected a kind of color, all allow maximum limits be colored so that the color sum that uses as far as possible little; This algorithm comprises two parts: the bigraph colouring algorithm 1, mated based on maximum; 2, find the NDP algorithm of the oriented chain n figure of section.
Described bigraph colouring algorithm based on the maximum coupling: from bigraph Gb, start to find a maximum coupling M1, and then find the maximum coupling M2 of Gb-M1, so continuation can be decomposed into Gb n coupling M1, M2 ..., Mn, each is mating a kind of color, is one group of color rendering intent.Gb is for having the bigraph of two classification (X, Y), and the specific algorithm of finding the maximum coupling of Gb is:
Step.1 arranges initial matching M for empty, if each summit of the saturated X of M, algorithm stops; Otherwise establishing u is the M unsaturation summit in X, puts point set S={u} and point set T=φ, φ means empty set.
If Step.2 is N (S)=T, N (S) means the neighborhood of point set S, due to | T|=|S|-1, so | N (S) |<| S|, algorithm stops, because according to the HALL theorem in graph theory, does not have the coupling on each summit of saturated X; Otherwise, set up an office y ∈ N (S) T.
If it is saturated that Step.3 y is M, establish yz ∈ M, make S=S ∪ { z}, T=T ∪ { y}, and jump to step2; Otherwise establishing path P is the extendible road of M, make M=(M ∪ E (P)-M ∩ E (P)), E (P) means the limit collection of path P, and jumps to step1.
The algorithm circulation stops the maximum coupling that rear resulting coupling M is Gb.
The NDP algorithm of the figure Gn of the oriented chain n of described searching section:
At first the figure Gn of chain n section is decomposed into to n-1 bigraph, then each bigraph Gi (i+1) is carried out respectively to the bigraph colouring algorithm based on the maximum coupling, limit corresponding to same color is one group of NDP.Specifically be divided into two steps:
(1) the bigraph colouring algorithm that starts successively each bigraph Gi (i+1) to be carried out based on the maximum coupling from G12 carries out edge coloring; (2) after often completing a kind of color painted, leave out painted limit, repeated execution of steps (1), until all limits in Gn all are colored, now Gn just is broken down into the NDP of N group by the different colours representative.
Instructions has absolutely proved necessary technology content of the present invention, and those of ordinary skill can be implemented according to instructions, therefore repeat no more ins and outs more specifically.
Claims (4)
1. interconnect architecture modeling method, it is characterized in that, comprise the steps: at first the metal wire in chip to be classified, of a sort metal wire is referred to as a layer, between two metal line, only have by the programmable configuration point PIP in switch enclosure and just can connect, PIP between similar metal wire is called intra-PIP, and the PIP between the dissimilar metals line is called inter-PIP; Then all layer of take are point, and the annexation of PIP is limit, sets up figure.
2. the vectorial automatic generation method of interconnect resources configuration, is characterized in that, comprises the steps:
1) switch box structure of the concrete fpga chip of basis, set up the interconnect resources model of this FPGA: at first the metal wire in chip is classified, of a sort metal wire is referred to as a layer, between two metal line, only have by the programmable configuration point PIP in switch enclosure and just can connect, PIP between similar metal wire is called intra-PIP, and the PIP between the dissimilar metals line is called inter-PIP; Each layer is a little, and all layer have formed point set V, and the annexation of PIP is limit, sets up the IR model;
2) by above-mentioned IR model conversion, be adjacency matrix A, each element in matrix A is corresponding to be encircled or directed edge in the IR model;
3) but according to matrix A, find the cloth path of one group of optimum, but each cloth path all corresponding the test configurations of one group of same type;
4) each paths obtained in step 3) is converted into to digraph Gp, the every line of each layer in path is expressed as the point in Gp, and each PIP comprised in path is expressed as the limit in Gp;
5) from graph theory model Gp, obtaining node-disjoint paths, adopt the edge coloring algorithm based on locally optimal solution to carry out edge coloring to Gp, obtain the solution of optimum or near-optimization; The limit of same color forms one group of NDP, test configurations that one group of NDP is namely corresponding, and the number of NDP equals the test configurations number of times;
6) repeating step 5) and step 6), until calculate NDP corresponding to all paths, obtain the test configurations set of this fpga chip.
3. interconnect resources as claimed in claim 2 configures vectorial automatic generation method, it is characterized in that, in described step 5), based on the edge coloring algorithm of locally optimal solution be: often after selected a kind of color, all allow maximum limits be colored so that the color sum that uses as far as possible little.
4. the vectorial automatic generation method of interconnect resources configuration as claimed in claim 2, is characterized in that, the described algorithm of edge coloring based on locally optimal solution comprises two parts: based on the bigraph colouring algorithm of maximum coupling; Find the NDP algorithm of the oriented chain n figure of section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310336510.1A CN103412253B (en) | 2013-08-05 | 2013-08-05 | Interconnect architecture modeling method and interconnect resources configuration vector automatic generation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310336510.1A CN103412253B (en) | 2013-08-05 | 2013-08-05 | Interconnect architecture modeling method and interconnect resources configuration vector automatic generation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103412253A true CN103412253A (en) | 2013-11-27 |
| CN103412253B CN103412253B (en) | 2016-01-20 |
Family
ID=49605279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310336510.1A Active CN103412253B (en) | 2013-08-05 | 2013-08-05 | Interconnect architecture modeling method and interconnect resources configuration vector automatic generation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103412253B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106546912A (en) * | 2016-10-14 | 2017-03-29 | 电子科技大学 | It is a kind of to apply relationship type FPGA automatic test collocation methods |
| CN106909728A (en) * | 2017-02-21 | 2017-06-30 | 电子科技大学 | A kind of FPGA interconnection resources configuration generating methods based on enhancing study |
| CN111930613A (en) * | 2020-07-14 | 2020-11-13 | 深圳市紫光同创电子有限公司 | Test case generation method and device for chip to be tested, electronic equipment and medium |
| CN112183014A (en) * | 2020-09-25 | 2021-01-05 | 无锡中微亿芯有限公司 | Force guiding layout method for carrying out crowded area expansion based on maximum flow algorithm |
| CN114371970A (en) * | 2022-01-10 | 2022-04-19 | 电子科技大学 | FPGA interconnection resource testing algorithm based on graph reinforcement learning |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1188569A (en) * | 1995-05-03 | 1998-07-22 | Btr公司 | Scalable multiple level interconnect architecture |
| US6631510B1 (en) * | 1999-10-29 | 2003-10-07 | Altera Toronto Co. | Automatic generation of programmable logic device architectures |
| US7103813B1 (en) * | 2003-11-06 | 2006-09-05 | Altera Corporation | Method and apparatus for testing interconnect bridging faults in an FPGA |
| US7191426B1 (en) * | 2004-09-01 | 2007-03-13 | Altera Corporation | Method and apparatus for performing incremental compilation on field programmable gate arrays |
| CN101881811A (en) * | 2009-05-08 | 2010-11-10 | 复旦大学 | Fault testing method for interconnection resource of programmable logic device |
| CN102116841A (en) * | 2011-01-04 | 2011-07-06 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
| CN102116839A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院沈阳自动化研究所 | Method for testing field programmable gate array (FPGA) based on maximum flow method |
| CN102116840A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院沈阳自动化研究所 | Method for testing local interconnection of field programmable gate array (FPGA) based on greedy strategy |
-
2013
- 2013-08-05 CN CN201310336510.1A patent/CN103412253B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1188569A (en) * | 1995-05-03 | 1998-07-22 | Btr公司 | Scalable multiple level interconnect architecture |
| US6631510B1 (en) * | 1999-10-29 | 2003-10-07 | Altera Toronto Co. | Automatic generation of programmable logic device architectures |
| US7103813B1 (en) * | 2003-11-06 | 2006-09-05 | Altera Corporation | Method and apparatus for testing interconnect bridging faults in an FPGA |
| US7191426B1 (en) * | 2004-09-01 | 2007-03-13 | Altera Corporation | Method and apparatus for performing incremental compilation on field programmable gate arrays |
| CN101881811A (en) * | 2009-05-08 | 2010-11-10 | 复旦大学 | Fault testing method for interconnection resource of programmable logic device |
| CN102116839A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院沈阳自动化研究所 | Method for testing field programmable gate array (FPGA) based on maximum flow method |
| CN102116840A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院沈阳自动化研究所 | Method for testing local interconnection of field programmable gate array (FPGA) based on greedy strategy |
| CN102116841A (en) * | 2011-01-04 | 2011-07-06 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
Non-Patent Citations (6)
| Title |
|---|
| CHRISTIAN GIASSON等: "Modeling The Interconnects Of Xilinx Virtex FPGAs And Derivation Of Their Test Configurations", 《CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING》 * |
| RUAN AIWU等: "Graph theory for FPGA minimum configurations", 《JOURNAL OF SEMICONDUCTORS》 * |
| 刘军华等: "一种基于匹配理论的FPGA三级互连网络测试方法", 《电子与信息学报》 * |
| 王林等: "一种用于FPGA互联资源测试的新方法", 《电子元器件应用》 * |
| 谈珺等: "FPGA通用开关盒层次化建模与优化", 《电子与信息学报》 * |
| 项传银等: "基于故障映射的FPGA互连资源故障测试与定位", 《仪器仪表学报》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106546912A (en) * | 2016-10-14 | 2017-03-29 | 电子科技大学 | It is a kind of to apply relationship type FPGA automatic test collocation methods |
| CN106546912B (en) * | 2016-10-14 | 2019-06-21 | 电子科技大学 | A kind of application relationship type FPGA automatic test configuration method |
| CN106909728A (en) * | 2017-02-21 | 2017-06-30 | 电子科技大学 | A kind of FPGA interconnection resources configuration generating methods based on enhancing study |
| CN106909728B (en) * | 2017-02-21 | 2020-06-16 | 电子科技大学 | FPGA interconnection resource configuration generation method based on reinforcement learning |
| CN111930613A (en) * | 2020-07-14 | 2020-11-13 | 深圳市紫光同创电子有限公司 | Test case generation method and device for chip to be tested, electronic equipment and medium |
| CN111930613B (en) * | 2020-07-14 | 2023-11-28 | 深圳市紫光同创电子有限公司 | Test case generation method and device for chip to be tested, electronic equipment and medium |
| CN112183014A (en) * | 2020-09-25 | 2021-01-05 | 无锡中微亿芯有限公司 | Force guiding layout method for carrying out crowded area expansion based on maximum flow algorithm |
| CN112183014B (en) * | 2020-09-25 | 2022-02-18 | 无锡中微亿芯有限公司 | Force guiding layout method for carrying out crowded area expansion based on maximum flow algorithm |
| CN114371970A (en) * | 2022-01-10 | 2022-04-19 | 电子科技大学 | FPGA interconnection resource testing algorithm based on graph reinforcement learning |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103412253B (en) | 2016-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103412253B (en) | Interconnect architecture modeling method and interconnect resources configuration vector automatic generation method | |
| CN104657418B (en) | A kind of complex network propagated based on degree of membership obscures corporations' method for digging | |
| CN105226647B (en) | A kind of high-performance electrical network real-time topology analysis method | |
| CN104462260A (en) | Community search algorithm based on k-kernel | |
| CN108833144B (en) | Intelligent ammeter concentrator site selection method based on cluster statistical model | |
| CN102647356B (en) | Carrier concentrator relay route meter reading method of ant colony-like algorithm based on candidate set strategy | |
| CN105005823B (en) | A kind of ship branch line paths planning method based on genetic algorithm | |
| Zhang et al. | A small world network model for energy efficient wireless networks | |
| CN103942345B (en) | Method for automatically generating IED network graph | |
| Pei et al. | Steiner traveler: Relay deployment for remote sensing in heterogeneous multi-robot exploration | |
| CN109460410A (en) | By the json data conversion with set membership at the method for tree structure data | |
| Sayyari et al. | Automated generation of software testing path based on ant colony | |
| CN113709754B (en) | Clustering algorithm based wireless broadband communication system station arrangement networking method and system | |
| CN104202241A (en) | Deflection fault-tolerant routing algorithm for network-on-chip with 2D-Mesh topology structure | |
| CN105930609B (en) | A kind of FPGA timing optimization method for coherent demodulation | |
| CN106412933A (en) | Communication method and equipment | |
| CN103428804A (en) | Method for searching mapping scheme between tasks and nodes of network-on-chip (NoC) and network code position | |
| CN106709119A (en) | FPGA chip wiring method | |
| Chen et al. | Obstacle-avoiding connectivity restoration based on quadrilateral Steiner tree in disjoint wireless sensor networks | |
| CN112231976B (en) | Method for establishing wind farm equivalent model | |
| CN116016384B (en) | Scalable network-on-chip topology structure based on ring layout and routing method thereof | |
| CN104080088A (en) | Method and device of channel allocation | |
| CN106339531B (en) | A kind of combinatorial logic unit circuit structure generation method that C cell is reinforced | |
| Chen et al. | An energy-aware heuristic constructive mapping algorithm for network on chip | |
| CN112180817B (en) | Method, device, equipment and storage medium for transforming ladder diagram into binary tree |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |