CN103427825B - Clock signal conversion method and device - Google Patents
Clock signal conversion method and device Download PDFInfo
- Publication number
- CN103427825B CN103427825B CN201210149979.XA CN201210149979A CN103427825B CN 103427825 B CN103427825 B CN 103427825B CN 201210149979 A CN201210149979 A CN 201210149979A CN 103427825 B CN103427825 B CN 103427825B
- Authority
- CN
- China
- Prior art keywords
- clock signal
- level
- phase inverter
- mentioned
- cml
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a kind of clock signal conversion method and device, said method is comprised the following steps：When level shift circuit receives current mode logic CML differential signals, line level movement is entered to which, and by the CML differential signal incoming level change-over circuits moved through over level；Above-mentioned level shifting circuit produces multiphase orthogonal clock signal according to the CML differential signals for receiving.CML logical transitions not only can be CMOS logic by the present invention, moreover it is possible to obtain the high-quality multi-phase clock signal of 50% dutycycle after converting, such that it is able to reduce the quiescent dissipation of clock and data recovery system, improve data recovering efficiency.
Description
Technical field
The present invention relates to signal switch technology field, more particularly to a kind of clock signal conversion method and device.
Background technology
High-speed serial data is needed using clock and data recovery system when transmitting.Clock and data recovery system extensively makes
With various recovering clock signals transmission datas, such as biphase (phase 180 degree) or four phases (phase place is 0 degree, 90 degree, 180 degree,
270 degree) clock signal.Therefore, the quality of clock signal quality directly influences transmission performance.Pass through in high speed solution tandem system
Often using the two phase clock signal of phase 180 degree.In some other clock and data recovery system, or even need to use
The clock signal of more multiphase.For multi-phase clock signal, data are recovered using its rising edge and trailing edge typically, so generally will
Ask clock meet the requirement of 50% dutycycle, to improve systematic function.
CML (current mode logic, current mode logic) circuit extensively should as its amplitude of oscillation is little, speed fast
Use in clock and data recovery system, but the partial data for relative low speeds, system is often desirable to adopt CMOS
(Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) logic circuit, to reduce
The quiescent dissipation of circuit.Although CML signals can be converted to cmos signal by prior art, after converting, but can not
The multiphase orthogonal signal of 50% dutycycle that generation system needs, so that can not effectively reduce the quiescent dissipation of circuit.
Content of the invention
It is an object of the invention to, there is provided a kind of clock signal conversion method and device, CML is believed with solving prior art
After number being converted to cmos signal, it is impossible to obtain the technical problem of high-quality multiphase orthogonal signal.
The present invention solves above-mentioned technical problem by the following technical programs：
A kind of clock signal conversion method, comprises the following steps：
When level shift circuit receives current mode logic CML differential signals, line level movement is entered to which, and will be through over level
Mobile CML differential signal incoming level change-over circuits；
Above-mentioned level shifting circuit produces multiphase orthogonal clock signal according to the CML differential signals for receiving.
According to the CML differential signals for receiving, produce multiphase orthogonal clock signal step includes above-mentioned level shifting circuit：
Above-mentioned level shifting circuit receives the CML differential signals moved through over level, is amplified, then output phase phase
The first complementary metal oxide semiconductors (CMOS) cmos clock signal and the second cmos clock signal of difference 180 degree；
Above-mentioned first dutyfactor adjustment circuit receives above-mentioned first cmos clock signal, produces phase place and is respectively 0 degree and 180
The clock signal of degree；
Above-mentioned second dutyfactor adjustment circuit receives above-mentioned second cmos clock signal, produce phase place be respectively 90 degree with
270 degree of clock signal.
According to preferred embodiment, above-mentioned level shift circuit includes two by N-type metal-oxide semiconductor (MOS) NMOS tube
Level shifting module with current source concatenation；
Above-mentioned level shifting circuit includes cross-linked first P-type mos PMOS and second
PMOS, also includes first NMOS tube and the second NMOS tube of receives input signal；
Above-mentioned first dutyfactor adjustment circuit by the first two-divider, the first phase inverter, first drive phase inverter, the two or two
Frequency divider, the second phase inverter and the second driving phase inverter sequential concatenation are formed；
Above-mentioned second dutyfactor adjustment circuit by the 3rd two-divider, the 3rd phase inverter, the 3rd drive phase inverter, the four or two
Frequency divider, the 4th phase inverter and the 4th driving phase inverter sequential concatenation are formed.
According to preferred embodiment, when above-mentioned level shift circuit receives current mode logic CML differential signals, electricity is carried out to which
Translation is dynamic, and the CML differential signal incoming level change-over circuit steps moved through over level are included：
Above-mentioned level shift circuit is by the first level shifting module to first in the original CML differential signals that receive
CML signals enter line level movement, by second electrical level mobile module to the 2nd CML signals in the original CML differential signals
Enter line level movement, make the level of above-mentioned CML signals and the 2nd CML signals reach the optimal work of above-mentioned level shifting circuit
Make level；
Then above-mentioned first level shifting module and second electrical level mobile module are by moving through over level of each processing
The above-mentioned level shifting circuit of signal input.
According to preferred embodiment, above-mentioned level shifting circuit receives the CML differential signals moved through over level, is put
Greatly, then the first cmos clock signal of output phase difference 180 degree and the second cmos clock signals step include：
Above-mentioned level shifting circuit receives the CML signals moved through over level by above-mentioned first NMOS tube, and will
Which is input in above-mentioned first PMOS；By above-mentioned second NMOS tube receive through over level move the 2nd CML signals, and by its
It is input in above-mentioned second PMOS；
Above-mentioned first PMOS is amplified to the signal for receiving, and then exports above-mentioned first cmos clock signal；
Above-mentioned second PMOS is amplified to the signal for receiving, and then exports above-mentioned second cmos clock signal.
Above-mentioned first dutyfactor adjustment circuit receives above-mentioned first cmos clock signal, produces phase place and is respectively 0 degree and 180
The clock signal step of degree includes：
Above-mentioned first two-divider receives above-mentioned first cmos clock signal, produces the first drive signal CK2, and will be above-mentioned
First drive signal CK2 is input in above-mentioned first phase inverter；
After above-mentioned first phase inverter receives above-mentioned first drive signal CK2, clock signal CK3 that phase place is 0 degree is produced, and
Above-mentioned clock signal CK3 input above-mentioned first is driven in phase inverter；
After above-mentioned first driving phase inverter receives above-mentioned clock signal CK3, the second drive signal CK4 is produced, and will be above-mentioned
Second drive signal CK4 is input in above-mentioned second two-divider；
After above-mentioned second two-divider receives above-mentioned second drive signal CK4, according to the input of above-mentioned level shifting circuit
First cmos clock signal produces the 3rd drive signal CK5, and above-mentioned 3rd drive signal CK5 is input into above-mentioned second phase inverter
In；
After above-mentioned second phase inverter receives above-mentioned 3rd drive signal CK5, clock signal CK6 of the phase place for 180 degree is produced.
Above-mentioned second dutyfactor adjustment circuit receives above-mentioned second cmos clock signal, produce phase place be respectively 90 degree with
270 degree of clock signal step includes：
Above-mentioned 3rd two-divider receives above-mentioned second cmos clock signal, produces fourth drive signal CK7, and will be above-mentioned
Fourth drive signal CK7 is input in above-mentioned 3rd phase inverter；
After above-mentioned 3rd phase inverter receives above-mentioned fourth drive signal CK7, clock signal CK8 that phase place is 90 degree is produced,
And drive above-mentioned clock signal CK8 input the above-mentioned 3rd in phase inverter；
After above-mentioned 3rd driving phase inverter receives above-mentioned clock signal CK8, the 5th drive signal CK9 is produced, and will be above-mentioned
5th drive signal CK9 is input in above-mentioned 4th two-divider；
After above-mentioned 4th two-divider receives above-mentioned 5th drive signal CK9, according to the input of above-mentioned level shifting circuit
Second cmos clock signal produces the 6th drive signal CK10, and anti-phase by the above-mentioned for above-mentioned 6th drive signal CK10 inputs the 4th
In device；
After above-mentioned 4th phase inverter receives above-mentioned 6th drive signal CK10, the clock signal that phase place is 270 degree is produced
CK11.
The present invention is also employed the following technical solutions：
A kind of clock signal conversion equipment, including：The level shift circuit being sequentially connected electrically and level shifting circuit；
Above-mentioned level shift circuit, for when CML differential signals are received, entering line level movement to which, and will mobile electricity
CML differential signal incoming level change-over circuits after flat；
Above-mentioned level shifting circuit, for according to the CML differential signals for receiving, producing multiphase orthogonal clock signal.
Further, above-mentioned level shifting circuit, the CML differential signals for receiving amplify, and then export a pair of phases
The cmos clock signal of position difference 180 degree.
Said apparatus also include：The first dutyfactor adjustment circuit for electrically connecting with above-mentioned level shifting circuit respectively and second
Dutyfactor adjustment circuit；
Above-mentioned first dutyfactor adjustment circuit, for receiving the first cmos clock letter of above-mentioned level shifting circuit output
Number, produce the quadrature clock signal that phase place is 0 degree and 180 degree；
Above-mentioned second dutyfactor adjustment circuit, for receiving the second cmos clock letter of above-mentioned level shifting circuit output
Number, produce the quadrature clock signal that phase place is 90 degree and 270 degree.
Above-mentioned level shift circuit includes two level shifting modules concatenated by NMOS tube and current source.
Above-mentioned level shifting circuit includes cross-linked first PMOS and the second PMOS, also includes receives input
First NMOS tube and the second NMOS tube of signal；
Above-mentioned first NMOS tube and the second NMOS tube, for receiving the CML differential signals moved through over level, and will receive
Signal be input in above-mentioned first PMOS and the second PMOS respectively；
Above-mentioned first PMOS and the second PMOS, are amplified for the CML differential signals to receiving, then in output
State the cmos clock signal of phase 180 degree.
Above-mentioned first dutyfactor adjustment circuit and the second dutyfactor adjustment circuit include identical component；
Above-mentioned first dutyfactor adjustment circuit by the first two-divider, the first phase inverter, first drive phase inverter, the two or two
Frequency divider, the second phase inverter and the second driving phase inverter sequential concatenation are formed；
Above-mentioned second dutyfactor adjustment circuit by the 3rd two-divider, the 3rd phase inverter, the 3rd drive phase inverter, the four or two
Frequency divider, the 4th phase inverter and the 4th driving phase inverter sequential concatenation are formed.
Compared with prior art, the present invention has following Advantageous Effects：The present invention not only can be by CML logical transitions
For CMOS logic, moreover it is possible to obtain the high-quality multi-phase clock signal of 50% dutycycle after converting, during such that it is able to reducing
Clock and the quiescent dissipation of data recovery system, improve data recovering efficiency.
Description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the present invention, this
Bright schematic description and description does not constitute inappropriate limitation of the present invention for explaining the present invention.In the accompanying drawings：
Fig. 1 is a kind of flow chart of clock signal conversion method in the preferred embodiment of the present invention；
Fig. 2 is a kind of module frame chart of clock signal conversion equipment in the preferred embodiment of the present invention；
Fig. 3 is the internal circuit schematic diagram of the clock signal conversion equipment in the preferred embodiment of the present invention as described in Figure 2；
Fig. 4 be the preferred embodiment of the present invention in change over clock signal, the waveform of adopted or obtained clock signal
Schematic diagram；
Fig. 5 is the preferred embodiment of the present invention when the dutycycle of cmos clock signal is adjusted, obtained M signal
Waveform diagram.
Specific embodiment
In order that the technical problem to be solved, technical scheme and beneficial effect are clearer, clear, below tie
Drawings and Examples are closed, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention.
Fig. 1 is a kind of flow chart of clock signal conversion method in the preferred embodiment of the present invention.As shown in figures 1 and 3, originally
The method of invention preferred embodiment is comprised the following steps：
Step S101：By in CML differential signal incoming levels walking circuit 201；
Above-mentioned CML differential signals include CML signals (CK_CML) and the 2nd CML signals (CK_CML_N) of difference,
Its waveform situation refers to Fig. 4.In the present embodiment, the supply voltage of level shift circuit is 1V, and the amplitude of oscillation of CML differential signals exists
Between 0.6V to 1V.
Step S102：Above-mentioned level shift circuit 201 receives above-mentioned CML differential signals, and above-mentioned CML differential signals are entered
Line level is moved；
In the embodiment of the present invention, above-mentioned level shift circuit 201 includes two by NMOS (N-Mental-Oxide-
Semiconductor, N-type metal-oxide semiconductor (MOS)) manage the level shifting module concatenated with current source.
After above-mentioned level shift circuit 201 receives above-mentioned CML differential signals, by the following method above-mentioned CML difference is believed
Number enter line level movement：
Above-mentioned level shift circuit 201 by the first level shifting module (concatenated by NMOS tube 301 and current source 303 and
Into) enter line level movement to the CML signal CK_CML in the original CML differential signals that receive, moved by second electrical level
Module (being formed by NMOS tube 302 and the concatenation of current source 304) is to the 2nd CML signal CK_ in above-mentioned original CML differential signals
CML_N enters line level movement, makes above-mentioned CML signals and the level of the 2nd CML signals reach level shifting circuit 202 most
Good operation level.
Step S103：Above-mentioned level shift circuit 201 will be electric for the CML differential signals incoming level moved through over level conversion
Road 202；
As shown in figure 3, in the present embodiment, above-mentioned first level shifting module carries out electricity to a CML signals CK_CML
After translation is dynamic, the CML differential signals A for obtaining can be input into above-mentioned level shifting circuit 202；Above-mentioned second electrical level mobile module
After entering line level movement to above-mentioned 2nd CML signal CK_CML_N, the CML differential signals A_N for obtaining can be input into above-mentioned electricity
Flat change-over circuit 202.
Step S104：Above-mentioned level shifting circuit 202 produces phase 180 degree according to the CML differential signals for receiving
First cmos clock signal B and the second cmos clock signal B_N；
In the embodiment of the present invention, above-mentioned level shifting circuit 202 includes cross-linked PMOS (N-Mental-
Oxide-Semiconductor, P-type mos) pipe 305 and the second PMOS 306, also include that receives input is believed
Number the first NMOS tube 307 and the second NMOS tube 308；
Therefore, above-mentioned steps S104 are specifically included：
Above-mentioned level shifting circuit 202 receives the CML letters moved through over level by above-mentioned first NMOS tube 307
Number, and be inputted in above-mentioned first PMOS 305；Move through over level second is received by above-mentioned second NMOS tube 308
CML signals, and be inputted in above-mentioned second PMOS 306；
305 pairs of signals for receiving of above-mentioned first PMOS are amplified, and then export above-mentioned first cmos clock signal B；
306 pairs of signals for receiving of above-mentioned second PMOS are amplified, and then export above-mentioned second cmos clock signal B_
N.
Original CML differential signals that step S101 is adopted, step S102 through the CML differential signals after over level movement, with
And step S104 output cmos clock signal refer to Fig. 4, as seen in Figure 4, above-mentioned first cmos clock signal B and
Second cmos clock signal B_N there may be Duty Cycle Distortion, it is therefore desirable to by following steps S105-107 to above-mentioned CMOS
The dutycycle of clock signal is adjusted and optimizes.
Step S105：The first dutycycle of above-mentioned first cmos clock signal input is adjusted by above-mentioned level shifting circuit 202
Circuit 203, by the second dutyfactor adjustment circuit of above-mentioned second cmos clock signal input 204；
Step S106：Above-mentioned first dutyfactor adjustment circuit 203 receives above-mentioned first cmos clock signal, produces phase place and is
0 degree and the clock signal of 180 degree；
In embodiments of the present invention, above-mentioned first dutyfactor adjustment circuit 203 is anti-phase by the first two-divider 310, first
Device 311, first drives phase inverter 312, the second two-divider 313, the second phase inverter 314 and second to drive 315 order of phase inverter
Concatenation is formed.Above-mentioned second driving phase inverter 315 is matched with the first phase inverter 312, to meet 0 degree of cmos clock and 180 degree
Cmos clock has identical driving force.
Above-mentioned steps S106 specifically include (being read in conjunction with Fig. 3)：
Above-mentioned first two-divider 310 receives above-mentioned first cmos clock signal (representing with B or CK1), produces first and drives
Dynamic signal CK2, and above-mentioned first drive signal CK2 is input in above-mentioned first phase inverter 311；
After above-mentioned first phase inverter 311 receives above-mentioned first drive signal CK2, the clock signal that phase place is 0 degree is produced
CK3, and above-mentioned clock signal CK3 input above-mentioned first is driven in phase inverter 312；
After above-mentioned first driving phase inverter 312 receives above-mentioned clock signal CK3, the second drive signal CK4 is produced, and will be upper
State the second drive signal CK4 to be input in above-mentioned second two-divider 313；
After above-mentioned second two-divider 313 receives above-mentioned second drive signal CK4, it is input into according to above-mentioned level shifting circuit
The first cmos clock signal CK1 produce the 3rd drive signal CK5, and will above-mentioned 3rd drive signal CK5 input above-mentioned second
In phase inverter 314；
After above-mentioned second phase inverter 314 receives above-mentioned 3rd drive signal CK5, clock signal of the phase place for 180 degree is produced
CK6.
Step S107：Above-mentioned second dutyfactor adjustment circuit 204 receives above-mentioned second cmos clock signal, produces phase place and is
90 degree and 270 degree of clock signal.
In embodiments of the present invention, above-mentioned second dutyfactor adjustment circuit 204 is anti-phase by the 3rd two-divider the 316, the 3rd
Device the 317, the 3rd drives phase inverter 318, the 4th two-divider 319, the 4th phase inverter 320 and the 4th to drive 321 order of phase inverter
Concatenation is formed.
Therefore, above-mentioned steps S107 specifically include (being read in conjunction with Fig. 3)：
Above-mentioned 3rd two-divider 316 is received above-mentioned second cmos clock signal (being represented with B_N), is produced the 4th and is driven letter
Number CK7, and above-mentioned fourth drive signal CK7 is input in above-mentioned 3rd phase inverter 317；
After above-mentioned 3rd phase inverter 317 receives above-mentioned fourth drive signal CK7, the clock signal that phase place is 90 degree is produced
CK8, and above-mentioned clock signal CK8 input the above-mentioned 3rd is driven in phase inverter 318；
After above-mentioned 3rd driving phase inverter 318 receives above-mentioned clock signal CK8, the 5th drive signal CK9 is produced, and will be upper
State the 5th drive signal CK9 to be input in above-mentioned 4th two-divider 319；
After above-mentioned 4th two-divider 319 receives above-mentioned 5th drive signal CK9, it is input into according to above-mentioned level shifting circuit
The second cmos clock signal B_N produce the 6th drive signal CK10, and above-mentioned 6th drive signal CK10 is input into above-mentioned the
In four phase inverters 320；
After above-mentioned 4th phase inverter 320 receives above-mentioned 6th drive signal CK10, the clock signal that phase place is 270 degree is produced
CK11.
The method that above step describes the preferred embodiment of the present invention in detail.Of the invention below by Fig. 3 and Fig. 5 analyses
The dutycycle situation of four clock signals for arriving.
As shown in figure 3, above-mentioned first drive signal CK2 just exports CK3 after inverter delay Δ t1, the above-mentioned 3rd drives
Dynamic signal CK5 just exports CK6 after also passing through inverter delay Δ t1, and CK2 and CK5 are to obtain (figure by the sampling of CK1 rising edges
5), so CK2 and CK5 phase 180 degrees, after identical inverter delay, CK3 and CK6 also differs 180 degree.In addition,
As overturning each time for CK2 and CK6 is all that the rising edge in CK1 occurs, so CK2 and CK6 are obtained in that 50% duty
Than so as to CK3 and CK6 are phase 180 degrees, meeting the biphase orthogonal clock of 50% dutycycle.
In the same manner, it is 90 that the second cmos clock signal B_N will produce phase place after the second dutyfactor adjustment circuit 204, also
Spend the biphase orthogonal clock with 270 degree.So the present invention can obtain four mutually orthogonal, the clock signals of dutycycle 50%.
Fig. 2 is a kind of module frame chart of clock signal conversion equipment in the preferred embodiment of the present invention.As shown in Fig. 2 this
The device of bright preferred embodiment includes：The level shift circuit 201 being sequentially connected electrically and level shifting circuit 202, also include point
The first dutyfactor adjustment circuit 203 not electrically connected with above-mentioned level shifting circuit and the second dutyfactor adjustment circuit 204；
Above-mentioned level shift circuit 201, for when CML differential clock signals are received, entering line level movement to which, and will
Through the CML differential clock signal incoming levels change-over circuit 202 that over level is moved；
Above-mentioned level shifting circuit 202, for receiving the CML differential clocks moved through over level, is amplified, then defeated
Go out the cmos clock signal of a pair of phase 180 degrees.
Above-mentioned first dutyfactor adjustment circuit 203, for receiving the first cmos clock of above-mentioned level shifting circuit output
Signal, produces the quadrature clock signal that phase place is respectively 0 degree and 180 degree.
Above-mentioned second dutyfactor adjustment circuit 204, for receiving the second cmos clock of above-mentioned level shifting circuit output
Signal, produces the quadrature clock signal that phase place is respectively 90 degree and 270 degree.
Above-mentioned level shift circuit 201, above-mentioned level shifting circuit 202, above-mentioned first dutyfactor adjustment circuit 203 and
Component inside two dutyfactor adjustment circuits 204 is constituted and refers to Fig. 3, as shown in Figure 3：
Above-mentioned level shift circuit includes two level shifting modules concatenated by NMOS tube and current source.
Above-mentioned level shifting circuit includes cross-linked first PMOS 305 and the second PMOS 306, also includes connecing
Receive first NMOS tube 307 and the second NMOS tube 308 of input signal；
Above-mentioned first NMOS tube 307 and the second NMOS tube 308, for receiving the CML differential signals moved through over level, and
The signal for receiving is input in above-mentioned first PMOS 305 and the second PMOS 306 respectively；
Above-mentioned first PMOS 305 and the second PMOS 306, are amplified for the CML differential signals to receiving, then
Export the cmos clock signal of above-mentioned phase 180 degree.
Above-mentioned first dutyfactor adjustment circuit 203 and the second dutyfactor adjustment circuit 204 include identical circuit devcie.
Above-mentioned first dutyfactor adjustment circuit 203 is driven anti-phase by the first two-divider 310, the first phase inverter 311, first
Device 312, the second two-divider 313, the second phase inverter 314 and the second driving 315 sequential concatenation of phase inverter are formed；
Above-mentioned second dutyfactor adjustment circuit 204 is driven anti-phase by the 3rd two-divider 316, the 3rd phase inverter the 317, the 3rd
Device 318, the 4th two-divider 319, the 4th phase inverter 320 and the 4th driving 321 sequential concatenation of phase inverter are formed.
Described above illustrates and describes the preferred embodiments of the present invention, but as previously mentioned, it should be understood that the present invention is not
Form disclosed herein is confined to, the exclusion to other embodiment is not to be taken as, and be can be used for various other combinations, modification
And environment, and can be carried out by the technology or knowledge of above-mentioned teaching or association area in invention contemplated scope described herein
Change.And change that those skilled in the art are carried out and change be without departing from the spirit and scope of the present invention, then all should be in institute of the present invention
In attached scope of the claims.
Claims (10)
1. a kind of clock signal conversion method, it is characterised in that comprise the following steps：
When level shift circuit receives current mode logic CML differential signals, line level movement is entered to which, and will be moved through over level
CML differential signal incoming level change-over circuits；
The level shifting circuit produces multiphase orthogonal clock signal according to the CML differential signals for receiving；
Wherein, according to the CML differential signals for receiving, produce multiphase orthogonal clock signal step includes the level shifting circuit：
The level shifting circuit receives the CML differential signals moved through over level, is amplified, then output phase difference
The first complementary metal oxide semiconductors (CMOS) cmos clock signal and the second cmos clock signal of 180 degree；
First dutyfactor adjustment circuit receives the first complementary metal oxide semiconductors (CMOS) cmos clock signal, produces phase place point
Not Wei 0 degree and 180 degree clock signal；
Second dutyfactor adjustment circuit receives the second cmos clock signal, produce phase place be respectively 90 degree and 270 degree when
Clock signal.
2. method according to claim 1, it is characterised in that：The level shift circuit includes two by N-type metal
Oxide semiconductor NMOS tube and the level shifting module of current source concatenation；
The level shifting circuit includes cross-linked first P-type mos PMOS and the 2nd PMOS
Pipe, also includes first NMOS tube and the second NMOS tube of receives input signal；
First dutyfactor adjustment circuit drives phase inverter, the second two divided-frequency by the first two-divider, the first phase inverter, first
Device, the second phase inverter and the second driving phase inverter sequential concatenation are formed；
Second dutyfactor adjustment circuit drives phase inverter, the 4th two divided-frequency by the 3rd two-divider, the 3rd phase inverter, the 3rd
Device, the 4th phase inverter and the 4th driving phase inverter sequential concatenation are formed.
3. method according to claim 2, it is characterised in that：When the level shift circuit receives CML differential signals, right
Which enters line level movement, and the CML differential signal incoming level change-over circuit steps moved through over level are included：
The level shift circuit is by the first level shifting module to the CML letters in the original CML differential signals that receive
Number enter line level movement, electricity is carried out to the 2nd CML signals in the original CML differential signals by second electrical level mobile module
Translation is dynamic, makes the level of CML signals and the 2nd CML signals reach the best effort electricity of the level shifting circuit
Flat；
Then first level shifting module and second electrical level mobile module are by the signal moved through over level for each processing
It is input into the level shifting circuit.
4. method according to claim 3, it is characterised in that the level shifting circuit is received and moved through over level
CML differential signals, are amplified, then the first cmos clock signal of output phase difference 180 degree and the second cmos clock letter
Number step includes：
The level shifting circuit receives the CML signals moved through over level by first NMOS tube, and which is defeated
Enter in first PMOS；The 2nd CML signals moved through over level are received by second NMOS tube, and is inputted
In second PMOS；
First PMOS is amplified to the signal for receiving, and then exports the first cmos clock signal；
Second PMOS is amplified to the signal for receiving, and then exports the second cmos clock signal.
5. method according to claim 4, it is characterised in that first dutyfactor adjustment circuit receives described first
Cmos clock signal, the clock signal step for producing respectively 0 degree of phase place and 180 degree include：
First two-divider receives the first cmos clock signal, produces the first drive signal CK2, and by described first
Drive signal CK2 is input in first phase inverter；
After first phase inverter receives the first drive signal CK2, it is 0 degree of clock signal CK3 to produce phase place, and by institute
State clock signal CK3 input described first to drive in phase inverter；
After the first driving phase inverter receives clock signal CK3, the second drive signal CK4 is produced, and by described second
Drive signal CK4 is input in second two-divider；
After second two-divider receives the second drive signal CK4, according to the first of level shifting circuit input
Cmos clock signal produces the 3rd drive signal CK5, and the 3rd drive signal CK5 is input in second phase inverter；
After second phase inverter receives the 3rd drive signal CK5, clock signal CK6 of the phase place for 180 degree is produced.
6. method according to claim 4, it is characterised in that second dutyfactor adjustment circuit receives described second
Cmos clock signal, the clock signal step for producing respectively 90 degree and 270 degree of phase place include：
3rd two-divider receives the second cmos clock signal, produces fourth drive signal CK7, and by the described 4th
Drive signal CK7 is input in the 3rd phase inverter；
After 3rd phase inverter receives fourth drive signal CK7, clock signal CK8 that phase place is 90 degree is produced, and will
The clock signal CK8 input the described 3rd is driven in phase inverter；
After the 3rd driving phase inverter receives clock signal CK8, the 5th drive signal CK9 is produced, and by the described 5th
Drive signal CK9 is input in the 4th two-divider；
After 4th two-divider receives the 5th drive signal CK9, according to the second of level shifting circuit input
Cmos clock signal produces the 6th drive signal CK10, and the 6th drive signal CK10 is input into the 4th phase inverter
In；
After 4th phase inverter receives the 6th drive signal CK10, clock signal CK11 that phase place is 270 degree is produced.
7. a kind of clock signal conversion equipment, it is characterised in that include：The level shift circuit being sequentially connected electrically and level conversion
Circuit, the first dutyfactor adjustment circuit for electrically connecting with the level shifting circuit respectively and the second dutyfactor adjustment circuit；
The level shift circuit, for when CML differential signals are received, entering line level movement to which, and after moving level
CML differential signal incoming level change-over circuits；
The level shifting circuit, for according to the CML differential signals for receiving, producing multiphase orthogonal clock signal；
The level shifting circuit, the CML differential signals for being additionally operable to receive amplify, and then export a pair of phase 180 degrees
Cmos clock signal；
First dutyfactor adjustment circuit, for receiving the first cmos clock signal of the level shifting circuit output, produces
Raw phase place is the quadrature clock signal of 0 degree and 180 degree；
Second dutyfactor adjustment circuit, for receiving the second cmos clock signal of the level shifting circuit output, produces
Raw phase place is the quadrature clock signal of 90 degree and 270 degree.
8. device according to claim 7, it is characterised in that：The level shift circuit include two by NMOS tube and
The level shifting module of current source concatenation.
9. device according to claim 7, it is characterised in that：The level shifting circuit includes cross-linked first
PMOS and the second PMOS, also include first NMOS tube and the second NMOS tube of receives input signal；
First NMOS tube and the second NMOS tube, for receiving the CML differential signals moved through over level, and by the letter for receiving
Number it is input in first PMOS and the second PMOS respectively；
First PMOS and the second PMOS, for being amplified to the CML differential signals for receiving, then export the phase
The cmos clock signal of position difference 180 degree.
10. device according to claim 7, it is characterised in that：First dutyfactor adjustment circuit and the second dutycycle
Adjustment circuit includes identical component；
First dutyfactor adjustment circuit drives phase inverter, the second two divided-frequency by the first two-divider, the first phase inverter, first
Device, the second phase inverter and the second driving phase inverter sequential concatenation are formed；
Second dutyfactor adjustment circuit drives phase inverter, the 4th two divided-frequency by the 3rd two-divider, the 3rd phase inverter, the 3rd
Device, the 4th phase inverter and the 4th driving phase inverter sequential concatenation are formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210149979.XA CN103427825B (en) | 2012-05-15 | 2012-05-15 | Clock signal conversion method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210149979.XA CN103427825B (en) | 2012-05-15 | 2012-05-15 | Clock signal conversion method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103427825A CN103427825A (en) | 2013-12-04 |
| CN103427825B true CN103427825B (en) | 2017-03-15 |
Family
ID=49652086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210149979.XA Active CN103427825B (en) | 2012-05-15 | 2012-05-15 | Clock signal conversion method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103427825B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104320112B (en) * | 2014-09-26 | 2016-10-19 | 中国电子科技集团公司第二十四研究所 | A kind of accurate adjustable two-way clock generation circuit of phase place |
| CN109217869B (en) * | 2017-07-03 | 2024-04-05 | 美国莱迪思半导体公司 | PLL phase rotator system and method |
| CN109428567B (en) * | 2017-08-25 | 2022-08-12 | 深圳市中兴微电子技术有限公司 | Device for realizing duty ratio adjustment |
| US10395704B2 (en) * | 2017-12-22 | 2019-08-27 | Micron Technology, Inc. | Apparatuses and methods for duty cycle error correction of clock signals |
| EP3803872A4 (en) | 2018-05-29 | 2022-03-09 | Micron Technology, Inc. | Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle |
| US11189334B2 (en) | 2018-11-21 | 2021-11-30 | Micron Technology, Inc. | Apparatuses and methods for a multi-bit duty cycle monitor |
| US10715127B2 (en) | 2018-11-21 | 2020-07-14 | Micron Technology, Inc. | Apparatuses and methods for using look-ahead duty cycle correction to determine duty cycle adjustment values while a semiconductor device remains in operation |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304251A (en) * | 2008-05-30 | 2008-11-12 | 西安电子科技大学 | Difference interface circuit for on-chip long lines interlinkage |
| US7626437B2 (en) * | 2001-12-13 | 2009-12-01 | Texas Instruments Deutschland Gmbh | Circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal |
| CN201869179U (en) * | 2010-10-09 | 2011-06-15 | 中国电子科技集团公司第五十八研究所 | Multi-phase clock generating circuit with programmable dutyfactor |
| CN201909847U (en) * | 2011-01-13 | 2011-07-27 | 南京国睿安泰信科技股份有限公司 | Double-channel digital signal acquisition device on basis of VXI (VME <Virtual Machine Enviroment> bus Extension for Instrumentation) interface |
| CN102160288A (en) * | 2008-12-29 | 2011-08-17 | 艾格瑞系统有限公司 | Voltage level translator circuit |
| WO2011136964A1 (en) * | 2010-04-26 | 2011-11-03 | Qualcomm Incorporated | Level shifter for differential signals with balanced transition times |
| JP4872470B2 (en) * | 2006-06-09 | 2012-02-08 | ソニー株式会社 | Level shifter circuit and information reproducing apparatus |
-
2012
- 2012-05-15 CN CN201210149979.XA patent/CN103427825B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7626437B2 (en) * | 2001-12-13 | 2009-12-01 | Texas Instruments Deutschland Gmbh | Circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal |
| JP4872470B2 (en) * | 2006-06-09 | 2012-02-08 | ソニー株式会社 | Level shifter circuit and information reproducing apparatus |
| CN101304251A (en) * | 2008-05-30 | 2008-11-12 | 西安电子科技大学 | Difference interface circuit for on-chip long lines interlinkage |
| CN102160288A (en) * | 2008-12-29 | 2011-08-17 | 艾格瑞系统有限公司 | Voltage level translator circuit |
| WO2011136964A1 (en) * | 2010-04-26 | 2011-11-03 | Qualcomm Incorporated | Level shifter for differential signals with balanced transition times |
| CN201869179U (en) * | 2010-10-09 | 2011-06-15 | 中国电子科技集团公司第五十八研究所 | Multi-phase clock generating circuit with programmable dutyfactor |
| CN201909847U (en) * | 2011-01-13 | 2011-07-27 | 南京国睿安泰信科技股份有限公司 | Double-channel digital signal acquisition device on basis of VXI (VME <Virtual Machine Enviroment> bus Extension for Instrumentation) interface |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103427825A (en) | 2013-12-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103427825B (en) | Clock signal conversion method and device | |
| CN102668386B (en) | Rf signal generation circuit and wireless transmitter | |
| CN103580479B (en) | Voltage conversion circuit | |
| CN104135272B (en) | Save the preemphasis LVDS drive circuits of power consumption | |
| US9001869B2 (en) | Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes | |
| US7482841B1 (en) | Differential bang-bang phase detector (BBPD) with latency reduction | |
| US9130735B2 (en) | Multi-phase clock generation method | |
| CN110232886B (en) | Two-stage decision feedback equalizer and display including the same | |
| CN101640651B (en) | Information processing device and signal processing method | |
| CN106575945A (en) | Apparatus to convert electrical signals from small-signal format to rail-to-rail format | |
| CN101084626A (en) | Mechanism to aid a phase interpolator in recovering a clock signal | |
| CN106385251A (en) | Clock data recovery circuit | |
| US20100167678A1 (en) | Receiver circuit and data transmission system | |
| CN103401551B (en) | A kind of method of sampling of SerDes technology high speed serial signal and device | |
| CN109412579B (en) | Current mode logic driving circuit | |
| JP4441527B2 (en) | Latch circuit and deserializer circuit | |
| CN102055466A (en) | Multi-phase signal generation device | |
| CN103812497B (en) | Driver and method for outputting a low-jitter serial signal | |
| CN103532522B (en) | Dutyfactor adjustment circuit, Double-end-to-singlecircuit circuit and oscillator | |
| US9455846B2 (en) | Decision feedback equalization | |
| CN106951382A (en) | Support the LVDS receiving circuits of DDR data forms | |
| Peng et al. | A 50-Gb/s quarter-rate voltage-mode transmitter with three-tap FFE in 40-nm CMOS | |
| US8811556B2 (en) | Receiving circuit, clock recovery circuit, and communication system | |
| US9847777B2 (en) | Signal potential converter | |
| JP2005333508A (en) | Signal converter and driver |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHENZHEN ZTE MICROELECTRONIC TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: ZTE CORPORATION Effective date: 20131203 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 518057 SHENZHEN, GUANGDONG PROVINCE TO: 518083 SHENZHEN, GUANGDONG PROVINCE |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20131203 Address after: Dameisha Yantian District of Shenzhen City, Guangdong province 518083 Building No. 1 Applicant after: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Applicant before: ZTE Corporation |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20131204 Assignee: Xi'an Chris Semiconductor Technology Co. Ltd. Assignor: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Contract record no.: 2019440020036 Denomination of invention: Method and device for clock signal conversion Granted publication date: 20170315 License type: Common License Record date: 20190619 |