CN103488146B - A kind of BMK telemetry with channel selecting function switches selects module - Google Patents
A kind of BMK telemetry with channel selecting function switches selects module Download PDFInfo
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- CN103488146B CN103488146B CN201310435166.1A CN201310435166A CN103488146B CN 103488146 B CN103488146 B CN 103488146B CN 201310435166 A CN201310435166 A CN 201310435166A CN 103488146 B CN103488146 B CN 103488146B
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Abstract
The BMK telemetry with channel selecting function switches selects a module, and it comprises FPGA subelement, Power supply subelement, passage gating controls address buffer subelement, BMK telemetry receives submodule, BMK telemetry forwards submodule, indicating circuit submodule and clock circuit; Power supply subelement is positioned at the upper left side of FPGA subelement; Passage gating controls the left side that address buffer subelement is positioned at FPGA subelement, and BMK telemetry receives submodule and is positioned at below FPGA subelement; BMK telemetry forwards submodule and is positioned at above FPGA subelement; Indicating circuit submodule is positioned at FPGA subelement upper right side; Clock circuit is positioned on the right side of FPGA subelement; The quantity of BMK Telemetry Data Acquisition card when the present invention significantly reduces the BMK Telemetry Data Acquisition sent more than a set of test product, has saved hardware cost, save the bus expansion slot of testing computer system, and cost performance has been high, be convenient to integrated use.
Description
Technical field
The present invention relates to a kind of BMK telemetry with channel selecting function and switch selection module, for the multiple channel B MK telemetries sent more than 1 cover (such as: 5 covers) test product, realize programmed control multiselect one (such as: 5 select 1) and switch distribution controlling functions, then export the BMK Telemetry Data Acquisition cartoon road in testing computer system to.Thus the time-sharing multiplex that can realize a BMK Telemetry Data Acquisition card acquisition channel, and serial acquisition is carried out to the BMK telemetry more than 1 passage that multiple test product sends.This structure is very beneficial for the testing efficiency improving many cover products, significantly reduces the cost of test macro or equipment, economizes on resources, saves space.The invention belongs to compunication, computer-aided test and field of automatic testing.
Background technology
Telemetry is that the close-in measurement value of object parametric is transferred to remote measuring station to realize the technology of telemeasurement, is the integrated technology utilizing sensing technology, the communication technology and data processing technique.Be mainly used in centralized detecting is disperseed or inaccessible measurand, if measurand is apart from remote, residing bad environments, or be in high-speed motion state.Utilize remote measurement to realize Centralizing inspection, improve automatization level, raise labour productivity, improve working conditions, improve scheduling quality.Remote measurement is that scientific research provides a kind of important means of testing, makes the research project being originally difficult to carry out surveying, obtains important dynamic performance data, be used widely in national economy, scientific research and military technology etc.
In contemporary guided missile telemetry measuring technology, telemetry mainly carries out data transmission with BMK type, is called: BMK telemetry.BMK telemetry is a typical unidirectional bus structure, is mainly used in connecting a large amount of comparatively low-speed devices, is divided into transmit leg and take over party.BMK classical data transmission rate is approximately 1Mbit/s, and the interval of namely transmitting 1 8bits byte is 1us.The base unit that BMK data transmit is a 8bits byte.
BMK telemetry have employed 8 bit address/data line BMK0 ~ BMK7, adds CS1, CS2, EN tri-control lines, carrys out the transmission that timesharing realizes 8 bit address and 16 bit data, and the timing waveform that BMK data export as shown in Figure 11.The maximum 256x3 byte of every frame continuous print BMK data, the time interval representative value between frame and frame is 5ms, as shown in Figure 12.
Between signal EN low period, by the various combination of identification signal CS1 and CS2, address, a data high position, data low level are screened.When CS1 be high CS2 is low, the data representation address bit on Current bus; When CS1 signal is low and CS2 signal is high, the data representation data most-significant byte on Current bus; When CS1 signal is low and CS2 signal is low, the data representation data least-significant byte on Current bus.
So just reach the requirement that 8 bit data address buss transmit 16 bit parallel data.The low effective pulse width representative value of CS1, CS2 is the low effective pulse width representative value of 1us, EN is 0.75us.For improving reliability and the security of data transmission, BMK telemetry adopts differential transfer mode, and every 1 road signal is furnished with 5VCC datum.So BMK telemetry comprises 11 tunnel address/data/control signals and 11 road accompaniment signals, signal sum is altogether 22 road signals.
At missile ground test with emulation, BMK telemetry plays very important effect, and nearly all test result and simulation algorithm are all closely bound up with BMK telemetry.Particularly in the high/low temperature test process of guided missile associated components, wish the volume making full use of high-low temperature chamber, put into high-low temperature chamber batch test overlapping product more, in the hope of significantly compression verification time.Now, with regard to needing, the BMK telemetry of many cover products is gathered.If adopt the method configuring polylith Telemetry Data Acquisition card in testing computer system, both a large amount of software and hardware resources had been wasted, be limited to the extended capability of testing computer system simultaneously, the Telemetry Data Acquisition card quantity increased is very limited, can not meet the BMK Telemetry Data Acquisition demand of a large amount of (such as: >=5 covers) test product.At present, also do not have a kind ofly can realize the module that multichannel BMK telemetry multiselect one switches distribution function.
A kind of BMK telemetry with channel selecting function that the present invention relates to switches selects module, can realize multiselect one (such as: 5 select 1) switching distribution and control, export BMK Telemetry Data Acquisition card to the BMK telemetry sent more than 1 test product.Thus testing computer system only need configure the serial acquisition function that one piece distant BMK survey data collecting card just can realize the BMK telemetry to the transmission of many cover test products.
Summary of the invention
1, object: the object of the present invention is to provide a kind of BMK telemetry with channel selecting function to switch and select module, make an acquisition channel of one piece of BMK Telemetry Data Acquisition card in testing computer system, can under program by BMK telemetry switch select module acquisition time receive more than 1 test product send more than 1 channel B MK telemetry, realize switching to distribute to the programmed control multiselect one (such as: 5 select 1) of BMK telemetry controlling.
2, technical scheme: a kind of BMK telemetry with channel selecting function of the present invention switches selects module, and this module comprises: FPGA subelement, Power supply subelement, passage gating control address buffer subelement, BMK telemetry receives submodule, BMK telemetry forwards submodule, indicating circuit submodule and clock circuit.Position annexation between them and concrete signal trend are: centered by FPGA subelement; Power supply subelement is positioned at the upper left side of FPGA subelement, and it is FPGA subelement, passage gating controls address buffer subelement, BMK telemetry receives submodule, BMK telemetry forwards submodule, indicating circuit submodule and clock circuit provides direct supply; Passage gating controls the left side that address buffer subelement is positioned at FPGA subelement, for providing passage gating to control address to FPGA subelement, controls to select BMK telemetry receiving cable; BMK telemetry receives submodule and is positioned at below FPGA subelement, for receiving outside BMK telemetry and being transferred to FPGA subelement; BMK telemetry forwards submodule and is positioned at above FPGA subelement, for receiving the BMK telemetry of FPGA subelement output and exporting to BMK telemetry receiving card; Indicating circuit submodule is positioned at FPGA subelement upper right side, for receiving the signal about pilot lamp that FPGA subelement exports; Clock circuit is positioned on the right side of FPGA subelement, for FPGA subelement provides necessary clock signal.
CycloneIII Series FPGA selected by described FPGA subelement---EP3C40F484C8N.The multiselect one that this FPGA subelement realizes more than one channel B MK telemetry by hardware program language (such as: Verilog or VHDL) switches distribution controlling functions, namely realizes the function of a data selector.This data selector has more than one above input channel, and each input channel comprises 11 road signals; This data selection has an output channel, and each output channel comprises 11 road signals.The output channel Zhong 11 road signal of this data selector is that the geocoding inputted by outside controls with the corresponding gating of 11 road signal of which input channel.This data selector only controls which input channel and output channel gating, does not carry out decoding, decode operation to any one input channel.
Two DC/DC power transfer module selected by described Power supply subelement, is respectively LT1587CM-3.3 and AMS1117-1.5, and direct current+5V is converted to direct current+3.3V ﹑+1.5V respectively.The direct current supply that it provides necessary for giving whole module.
It is control address to the passage gating of outside input or manual toggle switch setting passage gating is controlled to the buffering of address that described passage gating controls address buffer subelement.The passage gating that it receives outside input controls address, or manually toggle switch sets passage gating control address, and inputs to FPGA subelement.The buffering passage gating of outside input being controlled to address utilizes chip 74LCX541MTC, and this chip can also increase driving force in addition.Mainly gauge tap is manually passed through to the buffering that manual toggle switch setting passage gating controls address, makes corresponding address be high level or low level.
Described BMK telemetry receives submodule, and be made up of the optocoupler receiving circuit more than 1 cover, wherein opto-coupler chip selects the HCPL-063L of Agilent company.Every suit optocoupler receiving circuit Jun You 11 road optocoupler receiving circuit, input to FPGA subelement after one channel B MK telemetry Zhong 22 road signal is converted to 11 road single-ended signals, but do not change the sequential between the address/data/control signal in a channel B MK telemetry.Each optocoupler receiving circuit one end, road is connected with a channel B MK telemetry Zhong mono-road accompaniment signal, and the other end is connected with a channel B MK telemetry Zhong mono-tunnel address/data/control signal.Wherein, the output circuit level of every suit optocoupler receiving circuit is LVTTL level or Transistor-Transistor Logic level.Wherein, described every suit optocoupler receiving circuit is " 1 " when BMK telemetry Zhong mono-tunnel address/data/control signal is high level, the not conducting of optocoupler receiving circuit, and what corresponding optocoupler exported is exactly high level; When BMK telemetry Zhong mono-tunnel address/data/control signal is low level " 0 ", LEDs ON, what corresponding optocoupler exported is exactly low level.
Described BMK telemetry forwards submodule and is made up of TI company SOIC packaged chip ULN2803ADW.The 11 road signals that the output channel of data selector in FPGA subelement exports are transformed to the channel B MK telemetry containing 22 road signals by it, wherein have 11 road signals to be+5V, then export to BMK telemetry receiving card.
Described indicating circuit submodule comprises passage pilot lamp group and FPGA tests pilot lamp group.It is used to indicate passage gating and controls address from outside input or toggle switch, and which channel B MK telemetry of designation data selector switch gating.FPGA test instruction is mainly judged the implementation status of FPGA internal hardware program, according to the display situation of pilot lamp and hardware program, whether sideslip is run to the whether consistent determining program of the logic control of pilot lamp.
Described clock circuit selects OSC series crystal oscillator.Its clocking, and input to FPGA subelement.
3, advantage and effect: a kind of BMK telemetry with channel selecting function of the present invention switches selects module, its advantage and effect are: can realize program control or manual multiselect one to more than one channel B MK telemetry and switch distribution controlling functions, therefore just can realize an acquisition channel time-sharing multiplex of one piece of BMK Telemetry Data Acquisition card, and then the serial acquisition function to the BMK telemetry sent more than a set of test product can be realized.Thus the quantity of Telemetry Data Acquisition card when significantly can reduce the BMK Telemetry Data Acquisition sent more than a set of test product, save hardware cost, save the bus expansion slot (as: pci bus expansion slot or cpci bus expansion slot) of testing computer system, and cost performance is high, be convenient to integrated use.
Accompanying drawing explanation
The concrete principle assumption diagram of the present invention shown in Fig. 1
The layout of whole PCB design of the present invention shown in Fig. 2
Figure 3 shows that the PCB hierarchical design schematic diagram of the control circuit board in Fig. 2
Figure 4 shows that hardware global design block diagram of the present invention
Figure 5 shows that FPGA subelement configuration module port definition schematic diagram in Fig. 2
Figure 6 shows that in Fig. 4, BMK telemetry receives submodule design drawing
Figure 7 shows that in Fig. 4, BMK telemetry forwards submodule design drawing
Figure 8 shows that the DB37 gang socket front elevation in Fig. 2
Figure 9 shows that the VHDCI50 gang socket front elevation in Fig. 2
Figure 10 shows that 6UEurocard board front panel front elevation in Fig. 2
Figure 11 shows that the timing waveform of BMK telemetry
Figure 12 shows that frame and the frame structure sketch schematic diagram of BMK telemetry
In figure, concrete label declaration is as follows:
The some electronic devices and components of 201 control circuit board 202
The gang socket of 203DB37 signal gang socket 204VDHCI50 signal
2056UEurocard board front panel 401FPGA submodule
402 passage gatings control address buffer subelement 403BMK telemetry and receive submodule
404BMK telemetry forwards submodule 405 Power supply subelement
406 indicating circuit submodule 407 clock circuits
501FPGA chip JTAG configured port defines
502FPGA chip AS configured port defines
1001 front panels fix pincers 1002 attachment screw
Embodiment
See Fig. 1, Fig. 2, Fig. 4, a kind of BMK telemetry with channel selecting function of the present invention switches selects module, and this module comprises: FPGA subelement, Power supply subelement, passage gating control address buffer subelement, BMK telemetry receives submodule, BMK telemetry forwards submodule, indicating circuit submodule and clock circuit.Position annexation between them is position annexation between them and concrete signal trend: centered by FPGA subelement; Power supply subelement is positioned at the upper left side of FPGA subelement, and for FPGA subelement, passage gating controls address buffer subelement, BMK telemetry receives submodule, the forwarding of BMK telemetry submodule, indicating circuit submodule and clock circuit provide direct supply; Passage gating controls the left side that address buffer subelement is positioned at FPGA subelement, for providing passage gating to control address to FPGA subelement, controls to select BMK telemetry receiving cable; BMK telemetry receives submodule and is positioned at below FPGA subelement, for receiving outside BMK telemetry and being transferred to FPGA subelement; BMK telemetry forwards submodule and is positioned at above FPGA subelement, for receiving the BMK telemetry of FPGA subelement output and exporting to BMK telemetry receiving card; Indicating circuit submodule is positioned at FPGA subelement upper right side, for receiving the signal about pilot lamp that FPGA subelement exports; Clock circuit is positioned on the right side of FPGA subelement, for FPGA subelement provides necessary clock signal.
Owing to the present invention be directed to multiple channel B MK telemetries that multiple test product sends, realize programmed control multiselect one and switch distribution controlling functions.But can not illustrate in a specific embodiment, therefore select 1 switching to distribute with 5 and control as an example.
See Fig. 2, hardware of the present invention comprises a control circuit board 201, some electronic devices and components 202, DB37 signal gang socket 203, five VHDCI50 connector body 204, standard 6UEurocard board front panels 205.
Described control circuit board 201 adopts standard Eurocard physical construction, 6U external form, and board is of a size of 233.35mm × 160mm, thickness 1.8mm.
See Fig. 3, described control circuit board 201 adopts the making sheet of standard FR-4 material, 4 layers of PCB design, ground floor (L1) is signals layer 1, the second layer (L2) is stratum, third layer (L3) is bus plane, and the 4th layer (L4) is signals layer 2, and each flaggy thickness is as shown in table 1 below.
The each laminate thickness of table 1
| Level number | Type | Thickness (mils) |
| L1 | 0.60 | |
| Prepreg | 4.00 | |
| L2 | 1.20 | |
| Central layer | 53.4 | |
| L3 | 1.20 | |
| Prepreg | 4.00 | |
| L4 | 0.60 |
Described some electronic devices and components 202 are all welded on described control circuit board, 7 unit are divided into: FPGA subelement according to function, passage gating controls address buffer subelement, BMK telemetry receives submodule, BMK telemetry forwards submodule, Power supply subelement, indicating circuit submodule, clock circuit.
See Fig. 4, described FPGA subelement 401 selects the high-performance of altera corp, CycloneIII Series FPGA---the EP3C40F484C8N of high performance-price ratio.Use VerilogHDL programming development, realize the selection to BMK telemetry, this data selector has five input channels, and each input channel comprises 11 road signals; This data selector has an output channel, and each output channel comprises 11 road signals.The output channel Zhong 11 road signal of this data selector is that the geocoding inputted by outside controls with the corresponding gating of 11 road signal of which input channel, but this data selector only controls which input channel and output channel gating, does not carry out decoding, decode operation to any one input channel.FPGA configuration module is divided into JTAG and AS two kinds of patterns.JTAG is on-line debugging pattern, power on namely available, but power down information is then all lost, and JTAG download port pinout as shown in Figure 5; AS is program Solidification pattern, and use EEPROM save routine, FPGA power down is not lost, and after powering on, FPGA can read configurator from EEPROM, and EEPROM selects EPCS4 chip, and AS download port pinout as shown in Figure 5.
Described passage gating control address buffer subelement 402, the passage gating receiving outside input controls address, or manually toggle switch sets passage gating control address, and inputs to FPGA subelement.Specifically utilize A0-A2 to carry out the passage controlling to select BMK telemetry data transmission.Its particular content is as shown in table 2 below.Due to the restriction of field condition, A0-A2 easily produces interference burr, need come anti-interference by program.
The passage gating of table 2 outside input controls
| A0 | A1 | A2 | Practical function |
| 0 | 0 | 0 | Reset |
| 0 | 0 | 1 | Selector channel 1BMK telemetry |
| 0 | 1 | 0 | Selector channel 2BMK telemetry |
| 0 | 1 | 1 | Selector channel 3BMK telemetry |
| 1 | 0 | 0 | Selector channel 4BMK telemetry |
| 1 | 0 | 1 | Selector channel 5BMK telemetry |
| 1 | 1 | 0 | Manual automatic switchover |
| 1 | 1 | 1 | Reset |
Wherein, when Non-follow control, utilize M0-M2 to realize control.Particular content is as shown in table 3 below.
The manual passage gating of table 3 controls
| M0 | M1 | M2 | Practical function |
| 0 | 0 | 1 | Selector channel 1BMK telemetry |
| 0 | 1 | 0 | Selector channel 2BMK telemetry |
| 0 | 1 | 1 | Selector channel 3BMK telemetry |
| 1 | 0 | 0 | Selector channel 4BMK telemetry |
| 1 | 0 | 1 | Selector channel 5BMK telemetry |
Described BMK telemetry receives submodule 403, be made up of 5 cover optocoupler receiving circuits, often overlap optocoupler receiving circuit Jun You 11 road optocoupler receiving circuit, input to FPGA subelement after one channel B MK telemetry Zhong 22 road signal is converted to 11 road single-ended signals, but do not change the sequential between the address/data/control signal in a channel B MK telemetry.The output circuit level of every suit optocoupler receiving circuit is LVTTL level.Opto-coupler chip selects the SO-8 of Agilent company to encapsulate opto-coupler chip HCPL-063L.HCPL-063L includes 2 road optocoupler passages, and adopt+3.3V to power, output terminal is LVTTL level after pull-up resistor, directly enters the pin of FPGA subelement.As shown in Figure 6.
Wherein, described every suit optocoupler receiving circuit is " 1 " when BMK telemetry Zhong mono-tunnel address/data/control signal is high level, the not conducting of optocoupler receiving circuit, and what corresponding optocoupler exported is exactly high level; When BMK telemetry Zhong mono-tunnel address/data/control signal is low level " 0 ", LEDs ON, what corresponding optocoupler exported is exactly low level.
Described BMK telemetry forwards submodule 404, the 11 road signals that the output channel of data selector in FPGA subelement exports is transformed to the channel B MK telemetry containing 22 road signals, then sends.In fact BMK telemetry forwards submodule is exactly 11 road OC gate output circuits, and its control signal is from FPGA subelement.OC gate output circuit selects TI company SOIC packaged chip ULN2803ADW.Monolithic ULN2803ADW includes 8 road OC doors.Meanwhile, BMK telemetry forwards submodule and also draws 11 tunnel+5V signals, to realize exporting accompaniment signal.As shown in Figure 7.
Wherein, when FPGA subelement exports as high level, OC door exports as low level, enters BMK Telemetry Data Acquisition card together with accompaniment signal; When FPGA subelement exports as low level, OC door exports as high level, enters BMK Telemetry Data Acquisition card together with accompaniment signal.
Described Power supply subelement 405, selects LT1587CM-3.3 and AMS1117-1.5 that+5V voltage is separately converted to+3.3V with+1.5V voltage for providing necessary direct current supply to whole module.Level transferring chip+3.3V and+1.5V input and output pin are all designed with decoupling capacitor, respectively comprise 1 10uF filter capacitor and 1 0.1uF filter capacitor.
Described indicating circuit submodule 406, comprises passage pilot lamp group and FPGA tests pilot lamp group.It is used to indicate passage gating and controls address from outside input or toggle switch, and which channel B MK telemetry of designation data selector switch gating.The BMK telemetry of selector channel 1 is represented when LED1 is bright; The BMK telemetry of selector channel 2 is represented when LED2 is bright; The BMK telemetry of selector channel 3 is represented when LED3 is bright; The BMK telemetry of selector channel 4 is represented when LED4 is bright; The BMK telemetry of selector channel 5 is represented when LED5 is bright. FPGA test instruction is mainly judged the implementation status of FPGA internal hardware program, according to the display situation of pilot lamp and hardware program, whether sideslip is run to the whether consistent determining program of the logic control of pilot lamp.
Described clock circuit 407, for generation of clock signal, and inputs to FPGA subelement.Select OSC series crystal oscillator, produce the frequency of 40MHz.
Described DB37 signal gang socket 203, has double 37 pins, is welded on described control circuit board 201 left side edge place, for transmitting BMK telemetry.BMK telemetry has 11 signal wires and comprises three parts: enable signal EN, and byte judges signal C1 and C2, and data/address multiplex data line D0-D7.What judge BMK telemetry data transmission according to C1, C2 is any content, and as the free time, address, most-significant byte data, least-significant byte data, now D0-D7 is just corresponding data.BMK telemetry after reception by the gang socket of DB37 signal and external unit interconnected.DB37 signal gang socket 203 interface is defined as follows shown in table 4.Figure 8 shows that the DB37 gang socket front elevation in Fig. 2.
The definition of table 4DB socket aperture interface
Five described VHDCI50 connector bodies 204, there are double 50 looper pins, be welded on described control circuit board 201 right side edge place, the air plug respectively by rack back finally interconnects with certain corresponding a set of private adapter, respectively mutually for receiving BMK telemetry.Therefore five VHDCI50 attachment unit interface definition are identical as shown in table 5 below.Figure 9 shows that the VHDCI50 gang socket front elevation in Fig. 2.
The definition of table 5VHDCI50 socket aperture interface
See Figure 10, described 6UEurocard board front panel 205 meets IEEE1101.1 and IEEE1101.10 standard, front panel 205 with EMC O-ring seal to reduce electromagnetic interference (EMI).Front panel 205 is fixed on described control circuit panel edges by 2 attachment screws 1002, near described VHDCI50 connector body 204 side, installs fastness by fixing guarantee of front panel drawing-aid device 1001 simultaneously.Figure 11 shows that the timing waveform of BMK telemetry, Figure 12 shows that frame and the frame structure sketch schematic diagram of BMK telemetry.
Claims (1)
1. the BMK telemetry with channel selecting function switches selects a module, it is characterized in that: this module comprises: FPGA subelement, Power supply subelement, passage gating control address buffer subelement, BMK telemetry receives submodule, BMK telemetry forwards submodule, indicating circuit submodule and clock circuit; Centered by FPGA subelement, Power supply subelement is positioned at the upper left side of FPGA subelement, and it is FPGA subelement, passage gating controls address buffer subelement, BMK telemetry receives submodule, BMK telemetry forwards submodule, indicating circuit submodule and clock circuit provides direct supply; Passage gating controls the left side that address buffer subelement is positioned at FPGA subelement, for providing passage gating to control address to FPGA subelement, controls to select BMK telemetry receiving cable; BMK telemetry receives submodule and is positioned at below FPGA subelement, for receiving outside BMK telemetry and being transferred to FPGA subelement; BMK telemetry forwards submodule and is positioned at above FPGA subelement, for receiving the BMK telemetry of FPGA subelement output and exporting to BMK telemetry receiving card; Indicating circuit submodule is positioned at FPGA subelement upper right side, for receiving the signal about pilot lamp that FPGA subelement exports; Clock circuit is positioned on the right side of FPGA subelement, for FPGA subelement provides necessary clock signal;
CycloneIII Series FPGA selected by described FPGA subelement---EP3C40F484C8N, the multiselect one that this FPGA subelement realizes more than one channel B MK telemetry by hardware program language switches distribution controlling functions, namely realizes the function of a data selector; This data selector has more than one input channel, and each input channel comprises 11 road signals; This data selector has more than one output channel, and each output channel comprises 11 road signals; The output channel Zhong 11 road signal of this data selector is that the geocoding inputted by outside controls with the corresponding gating of 11 road signal of which input channel; This data selector only controls which input channel and output channel gating, does not carry out decoding, decode operation to any one input channel;
Two DC/DC power transfer module selected by described Power supply subelement, is respectively LT1587CM-3.3 and AMS1117-1.5, and direct current+5V is converted to direct current+3.3V ﹑+1.5V respectively, the direct current supply that it provides necessary for giving whole module;
It is control address to the passage gating of outside input or manual toggle switch setting passage gating is controlled to the buffering of address that described passage gating controls address buffer subelement; The passage gating that it receives outside input controls address, or manually toggle switch sets passage gating control address, and inputs to FPGA subelement; The buffering passage gating of outside input being controlled to address utilizes chip 74LCX541MTC, this chip can also increase driving force in addition, mainly gauge tap is manually passed through to the buffering that manual toggle switch setting passage gating controls address, makes corresponding address be high level or low level;
Described BMK telemetry receives submodule, be made up of the optocoupler receiving circuit more than 1 cover, wherein opto-coupler chip selects HCPL-063L, every suit optocoupler receiving circuit Jun You 11 road optocoupler receiving circuit, input to FPGA subelement after one channel B MK telemetry Zhong 22 road signal is converted to 11 road single-ended signals, but do not change the sequential between the address/data/control signal in a channel B MK telemetry; Each optocoupler receiving circuit one end, road is connected with a channel B MK telemetry Zhong mono-road accompaniment signal, and the other end is connected with a channel B MK telemetry Zhong mono-tunnel address/data/control signal; Wherein, the output circuit level of every suit optocoupler receiving circuit is LVTTL level or Transistor-Transistor Logic level; Wherein, described every suit optocoupler receiving circuit is " 1 " when BMK telemetry Zhong mono-tunnel address/data/control signal is high level, the not conducting of optocoupler receiving circuit, and what corresponding optocoupler exported is exactly high level; When BMK telemetry Zhong mono-tunnel address/data/control signal is low level " 0 ", LEDs ON, what corresponding optocoupler exported is exactly low level;
Described BMK telemetry forwards submodule and is made up of SOIC packaged chip ULN2803ADW, the 11 road signals that the output channel of data selector in FPGA subelement exports are transformed to the channel B MK telemetry containing 22 road signals by it, wherein there are 11 road signals to be+5V, then export to BMK telemetry receiving card;
Described indicating circuit submodule comprises passage pilot lamp group and FPGA tests pilot lamp group; It is used to indicate passage gating and controls address from outside input or toggle switch, and which channel B MK telemetry of designation data selector switch gating, FPGA test instruction is mainly judged the implementation status of FPGA internal hardware program, according to the display situation of pilot lamp and hardware program, whether sideslip is run to the whether consistent determining program of the logic control of pilot lamp;
Described clock circuit selects OSC series crystal oscillator, its clocking, and input to FPGA subelement.
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| CN104539281B (en) * | 2014-10-28 | 2018-05-11 | 北京航空航天大学 | A kind of dual port RAM read/write channel switching distribution module with programmable function |
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