CN103534692A - Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device - Google Patents
Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device Download PDFInfo
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- CN103534692A CN103534692A CN201280023566.5A CN201280023566A CN103534692A CN 103534692 A CN103534692 A CN 103534692A CN 201280023566 A CN201280023566 A CN 201280023566A CN 103534692 A CN103534692 A CN 103534692A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017581—Coupling arrangements; Interface arrangements programmable
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Abstract
Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.
Description
the cross reference of related application
Here require rights and interests and the right of priority of the common unsettled same assignee's that submits on May 17th, 2011 U.S. Provisional Patent Application number 61/487046, itself so be incorporated into by reference of text this.
Background technology
Programmable device is known.Conventionally, such as the programmable device of field programmable gate array (FPGA), comprise a plurality of soft logic elements, they can be configured to implement the logic module of customization function.FPGA provides low-cost and solution flexibly for wanting to implement the client of its oneself functional module group.Yet, and comparing such as the hard logic solution of the specific integrated circuit of application (ASIC), FPGA conventionally operation is slower, and needs more power and larger area.On the other hand, ASIC is that dirigibility non-programmable and that therefore provide for the client who wants after structure, hardware to be customized is less.
Thus, there is comprising the mixing apparatus of hard logic and soft logic.The standard feature module that the common enforcement of hard logic may be used in various application, soft logic is realized the function of customization.Yet these equipment are being limited aspect function and dirigibility.Especially, hard logic module often operates with serial mode, and has no chance to walk around in order to support soft logic individual modules.In addition, hard logic module is lock out operation to a great extent, thereby the built-in function of individual hard logic module can not utilize soft logic feature to expand.Therefore, these mixing apparatus still require client that speed and the low-power advantage of hard logic are provided when the dirigibility that needs soft logic to provide.
Summary of the invention
The present invention relates to for mixing the system and method docking between the hard logic element implemented on integrated device and soft logic element.Especially, provide configurable interconnection between hard logic and soft logic, it makes signal between hard logic module and the input and output of soft logic module, to carry out route.This interconnection allows to walk around some hard logic module in order to realize soft logic function.In addition, this interconnection is for example by providing additional signal to allow soft logic to expand the processing of hard logic module to this hard logic module.
According to embodiments of the invention, a kind of integrated device is provided, it has hard logic part, field programmable gate array (FPGA) structure, and the interface that is configured to route signal between this hard logic part and FPGA structure.This hard logic partly comprises a plurality of hard logic modules connected in series, and this FPGA structure comprises steering logic and a plurality of soft logic module.This interface can be configured to selectively the node in this hard logic part (for example, the node in hard logic data routing) is connected to one of one of this soft logic module or this hard logic module in response to the control signal from this steering logic.
According to the other embodiment of the present invention, this first node can be the input for the second hard logic module.Therefore, this interface can be included in and in this hard logic part, be arranged at the multiplexer between these two hard logic modules.This multiplexer can be configured to have the first value (in this control signal, the output of this soft logic module is provided to this input of this second hard logic module in the time of bit value 1 or 0), and the output of this first hard logic module is provided to this second hard logic module when this control signal has the second value.
Another module that this soft logic module can be configured to the upstream from this first hard logic module or this data routing receives input signal.In certain methods, this soft logic module and this first hard logic module are all configured to receive identical input signal.In addition, this steering logic can be configured to close this first hard logic module when selecting this output of this soft logic module to be used for exporting by this multiplexer.
In certain embodiments, this interface comprises combiner circuit and a plurality of multiplexer being arranged in this hard logic part.The first multiplexer can be configured to this combiner circuit, provide data-signal (for example, being provided by this first hard logic module) or null value based on this control signal.Similarly, the second multiplexer can be configured to this combiner circuit, provide the second data-signal (for example, being provided by this soft logic module) and null value based on this control signal.This signal that this combiner circuit can be configured to that these two multiplexers are provided merges and the aforementioned nodes place in this hard logic part exports this signal through merging.
In one approach, this steering logic can (for example, the configuration data based on stored) be determined this first hard logic module that will use separately.Therefore, this steering logic can be configured to this combiner circuit, to provide this this data-signal that the first hard logic module is provided to this first multiplexer.Meanwhile, this steering logic can be configured to provide this null value to this combiner circuit to this second multiplexer.And then this combiner circuit can be configured to this data-signal and this null value to merge, the original data-signal that effectively output is provided by this first hard logic module thus.
In another approach, this steering logic can (for example, the configuration data based on stored) be determined this first soft logic module that will use separately.Therefore, this steering logic can be configured to provide null value to combiner circuit to the first multiplexer, this second multiplexer is configured to combiner circuit, provide this second data-signal (for example, being provided by this soft logic module) simultaneously.This combiner circuit can be configured to this second data-signal and this null value to merge, and the second original data-signal being provided by this soft logic module is provided thus effectively.
In another method, this steering logic can (for example, the configuration data based on stored) be determined this first hard logic module and this first soft logic module that will use together.Therefore, this steering logic can be configured to this combiner circuit, to provide this first data-signal and this second data-signal respectively to this first multiplexer and this second multiplexer.This combiner circuit can be configured to these two data-signals for example to merge, for output (, utilizing logical addition computing).
In certain embodiments, this interface comprises the one or more configurable delay line being arranged among this hard logic part.The first configurable delay line can be configured to delay input signal and provide this delayed input signal to this soft logic module.The second configurable delay line can be configured to the output signal of delay control three multiplexers, and provides this delayed output signal to the 4th and the 5th multiplexer.In this case, the 3rd multiplexer can be configured to this second configurable delay line, provide this first data-signal or this second data-signal based on this control signal.In addition, the 4th multiplexer can be configured to the first multiplexer, provide this first data-signal or this delayed output signal based on delayed control signal, and the 5th multiplexer is configured to this second multiplexer, provide this second data-signal or this delayed output signal based on this delayed control signal.
In certain embodiments, this integrated device comprises the processor subsystem with one or more microcontroller cores.Configuration interface can be arranged among this hard logic part and be coupled to each this hard logic module.This configuration interface can be configured to the parameter that the configuration logic based on from this FPGA structure and/or this processor subsystem receives and provide configuration signal to this hard logic module.
In certain embodiments, this integrated device comprises the debugging interface being arranged in this hard logic part.This debugging interface can be configured to test data based on storing in external memory storage and some sensing point in the data routing that comprises this hard logic module inserts and extract test signal.This external memory storage can be conducted interviews by the Memory Controller of implementing in this FPGA structure or this processor subsystem.
The method that integrated device described above is configured and is operated is also provided.
Accompanying drawing explanation
Consider in conjunction with the drawings following detailed description in detail, further aspect of the present invention and attribute thereof and various advantage will be apparent, and Reference numeral same in accompanying drawing refers to same part all the time, wherein:
Fig. 1 has described the exemplary mixing apparatus with hard logic part and FPGA structure according to one exemplary embodiment of the present invention;
Fig. 2 has described according to the main functional modules of the mixing apparatus of one exemplary embodiment of the present invention;
Fig. 3 has described the illustrative embodiments that is configured to replace with soft logic module the mixing apparatus of hard logic module according to one exemplary embodiment of the present invention;
Fig. 4 has described the illustrative embodiments of mixing apparatus that is configured to test one or more hard logic modules according to one exemplary embodiment of the present invention;
Fig. 5 has described hard logic to be coupled to the illustrative embodiments of the configurable interconnection of soft logic according to one exemplary embodiment of the present invention;
Fig. 6 has described the illustrative embodiments that makes it possible to insert the configurable interconnection of soft logic module in hard logic data routing according to one exemplary embodiment of the present invention;
Fig. 7 has described the illustrative embodiments that makes it possible to expand and/or replace the configurable interconnection of hard logic module according to one exemplary embodiment of the present invention;
Fig. 8 is the process flow diagram of exemplary steps performed while connecting hard logic and soft logic according to the use interface of one exemplary embodiment of the present invention; And
Fig. 9 is the process flow diagram of exemplary steps performed while being configured according to the interface between hard logic and soft logic of one exemplary embodiment of the present invention.
Embodiment
The system and method docking between the hard logic at mixing integrated device and soft logic has been described here.Especially, provide configurable interconnection between hard logic and soft logic, it makes signal between hard logic module and the input and output of soft logic module, to carry out route.This interconnection allows to walk around some hard logic module in order to support soft logic function.In addition, this interconnection is for example by providing additional signal to allow soft logic to expand the processing of hard logic module, for example, for merging with existing signal to hard logic module.This mixing apparatus can be single integrated chip, or in other embodiments, it can be the integrated form of non-monolithic (for example, two moulds in same package) of two or more chips.
Fig. 1 shows exemplary mixing apparatus 100, and it comprises hard logic, soft logic, microprocessor subsystem and according to the interface circuit of some embodiments of the invention.This hard logic comprises interface 110, Memory Controller 112 and hard logic part 114 and 116.Interface 110 comprises the hard logic element for for example, docking by SerDes (SERDES) circuit 142 and external module (, antennal interface).Memory Controller 112 comprises for controlling the hard logic element of the access (that is, read and write) of being undertaken by 140 pairs of external memory storages of interface.Hard logic part 114 and 116 comprise for input signal is processed hard logic element-they can be integrated into hard logic module.For example, hard logic part 114 and 116 can be implemented transceiver function, such as crest factor dwindle, digital pre-distortion, equalization, filtering and/or analog to digital conversion interface.Hard logic can dock with the external module of for example data converter by SERDES circuit 142.
Soft logic comprises FPGA structure 120, its have for input signal is processed a plurality of FPGA (Field Programmable Gate Array) key elements-they can be integrated into soft logic module.FPGA structure 120 also can be implemented transceiver function, and its benefit increasing is that these functions are that client is programmable.These customization soft logic modules are represented by frame 122 in Fig. 1.In some cases, soft logic module can be used to replace with hard logic part 114 and 116 functions of being implemented.In other cases, soft logic module can be used to inputting with generation in hard logic part 114 and 116 functions of being implemented.FPGA structure 120 can dock with hard logic part 114 and 116 by customizable interconnection 150.As will be further explained below, interconnection 150 can be in FPGA (, in FPGA structure 120, implement) control circuit is configured to walk around some hard logic module or provides the input from soft logic to one or more hard logic modules, or vice versa.
Microprocessor subsystem 130 comprises one or more processor cores, for example core 132 and 134.For example, microprocessor subsystem 130 can be the SOC (system on a chip) (SoC) with dual core processor.Microprocessor subsystem 130 can dock with the other parts of this equipment, or uses processor subsystem IO144 to dock with external module.
Should be understood that, the structure of equipment 100 is only exemplary, and can implement both have the mixing apparatus that hard logic also has soft logic with any suitable framework.It should be further understood that, hard logic partly comprises hard logic module, it is implemented for and is not required that the function of customization (being also referred to as " differential ") has realized the function of very lower powered solution-for example, apply specific criteria product (ASSP) function.For example, yet when needs dirigibility with when differential, configurable interconnection (, being connected with the high bandwidth among microprocessor subsystem to hard logic) can be docked with FPGA structure hard logic.Therefore, the merging of hard logic, soft logic and configurable interconnection provides cost efficient, power-efficient and solution flexibly.
In one embodiment, the 28nm geometric manipulations that hard logic part 114 and 116 use allow the frequency with 491Mhz to operate is implemented.Each interconnection can be so that data width bus interface be double, and this point that allows data to identify in the chain of hard logic module is to and from FPGA structure 120 and is transmitted.As discussed above, the current function that FPGA structure can be used to implement differential function or hard logic part is provided is expanded.In one embodiment, FPGA structure 120 use can be processed to implement up to the 28nm low-power of 245Msps with the sample support of each clock period.For example, can support higher sample rate with super sample rate embodiment.Certainly, with upper frequency, be only exemplary, and technology as described herein can be in conjunction with using with equipment lower or that higher frequency operates.In addition, should be understood that, hard logic part and soft logic part can operate with same frequency or different frequency.
Fig. 2 has described the main functional modules according to the mixing apparatus of some embodiments of the invention.Especially, Fig. 2 shows exemplary mixing apparatus 200, and it can be substantially similar to the equipment 100 of Fig. 1.As shown, equipment 200 comprises hard logic 202, FPGA structure 204 and microprocessor subsystem 206, and they can be substantially similar to respectively hard logic part 114 and/or 116, FPGA structure 120 and the microprocessor subsystem 130 of Fig. 1.In one embodiment, equipment 200 docks with the external memory storage 208 of for example Double Data Rate (DDR) storer by direct memory access (DMA) controller 294 of implementing in the soft logic at FPGA structure 204.
As shown, module 212-224 can be connected in series mutually, and the output of one of them module is connected to the input of next module.Should be understood that, module 212-224 is only exemplary, and in certain embodiments, may lack one or more in module 212-224 and/or may comprise one or more other functional modules (not describing).In addition, the order of module 212-224 is only exemplary, and should be understood that, module 212-224 can suitably sequentially arrange arbitrarily.In certain embodiments, can in hard logic 202, implement the additional parallel route of functional module.Therefore, hard logic 202 can comprise the serial chain (for example, being used for carrying out the function of receiver or forwarder front end) with the hard logic module that suitably order is connected arbitrarily of any amount.
In certain embodiments, configuration interface 230 is implemented in FPGA constructs soft processor and/or state machine are controlled.Configuration interface is also supported to be configured from for example ppu of microprocessor subsystem 206.Soft logic or microprocessor can provide configuration signal to the memory mapped configuration interface in hard logic, itself so that can be configured relevant hard logic module.In one embodiment, memory-mapped interface comprises 32 bit ports (for example, interconnecting 246) that for example operate with 245MHz.
Refer again to Fig. 2, soft logic 204 is implemented the programmable functions of any amount.As example, Fig. 2 shows the soft logic module that can be included to support transceiver front-end.Especially, soft logic 204 can comprise seizure impact damper 290, digital pre-distortion (DPD) adaptation module 292 and read/write direct memory access (DMA) controller 294.As shown, soft logic module 290-294 can be connected to each other, or in any other suitable collocation form.It is to be further understood that module 290-294 is only exemplary, and in some implementations, can lack one or more in module 290-294 and/or can implement one or more other soft mode pieces (not describing).In general, soft logic 204 can comprise the serial or parallel chain (for example, being used for carrying out the function of receiver or forwarder front end) of any amount of soft logic module that is connected to each other and/or is connected to the hard logic module of hard logic 202 with any suitably order.
Hard logic detours and implements by signal being carried out to route around in one or more hard logic modules, in some cases, with the customized version in FPGA structure, substitutes the hard logic module being bypassed.For example, if do not need the function of module 216, interconnection 272 can be configured to data-signal to route to FPGA structure 204 from the output of module 214, this signal can directly be delivered to interconnection 274 there, and this interconnection 274 can be configured to this data-signal to route to the input of module 218.As another example, if the function of module 216 will be substituted by soft logic module, interconnect and 272 can be configured to data-signal to route to FPGA structure 204 from the output of module 214, interconnection 274 be processed and be output to this signal can by soft logic module there, and this interconnection 274 can be configured to this data-signal to route to the input of module 218.Below in conjunction with Fig. 3 and 7 pairs, use configurable interconnection to walk around and/or replace hard logic module and carry out more detailed discussion.
Hard logic expands by the input that the soft logic module from FPGA structure 204 routes to hard logic module (or logic element) in hard logic module by signal to be implemented.Therefore especially, hard logic module can be accepted a plurality of inputs and process, and one of those inputs can provide by soft logic, the function of hard logic module is expanded.The signal being provided by soft logic can or can not be from hard logic path data-signal drawn.For example, interconnect and 274 input signal can be provided to can be configured to and accepts the predistortion module 218 of a plurality of inputs from FPGA structure 204.This input signal can be produced by the soft logic module that generates new signal, or is produced by the soft logic module that the signal that for example interconnection of the point of another from hard logic chain receives is processed.
The increase of logic function is by by signal, the point from hard logic chain routes to the soft logic module in FPGA structure and the identical point of sending back in hard logic chain is realized.Therefore, soft logic module quilt " insertion " is among hard logic path.For example, can be by 272 being configured that signal is routed to the soft logic module of being implemented FPGA structure 204 from the output of module 214 to interconnecting, at above-mentioned soft logic module place, processed and route is back to the input of module 216 to this signal, and between module 214 and 216, inserts additional logic module.Below in conjunction with Fig. 3, the 6 and 7 pairs of hard logics, expand and more detailed discussion is carried out in the increase of logic function.
As discussed above and depicted in figure 2, each in interconnection 270-282 can be arranged on the point between the hard logic module of two orders.More generally, interconnection can be connected to the node of any amount of (for example,, between hard logic module and/or within those modules) in hard logic data routing.Yet, should be understood that, this layout is conceptual in essence.Particularly, the quantity of node can be greater than the quantity of available interconnects.For example, in the system of Bandwidth-Constrained, may be this situation.Therefore, can use and select circuit (for example, one or more multiplexers) that available interconnects is connected to the node in hard logic data routing selectively.According to configuration data, this selection circuit can be configured to specific node to be connected with available interconnects (for example, by the steering logic in FPGA, microprocessor subsystem, or when device power by FPGA bit stream).By this way, can the interconnection of limited quantity be connected to the arbitrary node in hard logic data routing based on configuration data.
Fig. 3 has described to be configured to select the illustrative embodiments of equipment 200 of replacing Fig. 2 of hard logic module for soft logic module according to some embodiments of the invention.Especially, Fig. 3 shows exemplary mixing apparatus 300, and it can be substantially similar to the equipment 200 of Fig. 2, but has increased customization predistortion module 330 in FPGA structure 304.As shown, interconnect and 320 can be configured to the output of hard logic module 310 to route to soft logic module 330.And then 322 inputs that can be configured to the output of soft logic module 330 to route to hard logic module 314 interconnect.Therefore, the function of hard logic module 312 is substituted by the function of soft logic module 330.By this way, client can construct 304 to FPGA and programmes to implement customization function and replace any hard logic module in hard logic 302.In addition, in certain embodiments, the steering logic in FPGA structure 304 can be configured to when making while selecting the soft logic module of replacing the hard logic equipment that is bypassed invalid instead using.For example, steering logic can provide signal to configuration interface 316, and this configuration interface 316 can provide the configuration signal that makes the module 312 invalid power consumption of this module (or prevent or minimize).
Fig. 4 has described the illustrative embodiments of equipment 200 that is configured to test one or more hard logic modules according to some embodiments of the invention.Especially, Fig. 4 shows exemplary mixing apparatus 400, and it can be substantially similar to the equipment 200 of Fig. 2, but has the interconnection 428 that couples directly to dma controller 440.As shown, 428 signals that can be configured to that debugging interface 430 is provided that interconnect route to controller 440 to be stored in storer 406.The predetermined sensing point that debugging interface 430 makes it possible to from any hard logic module inserts or extracts data (for example,, for the object of testing).In certain embodiments, in die piece 212-224, only have some can be connected to debugging interface 250, for example hard logic module 212-220(as shown).Connection 420-426 in hard logic 402 routes to debugging interface 430 by the signal of predetermined sensing point, interconnect simultaneously 428 in the future the signal of Self-debugging interface 430 route to FPGA structure 404.In certain embodiments, the two-way test port that 428 formations that interconnect are single 32, provides unified debugging interface thus.In certain embodiments, can supplement debugging interface 430 with the additional debug logic in fpga logic.In such embodiments, interconnecting 428 can be configured to signal to route to debugging soft logic from debugging interface 428, and it can dock with storer by DMA440 subsequently.
In above-mentioned mode, use interconnection 428, debugging interface 430 and is connected 420-426 permission and obtain test data and among any predetermined sensing point is inserted into hard logic data routing from storer 406.Meanwhile, can extract data and be stored in storer 406 at any predetermined sensing point.Test data can help the hard logic module of hard logic 402 to test and debug in insertion and the collection of different sensing points.Should be understood that, also can when soft logic substitutes or expands any hard logic module, use this debug features.For example, Fig. 3 and interconnection depicted in figure 4 can be as shown in respective drawings and be configured time described above.By this way, debugging interface 430 also can be used to test the integrated of hard logic module and soft logic module.
Fig. 5 has described hard logic to be coupled to the illustrative embodiments of the configurable interconnection of soft logic according to some embodiments of the invention.Especially, Fig. 5 shows exemplary interconnection 500, and it can be substantially similar to any interconnection 270-282 of Fig. 2.As shown, 500 two interconnection 520 and 522 separately that comprise for route data between FPGA structure and hard logic that interconnect.Interconnection 520 is used to data to route to hard logic 502 from FPGA structure 504, interconnects 522 to be used to data to route to FPGA structure 504 from hard logic 502.In certain embodiments, FPGA structure operates with half speed of hard logic.Therefore,, when being provided data from FPGA structure 504 to hard logic 502, two data words can parallel transfers and in hard logic, are serialized subsequently.This serialization can be performed in bit level or word level.For example, two data words can be carried out serialization in hard logic in word level, provide word thus with serial mode to hard logic module.Therefore as shown, interconnect and 520 can comprise that serializer circuit 510 is to carry out serialization to two data words.Similarly, when from hard logic 502 to FPGA, structure 504 provides data, two data words can provide by parallelization and to FPGA structure in hard logic.Therefore as shown, interconnect and 522 can comprise that parallelization circuit 512 is to carry out parallelization to two data words.By this way, handling capacity reaches balance between hard logic faster and slower FPGA structure.
Fig. 6 has described making it possible to the illustrative embodiments of the configurable interconnection among soft logic module insertion hard logic data routing according to some embodiments of the invention.Especially, Fig. 6 shows exemplary interconnection 620, and it can be substantially similar to any interconnection 270-282 of Fig. 2.As shown, interconnect and 620 between hard logic 602 to FPGA structure 604, data-signal is carried out to route.Interconnection 620 comprises for construct the interconnection 624 that signal is provided from hard logic to FPGA, for construct the interconnection 626 that signal is provided to hard logic and multiplexer 622 from FPGA.Multiplexer 622 is configured to export one of the signal receiving from hard logic and the signal receiving from soft logic according to whether soft logic module being added into data routing.For example, for soft logic module 614 being inserted among hard logic data routing, interconnecting 624 routes to soft logic module 614 by the output of hard logic module 610.614 pairs of these signals of soft logic module are processed, and interconnect and 626 treated signal is routed to multiplexer 622, and it also directly receives undressed output from logic module 610.The signal that multiplexer 622 discretionary interconnections 626 provide is to be inserted into soft logic module among hard logic data routing, and hard logic module 612 receives treated signal.On the other hand, the signal that multiplexer 622 selection logic modules 610 provide is to walk around soft logic module, and in this case, hard logic module 612 directly receives undressed signal from module 610.
Should be understood that, Fig. 6 is the diagram of simplifying, and other suitable assembly can provide additional function.For example, can implement serialiser described in conjunction with Figure 5 and deserializer circuit compensates with the throughput information in FPGA structure.In addition, as shown in Figure 7, the circuit of Fig. 6 can utilize and make it possible to hard logic module to expand and/or the adjunct circuit replaced expands.
Fig. 7 described according to some embodiments of the invention make it possible to hard logic module is expanded and/or the illustrative embodiments of the configurable interconnection of replacing.Especially, Fig. 7 shows hard logic part 702 and FPGA structure 704.Hard logic part 702 can comprise hard logic module 710, multiplexer 720-728, combiner 730 and configurable delay line 740 and 742.FPGA structure 704 can comprise soft logic module 712.As will be described, the arrangement of components of describing allows hard logic module 710 to be substituted by soft logic module 712, or for using 712 pairs of hard logics of soft logic module to expand.In the latter's method, delay circuit has guaranteed any of processing speed between hard logic and soft logic assembly not mate and compensate.
When only need hard logic module 710 to provide function time, multiplexer 720-728 can be configured to the output of hard logic module 710 directly to deliver to combiner 730, it can export the signal as received subsequently.Especially, the data-signal that module 710 is exported is directly provided to multiplexer 722, and it is configured to this data-signal to deliver to multiplexer 726.Multiplexer 726 is configured to this data-signal to deliver to combiner 730 equally, and the null value that it exports multiplexer 728 merges (for example, being added) to this data-signal.In certain methods, may wish before merged device 730 outputs of the data-signal of exporting in hard logic module 710, it to be postponed.In this case, the data-signal that multiplexer 722 is configured to make delay line 742 export passes through, and this delay line 742 is set to provide the delay of desired quantity.Delay line 742 receives data-signal by multiplexer 720 from hard logic module 710, and this multiplexer 720 is configured to make its data-signal receiving from logic module 710 to pass through.
When soft logic module 712 will substitute hard logic module 710, multiplexer 720-728 can be configured to the output of soft logic module 712 directly to deliver to combiner 730, and it can export the signal as received subsequently.Especially, the data-signal of being exported by soft logic module 712 is directly provided to multiplexer 724, and it is configured to this data-signal to deliver to multiplexer 728.Multiplexer 728 is configured to this data-signal to deliver to combiner 730 equally, and the null value that it exports multiplexer 726 merges (for example, being added) to this data-signal.In certain methods, may be desirably in merged device 730 outputs of the data-signal of being exported by soft logic module 712 and before it be postponed.In this case, the data-signal that multiplexer 724 is configured to make delay line 742 export passes through, and this delay line 742 is set to provide the delay of desired quantity.Delay line 742 receives data-signal by multiplexer 720 from soft logic module 712, and this multiplexer 720 is configured to make its data-signal receiving from soft logic module 712 to pass through.
When hard logic module 710 will merge with soft logic module 712, multiplexer 720-728 can be configured to the output of the output of hard logic module 710 and soft logic module 712 to deliver to combiner 730, it can merge this signal (for example subsequently, be added) together, and the signal of output through merging.Especially, when unnecessary delay, multiplexer 722 and 726 signals that module 710 can be provided are directly delivered to combiner 730.Similarly, multiplexer 724 and 728 can directly be delivered to combiner 730 by the signal being provided by module 712.When needs postpone hard logic signal (for example, due in FPGA more slowly or longer processing), multiplexer 720 can provide the data-signal from module 710 to delay line 742, it can postpone hard logic signal with desired amount.Multiplexer 722 and 726 can directly be delivered to combiner 730 by delayed signal subsequently.Similarly, when needs postpone soft logic signal (for example, due in hard logic more slowly or longer processing), multiplexer 720 can will be delivered to delay line 742 from the data-signal of module 712, it can postpone soft logic signal with desired amount.Multiplexer 724 and 728 can directly be delivered to combiner 730 by delayed signal subsequently.
Should be understood that, the layout of Fig. 7 is only exemplary, and can remove as required or increase one or more assemblies.For example, multiplexer 720,722 and 724 and delay line 742 can be removed, and delay line 740 can be used to before signal is received by module 712, it be postponed.Choosing is for ground or additionally, delay line 740 can be removed together.Combiner circuit 730 can be totalizer, or is suitable for merging any other circuit of two or more signals.In addition, Fig. 7 can integrate in conjunction with Fig. 5 and 6 shown and described any assemblies.
Fig. 8 shows for using interface to connect the illustrative process 800 of hard logic and soft logic.In step 802, data routing configuration data can be received by the steering logic in the structure of FPGA for example.This data routing configuration data for example can be stored in, in external memory storage (, the storer 208 of Fig. 2) and the memory access equipment in FPGA constructs (for example, the DMA294 in Fig. 2) obtains.In step 804, the configuration data that steering logic can be based on obtained and the interface between hard logic part and FPGA structure is configured.For example, as explained above, steering logic can be configured to walk around hard logic module to any interconnection 270-282, utilizes soft logic module to substitute hard logic module, among soft logic module data inserting path, or from the signal of soft logic, expand hard logic by route.Therefore, steering logic can be configured any assembly of describing in conjunction with Fig. 5-7 He discuss.Especially, steering logic can be configured one or more multiplexers, serialiser or deserializer circuit and/or delay line.In other embodiments, except steering logic or as it, substitute, processor subsystem can be configured these assemblies.For example, processor subsystem can be configured the interface between hard logic part and FPGA structure by the configuration data based on obtained.
In step 806, this interface can for example, be connected to soft logic module or hard logic module by the node in hard logic data routing (, between two hard logic modules or within hard logic module) based on configuration.For example, with reference to figure 6, this interface can be connected to the input of logic module 612 according to configuration the output of hard logic module 610 or soft logic module 614.As another example, with reference to figure 7, the two can be connected to combiner 730 one of module 710 and module 712 or its.In any situation, configuration data is used for as required multiplexer and/or delay line being configured by steering logic and/or processor subsystem.
Fig. 9 shows the exemplary processes 900 being configured for the interface between hard logic and soft logic.Processing 900 can (for example,, by steering logic and/or processor subsystem) carry out as the part of the step 804 of Fig. 8.In step 902, from data routing configuration data specified data path configurations.That is to say, steering logic and/or processor subsystem are from memory read data and determine which interconnection will be configured and how they will be configured.Especially, can be for each hard logic module execution step 904-914 of hard logic chain.In step 904, steering logic and/or processor subsystem determine whether to use separately given hard logic module, by soft logic module, are not expanded or substitute.If so, this processing proceeds to step 906, and wherein interface (for example, interconnection, multiplexer and/or delay line) is configured to hard logic module to be connected to data routing.In step 908, steering logic and/or processor subsystem determine whether to use separately given soft logic module, substitute hard logic module.If so, this processing proceeds to step 910, and wherein interface (for example, interconnection, multiplexer and/or delay line) is configured to the alternative hard logic module of soft logic module to be connected to data routing.Finally, in step 912, steering logic and/or processor subsystem determine whether given hard logic module will be used in conjunction with soft logic module.If so, this processing proceeds to step 914, and wherein interface (for example, interconnection, multiplexer and/or delay line) is configured to hard logic module to be connected to soft logic module.For example,, by the output of each module is connected to combiner circuit.
In practice, processing the one or more steps shown in 800 and 900 can merge with other step, with suitable arbitrarily order, carries out, and parallel (for example, while or in fact while) carries out, or is removed.For example, unless it is definite to some extent in addition, otherwise steering logic and/or processor subsystem can connect all hard logic modules defaultly.Therefore, step 904 and 906 can be removed, and hard logic module can be only in response to determining and need such configuration be just replaced or expand from configuration data.In certain embodiments, interface (for example, interconnection, multiplexer and/or delay line) is configured by FPGA bit stream when device power.For example, multiplexer can be used as the part of FPGA configuration routine and use the data that are stored in config memory (CRAM) to be configured.Finally, processing 800 and/or 900 can implement with any suitable merging of hardware and/or software in any appropriate manner.For example, as discussed above, the two can be connected the steering logic in FPGA structure and one of processor subsystem or its and be configured with interface various hard logic modules, soft logic module.In the embodiment for example, being configured by FPGA bit stream (, using CRAM) during in device power at interface, steering logic and processor subsystem can or in addition docking port carry out dynamic-configuration.
During the embodiment of the present invention described above, for explanation, unrestriced object is given, and the present invention is only limited by following claim.
Claims (20)
1. an integrated device, comprising:
Hard logic part, comprises a plurality of hard logic modules;
Field programmable gate array (FPGA) structure, comprises steering logic and a plurality of soft logic module; And
Interface, is configured to route signal between described hard logic part and described FPGA structure;
Wherein, in response to the control signal from described steering logic, described interface is further configured to optionally the first node in described hard logic part is coupled to one of the first soft logic module in described a plurality of soft logic module and first hard logic module in described a plurality of hard logic module.
2. integrated device according to claim 1, wherein said first node is the input of going to the second hard logic module in described a plurality of hard logic module, and wherein said interface is included in described hard logic part and is arranged at the multiplexer between described the first hard logic module and described the second hard logic module, and described multiplexer is configured to:
The output of described the first soft logic module when having the first value, described control signal is provided to described the second hard logic module; And
The output of described the first hard logic module when having the second value, described control signal is provided to described the second hard logic module.
3. integrated device according to claim 2, wherein said the first soft logic module is configured to receive input signal from described the first hard logic module.
4. integrated device according to claim 2, wherein said the first soft logic module and described the first hard logic module are configured to receive identical input signal separately, and the described output that is configured to select described the first soft logic module when described multiplexer of wherein said steering logic when exporting by described the first hard logic module power-off.
5. integrated device according to claim 1, wherein said interface comprises combiner circuit and a plurality of multiplexer being arranged in described hard logic part, and wherein:
The first multiplexer in described a plurality of multiplexer is configured to described combiner circuit, provide one of the first data-signal and signal value of zero based on described control signal, and wherein said the first data-signal is provided by described the first hard logic module;
The second multiplexer in described a plurality of multiplexer is configured to described combiner circuit, provide one of the second data-signal and described signal value of zero based on described control signal, and wherein said the second data-signal is provided by described the first soft logic module; And
Described combiner circuit is configured to the described signal being provided by described the first multiplexer and described the second multiplexer to merge, and the signal of the output of the described first node place in described hard logic part through merging.
6. integrated device according to claim 5, wherein will be used separately described the first hard logic module in response to determining:
Described steering logic is configured to provide described the first data-signal to described combiner circuit to described the first multiplexer; And
Described steering logic is configured to provide described signal value of zero to described combiner circuit to described the second multiplexer;
Wherein said combiner circuit is configured to described the first data-signal and described signal value of zero to merge.
7. integrated device according to claim 5, wherein, will be used separately described the first soft logic module in response to determining:
Described steering logic is configured to provide described signal value of zero to described combiner circuit to described the first multiplexer; And
Described steering logic is configured to provide described the second data-signal to described combiner circuit to described the second multiplexer;
Wherein said combiner circuit is configured to described signal value of zero and described the second data-signal to merge.
8. integrated device according to claim 5, wherein, will be used described the first hard logic module and described the first soft logic module together in response to determining:
Described steering logic is configured to provide described the first data-signal to described combiner circuit to described the first multiplexer; And
Described steering logic is configured to provide described the second data-signal to described combiner circuit to described the second multiplexer;
Wherein said combiner circuit is configured to described the first data-signal and described the second data-signal to merge.
9. integrated device according to claim 5, wherein said interface further comprises a plurality of configurable delay line being arranged in described hard logic part, and wherein:
The first configurable delay line in described a plurality of configurable delay line is configured to delay input signal and provides delayed input signal to described the first soft logic module;
The second configurable delay line in described a plurality of configurable delay line is configured to postpone the output signal of the 3rd multiplexer in described a plurality of multiplexer, and provides delayed output signal to the 4th multiplexer in described a plurality of multiplexers and the 5th multiplexer in described a plurality of multiplexer;
Described the 3rd multiplexer is configured to described the second configurable delay line, provide one of described the first data-signal and described second data-signal based on described control signal;
Described the 4th multiplexer is configured to described the first multiplexer, provide one of described the first data-signal and described delayed output signal based on delayed control signal; And
Described the 5th multiplexer is configured to described the second multiplexer, provide one of described the second data-signal and described delayed output signal based on described delayed control signal.
10. an integrated device, comprising:
Hard logic part, comprises one or more hard logic modules;
Field programmable gate array (FPGA) structure, comprises configuration logic; And
Configuration interface, be arranged in described hard logic part and be coupled to one or more hard logic modules, the data-signal that wherein said configuration interface is configured to the described configuration logic reception based on from described FPGA structure provides configuration signal to described one or more hard logic modules.
11. integrated devices according to claim 10, further comprise processor subsystem, described processor subsystem comprises one or more microcontroller cores, and the second data-signal that wherein said configuration interface is further configured to based on receiving from described processor subsystem provides described configuration signal to described one or more hard logic modules.
12. integrated devices according to claim 10, further comprise the debugging interface being arranged in described hard logic part, the test data that wherein said debugging interface is configured to based on storing in storer is externally inserted and extracts test signal in the data routing that comprises described one or more hard logic modules, and wherein said external memory storage is conducted interviews by the Memory Controller of implementing in described FPGA structure.
13. 1 kinds of methods for docking between the hard logic part at integrated device and FPGA structure, described method comprises:
Use the steering logic in described FPGA structure to obtain data routing configuration data from storer;
Based on described data routing configuration data, utilize described steering logic to be configured the interface between described hard logic part and described FPGA structure, in wherein said configuration specified data path, whether comprise one or more hard logic modules in described hard logic part and the one or more soft logic modules in described FPGA structure; And
Based on described interface configuration, utilize described interface that the node in described hard logic part is coupled to one of the first soft logic module in described one or more soft logic module and first hard logic module in described one or more hard logic module.
14. methods according to claim 13, further comprise:
From described data routing configuration data, determine whether to use separately described the first hard logic module; And
In response to determining, to use separately described the first hard logic module, described interface is configured to the node in described hard logic part is coupled to the output of described the first hard logic module, and the output of wherein said the first soft logic module disconnects from described data routing.
15. methods according to claim 13, further comprise:
From described data routing configuration data, determine whether to use separately described the first soft logic module;
In response to determining, to use separately described the first soft logic module, described interface is configured to the node in described hard logic part is coupled to the output of described the first soft logic module; And
By described the first hard logic module power-off.
16. according to the method for claim 13, further comprises:
From described data routing configuration data, determine whether to use together described the first hard logic module and described the first soft logic module; And
In response to determining, to use together described the first hard logic module and described the first soft logic module, described interface is configured to the node in described hard logic part is coupled to the circuit arrangement that the output of the output of described the first hard logic module and described the first soft logic module is merged.
17. methods according to claim 13, further comprise:
Use the first configurable delay line to postpone the output of described the first hard logic module, the relative throughput speed of wherein said output and described FPGA structure postpones pro rata; And
Use the second configurable delay line to postpone the output of described the first soft logic module, the relative throughput speed of wherein said output and described the first hard logic module postpones pro rata.
18. methods according to claim 13, further comprise:
Utilize configuration interface in described hard logic part to receive configuration data from one of processor subsystem and configuration logic of implementing described FPGA structure; And
Based on described configuration data, utilize described configuration interface to provide a plurality of configuration signal to described one or more hard logic modules.
19. methods according to claim 13, further comprise:
The Memory Controller that use is implemented in described FPGA structure utilizes the debugging interface in described hard logic part to receive test data from external memory storage;
Utilize the first sensing point place of described debugging interface in described hard logic part to insert described test data;
Utilize the second sensing point place of described debugging interface in described hard logic part to extract tune-up data; And
Use described Memory Controller that extracted tune-up data is stored in described external memory storage.
20. methods according to claim 13, wherein said interface comprises a plurality of available interconnects, described method further comprises:
Based on described data routing configuration data, determine whether the one or more data routing nodes in described hard logic part will be connected to described FPGA structure; And
Based on described definite described one or more data routing nodes in described hard logic part that optionally described a plurality of available interconnects are coupled to.
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| US20120319730A1 (en) | 2012-12-20 |
| US8629691B2 (en) | 2014-01-14 |
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| JP2014513507A (en) | 2014-05-29 |
| WO2012158947A3 (en) | 2013-03-21 |
| WO2012158947A2 (en) | 2012-11-22 |
| US20140125379A1 (en) | 2014-05-08 |
| US9000802B2 (en) | 2015-04-07 |
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