CN103578951B - The manufacture method of semiconductor element - Google Patents
The manufacture method of semiconductor element Download PDFInfo
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- CN103578951B CN103578951B CN201210282153.0A CN201210282153A CN103578951B CN 103578951 B CN103578951 B CN 103578951B CN 201210282153 A CN201210282153 A CN 201210282153A CN 103578951 B CN103578951 B CN 103578951B
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- insulating barrier
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- semiconductor element
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
The invention discloses a kind of manufacture method of semiconductor element.Substrate has the firstth district, the secondth district and the 3rd district.The first insulating barrier is formed to the substrate being less than the firstth district and the secondth district.The second insulating barrier is formed on the substrate in the 3rd district.Inhibition zone is formed in the substrate in the secondth district.Remove the first insulating barrier.On substrate, form the 3rd insulating barrier, wherein the thickness of the 3rd insulating barrier on inhibition zone is less than the thickness of the 3rd insulating barrier in the firstth district.Conductor material layer is formed on substrate.Carry out patterning step, to form most first grid structures in the firstth district, to form at least one second grid structure and form at least one 3rd grid structure in the secondth district in the 3rd district.
Description
Technical field
The invention relates to a kind of manufacture method of electronic component, and relate to a kind of manufacture method of semiconductor element especially.
Background technology
Semiconductor element reduces costs and the demand of Simplified flowsheet step to reach, cell region (memorycell) is integrated with the element of surrounding zone (peripherycell) and becomes a kind of trend gradually on the same wafer, such as flash memory and logic circuit component are integrated on the same wafer, be then referred to as embedded flash memory (embeddedflashmemory).
In embedded flash memory, surrounding zone comprises low voltage component district and high voltage device district often.In general existing technique, the thickness of the gate insulation layer in low voltage component district belongs to the gate insulation layer of cell region and makes with technique, and thickness is each other suitable.But this kind of technology mode will make the usefulness in low voltage component district limited, cause the electrically not good of embedded flash memory.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of manufacture method of semiconductor element, it can manufacture relative to the gate insulation layer of the thinner thickness of cell region in low voltage component district, to provide semiconductor element good electrical.
The invention provides a kind of manufacture method of semiconductor element.There is provided substrate, substrate has the firstth district, the secondth district and the 3rd district.The first insulating barrier is formed to the substrate being less than the firstth district and the secondth district.The second insulating barrier is formed on the substrate in the 3rd district.Inhibition zone is formed in the substrate in the secondth district.Remove the first insulating barrier.On substrate, form the 3rd insulating barrier, wherein the thickness of the 3rd insulating barrier on inhibition zone is less than the thickness of the 3rd insulating barrier in the firstth district.Conductor material layer is formed on substrate.Carry out patterning step, to form most first grid structures on the substrate in the firstth district, to form at least one second grid structure and form at least one 3rd grid structure on the substrate in the secondth district on the substrate in the 3rd district.
In one embodiment of this invention, the method forming above-mentioned inhibition zone is included on substrate and forms patterning photoresist layer, to expose first insulating barrier in the secondth district; And carry out nitrogen implantation technique.
In one embodiment of this invention, above-mentioned nitrogen implants the implant dosage of technique is every square centimeter about 10
13~ 10
15individual atom, implanting energy is about 13 ~ 17KeV.
In one embodiment of this invention, the thickness of above-mentioned inhibition zone is about 10 dust ~ 90 dusts.
In one embodiment of this invention, in the step forming above-mentioned 3rd insulating barrier, the nitrogen in inhibition zone disengages from substrate.
In one embodiment of this invention, the method forming above-mentioned 3rd insulating barrier comprises carries out thermal oxidation method.
In one embodiment of this invention, the method forming above-mentioned first insulating barrier is included on substrate and forms insulation material layer; And remove portions of insulating material layer, to expose the section substrate in the 3rd district, remaining insulation material layer forms the first insulating barrier.
In one embodiment of this invention, the method forming above-mentioned second insulating barrier comprises carries out thermal oxidation method.
In one embodiment of this invention, the thickness of above-mentioned 3rd insulating barrier in the firstth district is less than the thickness of the second insulating barrier.
In one embodiment of this invention, above-mentioned firstth district is cell region, and the secondth district is low voltage component district, and the 3rd district is high voltage device district.
Based on above-mentioned, when semiconductor element of the present invention is applied to embedded flash memory, can prior to carrying out nitrogen implantation in low voltage component district, then carry out the making of gate insulation layer in cell region and low voltage component district.Thus, the gate insulation layer of the thinner thickness relative to cell region can be manufactured in low voltage component district.Utilizing the process of this kind of semiconductor element, when not affecting cell region electrical, the gate insulation layer that low voltage component district is thinner can be provided, to improve the overall efficiency of semiconductor element.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
The generalized section of semiconductor element of Figure 1A to 1H for illustrating according to one embodiment of the invention.
Wherein, description of reference numerals is as follows:
100: substrate;
100a: the first district;
100b: the second district;
100c: the three district;
102: insulation material layer;
102a: the first insulating barrier;
104: cover curtain material layer;
104a: cover curtain layer;
106,110: patterning photoresist layer;
108, the 108a: the second insulating barrier;
112: nitrogen implants technique;
114: inhibition zone;
116, the 116a: the three insulating barrier;
118: conductor material layer;
118a, 118b, 118c: conductor layer;
120: first grid structure;
122: second grid structure;
124: the three grid structures.
Embodiment
The generalized section of semiconductor element of Figure 1A to 1H for illustrating according to one embodiment of the invention.
First, please refer to Figure 1A, substrate 100 is provided.Substrate 100 is such as silicon substrate.Substrate 100 has the first district 100a, the second district 100b and the 3rd district 100c.In addition, there is multiple isolation structure (not illustrating) in substrate 100.Isolation structure is such as shallow trench isolation (STI) structure.First district 100a, the second district 100b of substrate 100 and the 3rd district 100c are isolated from each other by isolation structure.It should be noted that, when utilizing the manufacture method of semiconductor element of the present invention to manufacture embedded flash memory, first district 100a is such as cell region, the second district 100b is such as low voltage component district and the 3rd district 100c is such as high voltage device district, but the present invention is not as limit.
Then, on substrate 100, insulation material layer 102 is formed.The material of insulation material layer 102 is such as silicon dioxide, and its formation method comprises and carries out thermal oxidation method.Afterwards, on insulation material layer 102, cover curtain material layer 104 is formed.The material of cover curtain material layer 104 is such as silicon nitride, silica, silicon oxynitride or its composition.The formation method of cover curtain material layer 104 comprises carries out chemical gaseous phase Shen area method or physical vapor Shen area method.Then, patterning photoresist layer 106 is applied on cover curtain material layer 104.
Please refer to Figure 1B, be cover curtain with patterning photoresist layer 106, sequentially remove the part cover curtain material layer 104 on the substrate 100 of the 3rd district 100c and portions of insulating material floor 102, so that be less than formation first insulating barrier 102a and cover curtain layer 104a on the first district 100a and the second district 100b, and expose the section substrate 100 of the 3rd district 100c.The above-mentioned technique that removes comprises and carries out etch process.And then, patterning photoresist layer 106 is removed.In one embodiment, optionally carry out cineration technics, to guarantee that patterning photoresist layer 106 is removed completely.In the present embodiment, remove the section substrate 100 that technique only removes the 3rd district 100c although above-mentioned, the present invention is not as limit.In another embodiment, whole substrates 100 of also removable 3rd district 100c.In this case, the first insulating barrier 102a is only formed on the substrate 100 of the first district 100a and the second district 100b.
Moreover although in the present embodiment to remove the mode of portions of insulating material layer 102 to form the first insulating barrier 102a, the present invention does not limit the generation type of the first insulating barrier 102a.That is, in other embodiments, also can use other modes be applicable to and directly on the substrate 100 of the first district 100a and the second district 100b, form the first insulating barrier 102a.
Please refer to Fig. 1 C, on the substrate 100 of the 3rd district 100c, form the second insulating barrier 108.The formation method of the second insulating barrier 108 comprises carries out thermal oxidation method.In the present embodiment, the second insulating barrier 108 is formed on the section substrate 100 of the 3rd district 100c, and extends to because of beak effect in the first insulating barrier 102a around it (as shown in Figure 1 C).Moreover in the present embodiment, although the second insulating barrier 108 is only formed on the section substrate 100 of the 3rd district 100c, the present invention is not as limit.In another embodiment, the second insulating barrier 108 also can be formed on whole substrates 100 of the 3rd district 100c.In addition, in the step of formation the 3rd insulating barrier 108, also can form oxidation film layer (not illustrating) on the surface of cover curtain layer 104a simultaneously.In one embodiment, after the step of formation the 3rd insulating barrier 108, also can optionally carry out a wet dip (wetdip) technique, to remove the native oxide (nativeoxidelayer) on the 3rd insulating barrier 108 surface.Above-mentioned wet dip technique also can remove the oxidation film layer on cover curtain layer 104a surface simultaneously.Afterwards, cover curtain layer 104a is removed.
Please refer to Fig. 1 D, on substrate 100, form patterning photoresist layer 110, to expose the first insulating barrier 102a of the second district 100b.Then, carry out nitrogen and implant technique 112, to form inhibition zone 114 in the substrate 100 of the second district 100b.Special instruction ground is that, although among the present embodiment, inhibition zone 114 is only formed in the section substrate 100 of the second district 100b, and the present invention is not as limit.In another embodiment, inhibition zone 114 also can be formed in whole substrates 100 of the second district 100b.The formation method of inhibition zone 114 comprises with every square centimeter about 10
13~ 10
15the nitrogen that the implant dosage of individual atom and the implantation energy of about 13 ~ 17KeV carry out implants technique 112.The thickness of inhibition zone 114 is about 10 dust ~ 90 dusts, is more preferred from 10 dust ~ 70 dusts.
Please refer to Fig. 1 E, remove the patterning photoresist layer 110 on substrate 100.In one embodiment, optionally carry out cineration technics, to guarantee that patterning photoresist layer 110 is removed completely.Then, the first insulating barrier 102a is removed, to expose the substrate 100 of the first district 100a and the second district 100b.The removing method of the first insulating barrier 102a comprises and carries out etch process.
It is to be particularly noted that in the present invention, be that the nitrogen first carried out for the formation of inhibition zone 114 implants technique 112, then remove the first insulating barrier 102a.That is, when carrying out nitrogen to the second district 100b and implanting technique 112, the first insulating barrier 102a on the second district 100b can be used as the resilient coating of protection second district 100b, implants to avoid nitrogen substrate 100 surface that technique 112 destroys the second district 100b.
Please refer to Fig. 1 F, the 3rd insulating barrier 116 is formed on substrate 100, wherein, because the nitrogen in inhibition zone 114 can suppress the speed of growth of the 3rd insulating barrier 116, therefore the thickness of the 3rd insulating barrier 116 on inhibition zone 114 can be less than the thickness of the 3rd insulation layer 116 in the first district 100a.The method forming the 3rd insulating barrier 116 comprises carries out thermal oxidation method.In the present embodiment, the 3rd insulating barrier 116 is less than again the thickness of the second insulating barrier 108 in the thickness of the first district 100a.
It is to be particularly noted that in the step of formation the 3rd insulating barrier 116, the nitrogen in inhibition zone 114 disengages from substrate 100.Therefore, in Fig. 1 F with represented by dotted arrows inhibition zone 114.In specific words, in boiler tube growth regulation three insulating barrier 116 step in, carry out low-pressure suction (purge), therefore in inhibition zone 114, nitrogen upwards disengages from substrate 100, but not diffuses in substrate 100 simultaneously.From another viewpoint, can be considered in the semiconductor element finally completed (as shown in fig. 1h), nitrogen that is not residual or only residual minim is implanted the nitrogen that technique 112 is implanted.Therefore, the nitrogen that nitrogen implantation technique 112 is implanted can't affect in fact the usefulness of semiconductor element.
Please refer to Fig. 1 G, on substrate 100, form conductor material layer 118.Conductor material layer 118 is comprehensive to be covered on the second insulating barrier 108 and the 3rd insulating barrier 116.The material of conductor material layer 118 is such as polysilicon, and its formation method comprises and carries out chemical vapour deposition technique.
Then, please refer to Fig. 1 H, carry out patterning step, to form most first grid structures 120 on the substrate 100 of the first district 100a, form at least one second grid structure 122 and form at least one 3rd grid structure 124 on the substrate 100 of the second district 100b on the substrate 100 of the 3rd district 100c.Each first grid structure comprises conductor layer 118a and is arranged in below conductor layer 118a and is positioned at the 3rd insulating barrier 116a of the first district 100a.Second grid structure 122 comprises conductor layer 118b and is arranged in below conductor layer 118b and is positioned at the 3rd insulating barrier 116a of the second district 100b.3rd grid structure 124 comprises the second insulating barrier 108a of conductor layer 118c and below thereof.So far, the making of semiconductor element of the present invention is completed.
In sum, the present invention forms inhibition zone 114 in the substrate 100 of the second district 100b.The thickness of the 3rd insulating barrier 116 that inhibition zone 114 can suppress technique after a while to be formed.That is the thickness on the inhibition zone 114 of the 3rd insulating barrier 116 in the second district 100b is less than the 3rd insulating barrier 116 in the thickness of the first district 100a.When semiconductor element of the present invention is embedded flash memory, and the first district 100a be cell region, the second district 100b is when being low voltage component district, method of the present invention can make the thickness of the gate insulation layer in low voltage component district be less than the thickness of the gate insulation layer of cell region.Again, because compared to the manufacture method of prior art, manufacture method of the present invention there is no the thickness of the 3rd insulating barrier 116 changing any first district 100a (i.e. cell region).Therefore when not affecting the galvanic element of cell region, effectively can reduce the thickness of the gate insulation layer in low voltage component district, to provide the good electrical property efficiency of embedded flash memory.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; technical staff in any art; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended right person of defining that applies for a patent.
Claims (10)
1. a manufacture method for semiconductor element, comprising:
There is provided a substrate, this substrate has one first district, one second district and one the 3rd district;
One first insulating barrier is formed to this substrate being less than this firstth district and this secondth district;
One second insulating barrier is formed on this substrate in the 3rd district;
An inhibition zone is formed in this substrate in this secondth district;
Remove this first insulating barrier;
On this substrate, form one the 3rd insulating barrier, wherein the thickness of the 3rd insulating barrier on this inhibition zone is less than the thickness of the 3rd insulating barrier in this firstth district;
A conductor material layer is formed on this substrate; And
Carry out a patterning step, to form most first grid structures on this substrate in this firstth district, form at least one second grid structure and form at least one 3rd grid structure on this substrate in this secondth district on this substrate in the 3rd district.
2. the manufacture method of semiconductor element as claimed in claim 1, the method wherein forming this inhibition zone comprises:
A patterning photoresist layer is formed, to expose this first insulating barrier in this secondth district on this substrate; And
Carry out a nitrogen and implant technique.
3. the manufacture method of semiconductor element as claimed in claim 2, wherein this nitrogen implants the implant dosage of technique is every square centimeter 10
13~ 10
15individual atom, implantation energy is 13 ~ 17KeV.
4. the manufacture method of semiconductor element as claimed in claim 2, wherein the thickness of this inhibition zone is 10 dust ~ 90 dusts.
5. the manufacture method of semiconductor element as claimed in claim 2, wherein in the step forming the 3rd insulating barrier, the nitrogen in this inhibition zone disengages from this substrate.
6. the manufacture method of semiconductor element as claimed in claim 1, the method wherein forming the 3rd insulating barrier comprises carries out thermal oxidation method.
7. the manufacture method of semiconductor element as claimed in claim 1, the method wherein forming this first insulating barrier comprises:
An insulation material layer is formed on this substrate; And
Remove this insulation material layer of part, to expose this substrate of part in the 3rd district, this insulation material layer remaining forms this first insulating barrier.
8. the manufacture method of semiconductor element as claimed in claim 1, the method wherein forming this second insulating barrier comprises carries out thermal oxidation method.
9. the manufacture method of semiconductor element as claimed in claim 1, wherein the thickness of the 3rd insulating barrier in this firstth district is less than the thickness of this second insulating barrier.
10. the manufacture method of semiconductor element as claimed in claim 1, wherein this firstth district is cell region, and this secondth district is low voltage component district, and the 3rd district is high voltage device district.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210282153.0A CN103578951B (en) | 2012-08-09 | 2012-08-09 | The manufacture method of semiconductor element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210282153.0A CN103578951B (en) | 2012-08-09 | 2012-08-09 | The manufacture method of semiconductor element |
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|---|---|
| CN103578951A CN103578951A (en) | 2014-02-12 |
| CN103578951B true CN103578951B (en) | 2016-04-06 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4859619A (en) * | 1988-07-15 | 1989-08-22 | Atmel Corporation | EPROM fabrication process forming tub regions for high voltage devices |
| US5502009A (en) * | 1995-02-16 | 1996-03-26 | United Microelectronics Corp. | Method for fabricating gate oxide layers of different thicknesses |
| CN1302088A (en) * | 1999-12-24 | 2001-07-04 | 三星电子株式会社 | Semiconductor device with multi-grid insulation layer and its producing method |
| TWI304251B (en) * | 2006-06-09 | 2008-12-11 | Powerchip Semiconductor Corp | Method of manufacturing split gate flash device |
-
2012
- 2012-08-09 CN CN201210282153.0A patent/CN103578951B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4859619A (en) * | 1988-07-15 | 1989-08-22 | Atmel Corporation | EPROM fabrication process forming tub regions for high voltage devices |
| US5502009A (en) * | 1995-02-16 | 1996-03-26 | United Microelectronics Corp. | Method for fabricating gate oxide layers of different thicknesses |
| CN1302088A (en) * | 1999-12-24 | 2001-07-04 | 三星电子株式会社 | Semiconductor device with multi-grid insulation layer and its producing method |
| TWI304251B (en) * | 2006-06-09 | 2008-12-11 | Powerchip Semiconductor Corp | Method of manufacturing split gate flash device |
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| CN103578951A (en) | 2014-02-12 |
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