CN103609079B - Perform IDE and the method for the straight-through forwarding of grouped data - Google Patents

Abstract

A kind of IDE (105) includes straight-through forwarding module (100).Described straight-through forwarding module (100) includes at least one receiver assembly (120), and described receiver assembly is arranged to receive data to be forwarded；And at least one emitter assemblies (130), described emitter is arranged to the data that transmission is stored at least one transmitter buffer (135).Described straight-through forwarding module (100) farther includes at least one delimiter assembly (150), described delimiter assembly is arranged to, the data element (Y) (414,424,434,444) of the first number of respective Frame (410,420,430,440) is once received by described at least one receiver assembly (120), then in the transmission of described transmitter buffer (135) internal trigger frame data, the data element (Y) of described first number includes that first predefines integer value.

Description

Perform IDE and the method for the straight-through forwarding of grouped data

Technical field

The field of the invention relates to the IDE of a kind of straight-through forwarding performing grouped data And method.

Background technology

In computer networking field, straight-through forwarding, the most straight-through exchange, is a kind of use In the exchange method of packet switching system, wherein the network switch receives whole at the network switch Transmitted frame (or packet) is started before individual frame.Destination address one is processed, and is the most generally carried out This forwarding operates.By this way, straight-through forwarding makes it possible to significantly reduce and passes through switch Delay.Use the key character of the straight-through definitiveness automated system forwarding and being direct packets. Additionally, the realization of this system is constantly expanded in industrial market, and this technology is the most day by day Penetrate into family, medical treatment and the solution of automobile application.

Straight-through repeater system usually requires that the delay of strict control switch is (such as, at switch The data received and this data are subsequently by the delay between switch transmission (forwarding)) and tremble Dynamic (such as, the variance of the time cycle between the transmission of successive frame) is to guarantee the row determined For and scalability.Generally, this delay/shake requires between different straight-through " patterns " (between the most different packet switching protocols) is different.Such as, this direct mode operation can Can include, such as Ethernet protocol, such as the Ethernet of EtherCAT(auto-control technology), ProfiNET, EtherNet/IP, power distribution station automatization (IEC62439), DLR(device level Ring network technologies) or the straight-through exchange of IP operation.To the control of delay and jitter for including ether The straight-through forward mode particular importance of net frame etc., wherein frame is spaced unpredictably and can Be the second interval or immediately, this is different from such as has the networking telephone that can predict frame period (VoIP).In order to make cut-through switch the most competitive, it allows for many Individual straight-through Switching Module is supported this deterministic behavior and scalability.

Conventionally, closely the controlling of delay and jitter is provided by hardware blocks, described specially It is arranged to meet specific delays and shake requirement with hardware block.Single equipment uses this Plant hardware blocks and result in relatively costly and inflexible solution.Particularly, in order to make Given switch disclosure satisfy that the requirement of more than one direct mode operation, and each straight-through forward mode is just Need single hardware blocks, thus significantly reduce the cost of switch, power consumption and right Real estate demand in switch.

Summary of the invention

As described in claims, the invention provides a kind of grouped data of performing The straight-through IDE forwarded and method.

The specific embodiment of the present invention is elucidated with in the dependent claims.

With reference to embodiments described hereinafter, these or the other side of the present invention will be apparent that And it is set forth.

Accompanying drawing explanation

Referring to the drawings, only by way of example, the further detail below of the present invention, aspect and Embodiment will be described.In the accompanying drawings, similar reference number is used to indicate identical or merit The element that energy is similar.Element in accompanying drawing is in order to simple and clear and be illustrated, and differs Fixed drawn to scale.

Fig. 1 shows the simplified block diagram of the example of straight-through forwarding module.

Fig. 2 shows the simplification example of the straight-through forwarding performing Frame.

Fig. 3 shows that the replacement of the straight-through forwarding performing Frame simplifies example.

Fig. 4 shows the example that straight-through retransmitting paramater configures.

Fig. 5 and Fig. 6 shows the letter of the straight-through retransmitting paramater configuration modification in packet switching network Change example.

Fig. 7 shows the simple flow figure of a kind of method of straight-through forwarding performing grouped data.

Detailed description of the invention

The example of the present invention described now with reference to the example of straight-through forwarding module, such as can be The straight-through forwarding module realized in packet switching system.But, the invention is not restricted to referring to the drawings Described specific straight-through forwarding module architecture, and substituted systems can be equally applicable to Structure.Such as, for illustrated example, straight-through forwarding module is illustrated as including RISC(essence Letter instruction set computer) complex, wherein this complex includes being arranged to straight-through forwarding mould Block provides multiple RISC processing modules of data processing function.But, the number of straight-through forwarding module Can be implemented with any suitable alternative equally according to processing function.Such as, data process merit Energy can be by single risc processor or by one or more CISC(sophisticated vocabulary meters Calculation machine) processing module, one or more digital signal processor (DSP) etc. provide.Additionally, By the example realized with reference to some delimiters to describe the example of the present invention.But, the present invention is also It is not limited to the specific delimiter architecture being described with reference to the accompanying, and can be equally applicable to Substituted systems structure.Additionally, due to the example embodiment of present invention explanation may major part be to make It is implemented with the electronic building brick known to those skilled in the art and circuit, so details is not Can explain in any degree bigger than the above-mentioned illustrated degree felt the need to.Right The understanding of basic conception of the present invention and understanding are to be taught interior to not obscure or deviateing the present invention Hold.

The simplified block diagram of the example of straight-through forwarding module 100 is illustrated referring now to Fig. 1, Fig. 1, Such as can be implemented in packet switching system (not shown).In illustrated example, Straight-through forwarding module 100 is implemented in IDE 105.Straight-through forwarding module 100 It is arranged to divide via the usual data that receive in the 110 one or more input channels illustrated Group or " frame ", and by generally road in the 115 one or more output channels being illustrated By/forward the Frame received.

The straight-through of the straight-through forwarding module 100 in the such as Fig. 1 in packet switching system is used to turn Send out exchange to make it possible to reduce the delay in packet switching system (such as, in source electrode device transmission Data and target device receive the time between these data).Straight-through forwarding, the most straight-through Exchange, is a kind of exchange method for packet switching system, and wherein the network switch is (such as Straight-through forwarding module 100 in Fig. 1) before having been received by whole frame, start forwarding data frame (or packet)；It is generally but not unique, processed in the near future in destination address.With this The mode of kind, straight-through forwarding typically allows for significantly reducing the delay by each switch.Example As the delay of the straight-through forwarding switch of the straight-through forwarding module 100 of Fig. 1 is generally defined as straight Logical forwarding module 100 receives data and straight-through forwarding module 100 transmits (i.e. forwarding) subsequently and is somebody's turn to do Time between data.Therefore, by waiting until until receiving starting transmitting data frame Whole frame, can reduce the transmission delay of switch.Owing to the transmission of Frame is having been received by Begin to before complete Frame, hand over so Frame can spread all over packet during the transmission Change intrasystem multiple switch.For example, it is contemplated that the frame of 1000 byte longs, and include such as The exchange system of the straight-through forwarding switch of the straight-through forwarding module 100 in Fig. 1, wherein this is System starts after being included in 16 bytes that have received such as this frame to transmit (transmitting again)/forwarding data Frame.During end-to-end packet routing operations, this frame (in theory) can be with transfer more than 60 Straight-through forwarding switch.Therefore, receive with each switching equipment before forwarding this whole frame The system of whole frame compares, and straight-through forwarding makes it possible to be substantially reduced the delay through system.

The illustrated straight-through forwarding module 100 in example includes one or more receiver assembly 120 and one or more emitter assemblies 130.Each receiver assembly 120 includes receiving (Rx) FIFO(FIFO) buffer 125, the data wherein received are stored in this buffer. When ' B ' byte data block is received by receiver assembly 120 when, receiver assembly 120 quilt It is arranged to request is generated for data to be processed block, or certain other instruction is provided.Institute Diagram example in, for its generate this request or other indicate data block then by One or more risc processors 145 in the RISC complex 140 of straight-through forwarding module 100 Process.Each emitter assemblies 130 includes launching (Tx) fifo buffer 135, a denier Be processed according to block, then they can be transferred to this buffer.The most once for this data block It is provided with the mark indicating this data block to get out transmission, or otherwise triggers transmission, then May then pass through the output channel 115 of correspondence to transmit (that is, forward/route) Tx FIFO and delay Rush the data block in device 135.

Straight-through forwarding module 100 farther includes generally at the 150 delimiter assemblies being illustrated. Delimiter 150 is arranged to: receive a Y word upon respective receiver assembly 120 The respective Frame of joint, then at the transmission of Tx fifo buffer 135 internal trigger Frame, Y Including predefined integer value.

By this way, by the transmission of trigger frame data after receiving Y byte frame data, Can realize the Frame by straight-through forwarding module 100 beginning substantially definitely and determine The delay of property.This delay is substantially dependent only on the number in the Y byte triggered after transmission The data rate of mesh and each afferent pathway 110.As a result, the consistent sum being substantially the same Deterministic delay can be that the beginning of all Frames in data stream completes, wherein this number It is forwarded by straight-through forwarding module 100 according to stream.By this way, straight-through forwarding module 100 Substantially zero shake can be introduced to data stream.Regardless of frame sign, between frame rate or successive frame Time how to change, delay and jitter will be consistent.In some instances, owing to triggering The operation that the transmission of the beginning of Frame is not dependent on such as processing in territory is (such as, illustrated Example in the case of, the operation performed in being not dependent on RISC complex 140), so real The delay variation of the beginning of frame is minimized in matter.For clarity, a byte generally includes 8 The data of individual bit.But, it is contemplated that, for the purposes of the present invention, art used herein Language " byte " is equally applicable to the bit of any definition number, such as 4,16 etc..

For some examples, delimiter 150 can use the inside such as represented 155 to connect Bus is carried out with the speed line higher than the data rate of input/output passage 110,115, described Bus is coupled in Rx fifo buffer 125 He in identical module or on one module Respective Rx/Tx fifo buffer between Tx fifo buffer 135 in other module any 125, between 135.Alternatively, for some other examples, delimiter 150 can be included in Each the shift register between Rx/Tx fifo buffer 125,135 (the most also can be 155 Represent), when wherein shift register have shared identical with input/output passage 110,115 Clock.Alternatively, for some other examples, delimiter 150 can include passing through simple logic Door and the enumerator being activated afterwards on some clocks edge from frame reception beginning are implemented Enable bit.This example supposition last processes territory 140 and is arranged to, and fast enough, Once enable bit to be set after enumerator expires, then by first piece or ' X' byte moves to Tx FIFO125；The part of functions of delimiter 150 is implemented, such as at this in processing territory 140 In 155 expressions in individual example.

Alternatively, in other example, delimiter can be by other suitable scheme any by reality Existing, wherein said scheme completes " X " data byte in a kind of deterministic mode from Rx Fifo buffer 125 moves to Tx fifo buffer 135.

Delimiter assembly 150 can be further arranged at least one transmitter buffer (135) before the transmission of internal trigger frame data, by Frame start receive (that is, connect Receive an X byte data frames) X byte data is transferred to from respective Rx fifo buffer 125 Each Tx fifo buffer 135, wherein X includes predefined integer value.Such as, once exist Frame initially receive a described X byte, then delimiter assembly 150 can be arranged Become the X byte transmission initially received at Frame to respective Tx fifo buffer 135, Wherein X includes the predefined integer value less than or equal to Y.By this way, by receiving After Y byte frame data, before trigger frame data are transmitted, automatically transmit an X byte, can With guarantee at least these X byte data frames are present in Tx fifo buffer 135 with In transmission.

For the sake of completeness, the illustrating of straight-through forwarding module 100 of Fig. 1 is the use of one The example implementation of the straight-through forwarding module 100 of individual or multi-microprocessor or microcontroller abstract Figure.Each assembly of straight-through forwarding module 100 is such as the most operable by data/address bus 170 Coupling.It can be maybe outside that data/address bus 170 can be implemented by the internal bus in equipment 's.For illustrated example, RISC complex 140 is this situation, i.e. microprocessor bag Containing being arranged to process the integrated exclusive data plane treatment solution of straight-through block.This makes micro- The CPU160 of processor runs application software and manages datum plane hardware, such as start and Stop passage or dynamically the route of cut-through switch changed to another from Rx assembly 120 TX assembly 130.Additionally, shown in Fig. 1 also have CPU164, its potentially included via Bus 170 is in the one or more general core being interiorly or exteriorly attached.CPU164 is permissible It is arranged to such as perform straight-through block and the process of application software.

Fig. 2 illustrates the simplification example processing the Frame forwarded by straight-through forwarding module 100. Frame is received by receiver assembly 120 via input channel 110 with the form of data stream.With Data to be received, it is stored in respective Rx fifo buffer 125 by receiver assembly 120 In.In illustrated example, receiver assembly 120 is arranged to divide the data received It is slit into 8 block of bytes.Whenever receiving 8 block of bytes, receiver assembly 120 is such as by raw Request is become to send the signal that data block is processed.The data block that receives follow-up In process territory, (that is, in example illustration example in RISC complex 140) is processed (borrows Helping is the Rx buffer 125 of fifo buffer).Once be processed, then data block is passed It is passed to the Tx fifo buffer 135 of respective emitter assemblies 130.Each emitter assemblies 130 It is arranged to transmit (by being the Tx buffer 135 of fifo buffer) in order stored Data block in the respective Tx fifo buffer 135 having triggered transmission (such as, by Transmission mark etc. is set).

In example illustrated in fig. 2, delimiter assembly 150 is arranged to, such as, once In the one 8 byte that initially receives of Frame, then will start to receive at each Frame (that is, receive the one 8 byte data frames) 8(X=8) byte is from respective Rx fifo buffer 125 are transferred to respective Tx fifo buffer 135.Accordingly, because X(is by delimiter assembly 150 Automatically the byte number of Tx fifo buffer 135 it is transferred to from Rx fifo buffer 125) and B (byte number in block) is configured to equal, is 8 bytes the most in this illustration, so The first complete data block is transferred to Tx fifo buffer 135 by delimiter assembly 150 automatically, As illustrated by 210.At the time that the example for Fig. 2 is essentially identical, receive Device assembly 120 generates request for the first data block 210 to be processed, or provides certain Other instruction.In response to described request, in processing territory 140, process the first data block 210.

Once receiver assembly 120 generates such request, then process territory 140 in normal condition Under can be arranged to transmission of data blocks to Tx FIFO135.But, the pair of the first data block This (or at least part copy) is present in Tx FIFO135.Therefore, some are shown Example, delimiter 150 can include controlling labelling (not shown) or switch, described control labelling Or switch is arranged to the feature of " unlatching " or " closedown " straight-through forwarding module 100, such as With the feature of first piece of " on "/"off" transition observation (process) Frame.Such as, For the purpose classified, process territory 140 and may want to observe first piece of Frame.Mostly Under number direct mode operation, the content of first piece of Frame need not be changed.As example, allow It is contemplated that direct mode operation needs to filter Ethernet destination-address (the one 6 word of Rx packet Joint).In this illustration, when receive contain need classify (such as, IP/UDP+Ethernet The classification of DA) other block of more data when, can be stored this for place later Reason, or after receiving the first data block, but coming of the second data block can received Perform filtration.When receiving the first data block when, upon receipt of for the first data block Request, then process territory 140 can process first piece, maybe when receiving the second data block Waiting, upon receipt of the request for the second data block, then processing territory 140 can be together with second Data block processes the first data block together；In this illustration, will be after ' Y ' byte.

Alternative exemplary realizes to be realized by delimiter 150, wherein this delimiter 150 quilt Be arranged to the first of Frame ' X' byte moves to Tx fifo buffer 135, and work as X=B When, it also is moved into processing territory 140.And another example implementation or pattern can include delimiting Symbol 150, this delimiter 150 is arranged to move to Tx FIFO buffering by the first of Frame piece Device 135, but process territory 140 and be unaware that this moves.Processing territory 140 then can be from the Two data blocks (first piece comprises insignificant data) start, and process each the most in an orderly manner Subsequent block.

In some instances, once receiver assembly 120 receives the one 16 byte of Frame (Y=16), then delimiter assembly 150 is further arranged at Tx fifo buffer 135 The transmission of internal trigger frame data (that is, first piece of Frame 210).Therefore, for Fig. 2 Example illustrated in, owing to Y is configured to the size equal to two data blocks, so delimiting Symbol assembly 150 is arranged to, upon receipt of the second complete data block, then trigger data block The transmission of 210.The request generated accordingly, in response to receiver assembly 120, to the second data The process of block substantially occurs with the transmission triggering the first data block simultaneously.Once the second data block Processed territory 140 processes, then it is transferred to Tx fifo buffer 135 and its transmission quilt Trigger.Subsequently, the data block received is processed in the way of identical with second piece, wherein rings The Ying Yu request that such as receiver assembly 120 is generated and connect processing in territory 140 to process subsequently The data block received, and it is subsequently transferred to Tx fifo buffer 135 for transmission.

Assume that the data rate of input channel 110 is substantially equal to the data speed of output channel 115 Rate, in order to avoid getting out in Rx fifo buffer 125 data block excessive that process Run (over-run) and the not enough fortune to the data block being supplied to Tx fifo buffer 135 Row (under-run), and thus potentially result in respective Frame and be aborted, each data The process time of block is necessarily less than the time used by (or being at most equal to) reception/transmission data block.

By the transmission of trigger frame data after receiving Y byte frame data, it is possible to achieve pass through The most absolute and the deterministic delay of the beginning of the Frame of straight-through forwarding module 100；This Kind postpone substantially to be dependent only on the number of Y byte after triggering transmission and the most defeated Enter the data rate of passage 110.As a result, for the number forwarded by straight-through forwarding module 100 Beginning according to all Frames in stream, it is possible to achieve the consistent and definitiveness being substantially the same Delay.By this way, essence can be introduced to data stream by straight-through forwarding module 100 Upper zero shake.Particularly, if delimiter assembly 150 and receptor and emitter assemblies 120, The clock signal (not shown) that 130 each use are identical, then can realize zero shake.Even if Delimiter assembly 150 and receptor use different clock letters with emitter assemblies 120,130 Number, if described clock signal includes identical frequency, then shake also can be limited at single Clock cycle.

By the Frame received being divided into the B word being treated separately and be transmitted subsequently Locking nub, when can easily be exported the process to the data block by straight-through forwarding module 100 Between and postpone；

Wherein: delay=Y(is defined frame delay by the Y parameter of delimiter).Any in frame The maximum process time of data block depends on that size B of block, process complexity (such as, depend on Direct mode operation) and disposal ability (such as, RISC operation frequency etc.).Additionally, pass through Changing size B and/or the disposal ability of block, it appeared that configure below, this configuration can be simultaneously Meet specific direct mode operation processes the delay required with system and/or shake requirement.Merit attention , the only first data block has the dependency about delay and jitter, all follow-up datas Block must be processed in the budgetary of configuration；It is X or B byte * line speed in this example.With This mode, the configuration of block size B and delimiter parameter X and Y allows as application-specific or association View or particular procedure territory realize and control deterministically postpones, shakes and program requirement.

Fig. 3 illustrates the replacement of the process of straight-through forwarding module 100 forwarding data frame and simplifies example. In the example depicted in fig. 3, receiver assembly 120 is arranged to divide the Frame received It is slit into 16 block of bytes.And, delimiter 150 is arranged to: such as opening upon receipt of frame The one 16 byte begun, then by (that is, the reception first initially received at each Frame 16 byte data frames) 16(X=16) byte is transferred to respectively from respective Rx fifo buffer 125 From Tx fifo buffer 135.Accordingly, because X(is automatic from Rx FIFO by delimiter assembly 150 Buffer 125 is transferred to the byte number of Tx fifo buffer 135) and B(byte in block Number) it is configured to equal, it is 16 bytes the most in this illustration, so the first complete data Block is transferred to Tx fifo buffer 135 by delimiter assembly 150 automatically, as being schemed 210 Show.At the time that the example for Fig. 3 is essentially identical, depend on (unshowned Being configured in mode register) delimiter pattern, receiver assembly 120 can be for wanting The first processed data block 210 generates request, or provides certain other instruction.In response to Described request, can process the first data block 210 in processing territory 140.

In some instances, delimiter assembly 150 is further arranged to: once receptor group Part 120 receives the one 24 byte (Y=24) Frame, then at Tx fifo buffer 135 The transmission of internal trigger frame data (that is, first piece of Frame 210).Therefore, for Fig. 2 Shown in example, owing to Y is configured to the size equal to a half block, thus delimit Symbol assembly 150 is arranged to substantially trigger first piece 210 in the midway receiving the second data block Transmission.Assume the data speed that input channel 110 and output channel 115 include being substantially equal Rate, in the time that the second complete data block is received by receiver assembly 120, emitter assemblies 130 by the first data block of transmission half.Therefore, in order to avoid to being ready to delay at Rx FIFO Excessively running and to being supplied to Tx fifo buffer 135 of the data block processed in rushing device 125 The not enough operation of data block, and thus potentially result in respective Frame and be aborted, receive Complete second piece and processed be ready to Tx fifo buffer 135 in transmit second piece it Between maximum time be necessarily less than the half of time used by the first data block of transmission.Time identical Between limit all subsequent block of being used in Frame.

The transmission of trigger data frame by this way is made it possible to by delimiter assembly 150, can To be substantially reduced the delay by straight-through forwarding module 100 forwarding data frame.

Include header at the frame received, be greater than the IP(Internet Protocol of Y byte) header In the case of, it is assumed that the header of the Frame received is explained, but does not change.For Fig. 3 Shown in example, if header is more than such as 24 bytes (Y), then the block of 16 bytes is big Little and in delimiter 150 " transmission after 24 bytes " configuration combination would not allow for changing header Interior any field, if this is owing to any field in header is changed, then by needs weight New calculate new header check and.But, due to until next data block just receives header Remainder, therefore can not wait the remainder of header, this is because in this situation Lower will cause not enough operation.

For shown example, it is desirable to if X is less than or at most equal to Y(B is less than X, X Only can be equal to Y, otherwise X is necessarily less than Y) to guarantee when delimiter assembly 150 touches The when of sending out the transmission of the first data block, data are available in Tx fifo buffer 135. And, for shown example, it is desirable to Y is more than (or at least equal to) block size B, in order to Guarantee that the transmission of the first data block was not fully complete before receiving whole second piece.

For some example embodiments of the present invention, block size B can be configured to be equal to, than As, B=X=Y/2；

Wherein: Y is configured to realize by the expected delay of straight-through forwarding module 100, and X and B is configured to values below, and this value has adapted to a certain degree performance (such as, RISC frequency Rate) in the case of to the process requirement processing the direct mode operation disposed on complex.Particularly, This example can be implemented, wherein when receiving the second data block of frame the most completely and/or working as Rx Fifo buffer 125 sends, to processing territory 140, signal that the second data block is ready to be processed Time, trigger first piece or the transmission of X byte data.

However, it is possible to any suitable configurations of implementation value B, X and Y.Such as, Fig. 4 diagram Some other examples of possible parameter configuration, and they phases with the Frame received Should be related to.For each example shown in Fig. 4, X is configured to include the value of 14 bytes, And Y is configured to include the value of 42 bytes.Generally the first example in 410 instructions includes The block size B of 14 bytes；Generally the second example in 420 instructions includes the block size of 16 bytes B；Generally the 3rd example in 430 instructions includes the block size B of 21 bytes；And generally exist 4th example of 440 instructions includes the block size B of 42 bytes.These examples each in, By parameter Y is set to 42 bytes, the delay of 42 bytes is defined for triggering by directly The transmission of logical forwarding module 100.The block size B of change defines by receiver assembly 120 More conventional data postpone and lead directly to the direct mode operation processed in territory 140 of forwarding module 100 Process requirement.Equally, after the transmission of frame data is triggered, block size B and byte Y Relationship affect between number needs to be stored in Tx fifo buffer 135 etc. waiting for transmission The quantity of data, and therefore have impact on the memory requirement of straight-through forwarding module 100 (such as, The size of Tx fifo buffer 135).It should be noted that when buffering one compared to needs Or the storage of multiple full frame is when forwarding architecture, need less FIFO memory.

Therefore, parameter Y effectively defines the delay that the packet in straight-through module 100 forwards, This delay deducts in input logical equal to the delivery time of the first bit of frame in output channel 115 The reception time of the first bit of frame on road 110；Parameter Y also defines delimiter 150 and is touching Send out the number of the bits/bytes waited before the transmission of 115 from Tx FIFO130 to physical interface. Parameter X defines the number that delimiter moves to the bits/bytes of Tx FIFO130, parameter X The most directly define or have impact on and process the time quantum in territory 140 to run into lower operation or excessive Second piece of the pre-treatment frame of operation.Parameter B defines the number of the bits/bytes in data block, Thus define the frequency of the request for processing territory 140；In some cases, this is also place Reason territory processes the process budget of any single block in frame.

For some examples, the interaction between parameter X, Y and B, and they and place The relation of the available processes time of each data block in reason territory 140 can be described hereinafter.? In first example, make:

B=block size；And Y=2 × B

If X is configured to less than block size B, then during the available processes of the first data block of frame Between equal in input channel 115 the reception time of B byte data.The second data for frame Block, if the processed territory 140 of the remainder of the first data block (B-X byte) is transferred to Tx Fifo buffer 135, then the available processes time is also by the reception time equal to B byte.So And, if the remainder of the first data block (B-X byte) is not by delimiter assembly 150 Be transferred to Tx fifo buffer 135, then the second data block of frame is (untreated plus the first frame B-X byte) the available processes time by equal to X byte the reception time (that is, due to X close In the configuration of B, the second data block of frame can have the less available processes time).For 3rd and each subsequent data blocks of frame, the available processes time is by the reception equal to B byte data Time.

On the contrary, if X is configured to more than or equal to block size B, wherein delimiter assembly 150 It is arranged to transmit the first complete data block plus except the byte number of B is with equal to X(X-B), So for the first data block, essentially without the available processes time.Otherwise, the first number of frame According to available processes time of block by the reception time equal to B byte data.The second He for frame Each subsequent data blocks, the available processes time is by the reception time equal to B byte data.

In second example, make:

B=block size；And Y < 2 × B

In this illustration, if X is configured to less than block size B, then the first data of frame The available processes time of block is by the reception time equal to B byte data.The second data for frame Block, the available processes time will be equal to Y+X-2B.Here, we normally open after Y byte Originate and send X byte.If remaining B-X byte is not put into FIFO by the request of first piece, So have less time before the not enough operation on TX.Some X bytes are at second piece Sent before being fully received, be that further reduces second piece of place before deficiency is run The reason time.Such as, if it is assumed that B=8, X=7 and Y=14, then, when Tx is triggered The when of (after Y byte), in Tx FIFO, we have 7 bytes, and present Y is 14, We start to send X byte 2 byte, so working as at second piece to processing before territory sends request The when that the startup of process territory resting on only 5 byte in Tx FIFO, i.e. mean 5 words Joint deficiency is run；Therefore Y+X-2B=14+7-16=5.Now, for this situation, the second number Have to the remainder of first piece and all second piece are put into Tx FIFO according to block handling routine； It is 9 bytes (2B-X) in this case.Due to when Tx FIFO only has 5 byte Wait second piece of request to occur, and owing to processing territory the request of the 3rd piece occurs when by 9 Byte puts into Tx FIFO, so Tx FIFO has 9+5-B byte, and i.e. 6 bytes (Y-B). Therefore, for the 3rd and each subsequent data blocks of frame, the available processes time will be equal to Y-B.

On the contrary, if X is configured to equal to block size B, wherein delimiter assembly 150 is by cloth It is set to the first complete transmission of data blocks to Tx fifo buffer 135, then for the first number According to block, the time that substantially will not process can be used.Otherwise, the first data block of frame can use The reason time is by the reception time equal to B byte data.Second and each follow-up data for frame Block, the available processes time will be equal to Y-B.

On the contrary, if X is configured to more than block size B, wherein delimiter assembly 150 is by cloth It is set to the first complete transmission of data blocks to Tx fifo buffer 135, then for the first number According to block, the time that substantially will not process can be used.Otherwise, the first data block of frame can use The reason time is by the reception time equal to B byte data.For second and data block of frame, available The process time is by the reception time equal to B byte data.The 3rd and each follow-up number for frame According to block, the available processes time will be equal to Y-B.

In the 3rd example, make:

B=block size；And Y=B

When having been received by complete first piece when, it is transferred to Tx by delimiter assembly 150 The transmission of the oneth X byte of fifo buffer 135 starts.So post-processing domain 140 has transmission Time needed for X byte data is to put into Tx fifo buffer by remaining byte (Y-X) 135 and process the first data block.Upon receipt of the second complete data block of frame, then due to Overlap is not had to process, so not enough operation will be had.In order to overcome this point, delimiter group Part 150 may be configured to only process the first data block.By this way, delimiter assembly All subsequent block can be forwarded to Tx fifo buffer by 150, thus avoid the need for processing territory 140 perform such transmission, and this may need only to little delay, and i.e. seldom bit, keeps away Exempt from not enough operation.In such example, delimiter assembly is used in the application of straight-through forwarding Required critical data opening and closing process window.Owing to the most single piece of needs are processed, So this also allows for the desired properties reduced for processing territory.

In some instances, value B, X and Y can be configurable parameters.By this way, Straight-through forwarding module 100 may be configured to meet different delay and jitter requirements, and because of This may can support that more than one leads directly to forward mode.Such as, by modified block size B, can Receive the time used by complete block with amendment and process the time needed for this block.Therefore, may be used To control the data processing territory 140 by receiver assembly 120 and straight-through forwarding module 100 The process budget of block, in order to meet direct mode operation, the delay and jitter of system and process territory 140 The requirement of processing speed.On the contrary, by revising the number of byte Y, delimited receiving After the transmission of the frame data that symbol assembly 150 triggers, can dynamically control by straight-through forwarding The delay of the Frame of module 100.

Particularly, in some instances, parameter X and Y can be that software is configurable (such as, By can configure at one or more CPU160, the software that runs on 164), and therefore can Enough it is configured to " immediately ", such as, considers network topology change etc..Such as, Fig. 5 diagram The example that particularly this " immediately " of parameter Y configures, it directly affects by straight-through The delay of the Frame of forwarding module 100.

Specifically, Fig. 5 illustrates the example of the packet switching network including the first topology 510 Simplified block diagram.In this first topology 510, packet switching network includes data path, Described data path includes the first and second networks being arranged to receive and forward the packet of data Element 512,514.Such network element can be by straight-through forwarding module, such as Fig. 1 Straight-through forwarding module 100 is implemented.For shown example, packet switching network wraps further Including destination's element 518, wherein packet is forwarded to this destination's element 518.For this The individual example simplifying diagram, packet is from the first network element 512 of the delay including 8 bytes By including that the second network element 514 of the delay of 16 bytes is forwarded to destination's element 518. Therefore, for this first topology 510, the data path of packet switching network includes altogether 24 The delay of byte (8+16).

Fig. 5 further illustrates packet switching network due to the new network element " C " of introducing Simplified block diagram after causing network topology to change.This second network topology structure exists 520 are illustrated, and new network element is instructed to 526.Owing to introducing this new network element 526, so packet is passed through from the first network element 512 of the delay including 8 bytes now Including second network element 514 of delay of 16 bytes with include the further of another 8 byte The new network element 526 postponed is forwarded to destination's element 518.Therefore, for this Two topologys 520, the data path of packet switching network includes 32 bytes (8+16+8) altogether Postpone.For application in real time, this change through the total delay of data path may impact system The operation of system, wherein data path operates within the system.Conventionally, open up to adapt to network The such change flutterred, and not to being used as any change etc. in the remainder of system, Be necessary generally by amendment by individually lead directly to forwarding module for realize network element 512,514, The block size B that 526 are used is to revise the various network elements 512,514,526 of data path Interior delay.But, change the block size B used by straight-through forwarding module and require wherein It is modified for properly processing the data block of new spec in processing territory.This change generally needs Forwarding module to be led directly to " off-line " and reconfiguring；Thus carrying out this change when Network is caused infringement.

But, in some examples of the present invention, parameter X of straight-through forwarding module 100 and Y Can be that software is configurable (such as, by one or more CPU160,162,164 The software run can configure), and therefore, it is possible to it is configured to " immediately ".Therefore.For Example shown in Fig. 5, by reconfiguring one or more network element of such as data path Value Y of part 512,514,526, the delay of the network element by reconfiguring can be repaiied Change any change compensating in network topology.By example, and as shown in 530, Second network element 514 can be by straight-through forwarding module, the straight-through forwarding module of such as Fig. 1 100 are implemented, and can be arranged to the respective Frame upon receipt of Y byte, then The transmission of trigger frame data.Therefore, in the first topology 510, parameter Y of network element 514 The value of 16 bytes can be configured to, in order to offer is by 16 bytes of network element 514 Postpone.After introducing new network element 526, by parameter Y by network element 514 It is reconfigured for the value of 8 bytes, is reduced to 8 bytes by the delay of network element, thus Maintain the total delay in 24 byte data paths, as shown in 530.Advantageously, because This of parameter Y reconfigures without changing the block size B(leading directly to forwarding module 100 such as, B=4), so without carrying out any amendment in managing territory 140 at which.Therefore, to parameter Y So amendment and therefore can " immediately " to the amendment of the delay of straight-through forwarding module 100 Carry out, and without straight-through forwarding module 100 " off-line ".

Fig. 6 illustrates the alternative exemplary that this " immediately " configures.Specifically, Fig. 6 illustrates The simplified block diagram of the example of the packet switching network in the first configuration 610.Packet switching network Including the first data path, this first data path stems from network branches 605, includes network element Part 612 and 614 and terminate at destination's element 618.Packet switching network includes the second data Path, this second data path is also derived from network branches 605, includes network element 615 and 616 and also terminate in destination's element 618.This first configuration at packet switching network In 610, the first and second network elements 612 and 614 of the first data path include respectively 8 Byte, the delay of 16 bytes.Equally, the first data path includes the delay of 24 bytes altogether. On the contrary, the network element 616 in the second data path includes the delay of 8 bytes.Equally, Two data paths include the delay of 8 bytes altogether.

Including two data between different network branches 605 and the destination's elements 618 postponed The existence in path may cause packet to be route via different data paths, and does not presses Arrive at element 618 order.As a result, destination's element 618 needs to include more complicated Software is so as to identify the packet that receives the most in order, and hereafter to the data received Packet rearrangement.But, by revising one or more network elements 612,614,616 Delay so that two data paths include identical total delay, and packet is by with correct Order arrives at element 618, route regardless of via which in two data paths Packet.

Therefore, and as shown in 620, realized the second data road by straight-through forwarding module The network element 616 in footpath, and in the example shown, by Y is configured to equal to 24 words Joint (that is, the total delay of the first data path), network element 616 and therefore the second data The delay in path can be configured to the delay equal to the first data path, and wherein said leading directly to turns The straight-through forwarding module 100 sending out module, such as Fig. 1 is arranged to upon receipt of Y byte Each Frame, then transmission of trigger frame data.And, and as explained above, so Configuration variation without in network element 616 use block size B modify, and Therefore need not revise it and process territory.

For some example alternative embodiment, network branches 605 can be arranged to realize first And the redundancy that second between data path.Such as, including the first of network element 612 and 614 Data path or include that the second data path of network element 616 can be arranged to turn energetically Send out frame, and other data path is in inert condition.If data path can not forward energetically Frame or the most damaged, then network branches 605 may be transformed at another significant figure According to transmitted frame on path.By the delay of two data paths being configured to roughly equal, as above Described, no matter via which data path transmitted frame, receive network element 618 all by big for observation Cause equal frame and receive the time, and therefore do not have after the conversion of the data path of converted frames Its process territory 140 of necessary amendment.

Alternatively, and according to further example, network branches 605 can be arranged to multiple The packet of data processed, and substantially simultaneously forward them via two data paths.By inciting somebody to action The delay of two data paths is configured to roughly equal, as it has been described above, receive network element 618 The packet replicated will be received via each data path in the roughly the same time.Equally, net is received Network element 618 can select abandon a packet or keep two copies of this packet.If one Individual data path breaks down, owing to the delay of each data path is the most substantially matching, so not Pipe, via which data path transmitted frame, receives network element 618 all by roughly equal for observation Frame receives the time, and therefore need not revise its process territory 140.

In some instances, network element 612,614,616 and 618 can be shared identical Clock (not shown).In this manner it is achieved that via different data path transmission numbers Appended synchronization according to packet.

Therefore, it has been described that the example of straight-through forwarding module 100, described straight-through forwarding module energy Deterministic forward delay is enough provided, allows Frame immediately to be processed in software simultaneously, its Described in postpone to be low jitter in straight-through forwarding scheme and be probably zero shake.Particularly, Having been described in the example of the present invention, wherein delimiter assembly 150 is arranged to automatically will receive X byte data frames be transferred to respective Tx fifo buffer 135, and receiving Y word The transmission of thus trigger frame data after joint Frame；X, Y are configurable parameters.This makes it possible to Enough delay and jitters that deterministically controls, allow the program via the multiple application of software support simultaneously In multiple agreements.Additionally, by being divided into Rx FIFO to delay the Frame received in real time The B byte rushed in device 125 can configure block, for application-specific, agreement, disposal ability etc. , it is possible to easily derive and postpone and process requirement.

Particularly, for some example embodiment in the present invention, receptor and emitter assemblies 120,130 and delimiter assembly 150 can be implemented the most within hardware with utilize therefore Attainable improvement performance, and therefore promote realize multiple straight-through forward mode delay and/or Shake requirement.On the contrary, it is contemplated that, for some example embodiments of the present invention, process territory 140 Can be implemented the most in software to utilize the most attainable motility, and therefore Make it possible to support multiple straight-through forward mode.

Although " byte " transmission according to data describes example, but other example can also It is applied to the transmission of the data element of any form or number, including bit, byte, frame etc. Deng.

Prolong except achieving the deterministic forwarding being probably zero shake in straight-through forwarding scheme Late, the example embodiment of the present invention can be furthermore enable to reduce application MIPS(per second Million instructions) requirement, due to straight-through module 100 the most general and can support wide General agreement, so this just can be achieved.It is additionally, since shake and postpones to be delimited Symbol 150 control, so ensureing delay and jitter target without dedicated high priority software module, This can significantly simplify application software.Compared on same IDE or multiple collection Becoming and require multiple hardware block on circuit arrangement, it can also reduce the size of software and simplify multiple Polygamy, this is owing to single IDE hardware block realizes supporting multiple patterns.

Additionally, for some examples, due to along with during forwarding operation, only little relative to one The frame of part is stored in any point, it is possible to reduce the size of Rx/Tx fifo buffer, because of This memorizer for buffering that can realize reducing quantity.Especially, forward compared to storage, Which also saves many memorizeies, such as, based on being assigned to store the packet for process DDR, FIFO or DPRAM, this is optional for some examples of the present invention.

Additionally, for some examples, it may be required reduce hardware (the RTL-resistance crystal of quantity Pipe logic) to realize the support of multiple agreement, this is owing in some instances, only delimiting Symbol and FIFO segmenting system need to be designed within hardware.And, for some examples, the most directly The unique hardware block of logical pattern there is no need to realize in software as each pattern.

Additionally, for some examples, due to the less hardware of test, less chip size, Lower power, easier encapsulation etc., it is possible to realize die size, the test reduced Vector, testing time, and therefore support that the integrated circuit of multiple straight-through forward mode/agreement sets Standby manufacturing cost.

The most by way of example, straight-through turn realized according to some example embodiments of the present invention Some examples sending out the straight-through forward mode that module can be supported include Ethernet protocol, such as The Ethernet of EtherCAT(auto-control technology), ProfiNET, EtherNet/IP, DLR (device level Ring network technologies) or the straight-through exchange of IP operation.

Illustrating referring now to Fig. 7, Fig. 7 such as can be at the straight-through forwarding module 100 of Fig. 1 Interior realization, the simple flow figure of the example of a kind of method of straight-through forwarding performing grouped data 700.Described method starts from 710, wherein receives what device assembly 120 the most to be received forwarded The beginning of Frame.The frame data received are such as divided in Rx fifo buffer 125 Become B byte block, and upon receipt of each data block, then trigger the place to this block 720 Reason.For example, it is possible to be supplied to process the request in territory 140 by generation to come the place of trigger data block Reason.Then, in processing territory 140, such as process the block after data block, and process in order It is transferred to the transmitter buffer of Tx fifo buffer 135 of such as Fig. 1 for transmission.

For shown example, after 710 beginnings receiving Frame to be forwarded, The method of Fig. 7 farther includes, upon receipt of the frame data of X byte, then by those X words The frame data of joint are such as transferred to Tx fifo buffer from the Rx fifo buffer 125 of Fig. 1 135.Subsequently, upon receipt of the frame data of Y byte, the most described method farther includes to trigger The first data block from Tx fifo buffer 135 transmission frame.Then 740, transmit in order Data block in Tx fifo buffer 135.Described method ends at 770, such as, and Qi Zhongchuan The final data block of the defeated Frame received.

The present invention's at least partially can be in the computer journey for running on the computer systems Sequence is implemented, at least includes for working as in such as computer system or making programmable device When running on the programmable device of the function being able to carry out the equipment according to the present invention or system, Perform the code section of steps of a method in accordance with the invention.

Computer program is a series of instructions, such as application-specific and/or operating system.Computer Program can such as include following in one or more: routine, function, program, object side Method, object implementatio8, executable application, small routine, servlet, source code, object Code, shared library/dynamic loading storehouse and/or be designed for other of execution on the computer systems Job sequence.

Computer program internally can be stored or via meter on computer-readable recording medium The readable some transmission medium of calculation machine is to computer system.All or some computer programs are permissible Permanently, removably provided at computer-readable medium or be remotely coupled to information processing System.Computer-readable medium can include, below any number of: bag Include the magnetic storage medium of Disk and tape storage medium；Optical storage medium, such as CD media (such as, CD-ROM, CD-R etc.) and digital video disk storage medium；Non-volatile deposit Memory storage media, including based on semiconductor memory cell, such as FLASH memory, EEPROM、EPROM、ROM；Ferromagnetic digital memories；MRAM；Volatile storage is situated between Matter, including depositor, buffer or caching, main storage, etc.；And Digital Transmission is situated between Matter, including computer network, point-to-point communication equipment and carrier wave transmission media, only lifts several Example.

Computer disposal normally includes performing (operation) program or a part for program, existing Programmed value and status information, and by operating system for managing the resource of execution of process. Operating system (OS) be management one computer resource-sharing and be supplied to programmer for Access the software at the interface of those resources.Operating system processing system data and user's input, with And pass through distribution and management role and internal system resources as system of users and the one of program Item service response.

Computer system can such as include at least one processing unit, associative storage and a large amount of Input/output (I/O) equipment.When a computer program is executed, computer system is according to calculating Machine routine processes information and via I/O equipment produce obtained by output information.

In the foregoing description, the present invention is entered by the particular example with reference to the embodiment of the present invention Go description.It may be evident, however, that institute is one or more in without departing from such as claims In the case of the wider spirit and scope of the present invention stated, various modifications and variations can be made.

Connect as in this discussion and can be adapted for such as transmitting from via intermediate equipment or going to Any kind of connection of the signal of corresponding node, unit or equipment.Therefore, unless implied Or additionally show, described connection can be such as connected directly or indirectly.Described connection can To be illustrated or described as relating to singular association, multiple connection, unidirectional connection or being bi-directionally connected. But, different embodiments can change the realization of connection.It is, for example possible to use independent unidirectional company Connect rather than be bi-directionally connected, and vice versa.And, multiple connections may alternatively be even Or transmit the singular association of multiple signal in a time multiplexed manner continuously.Similarly, carry multiple The singular association of signal can be separated into the various different company of the subset carrying these signals Connect.Accordingly, there exist the many options for transmitting signal.

Each signal described in the invention can be designed as positive logic or negative logic.Patrol negative In the case of collecting signal, described signal is low activity, and wherein said logically true state is corresponding to patrolling Collect level 0.In the case of positive logic signal, described signal is high activity, wherein said logic True state is corresponding to logic level 1.Noting, any signal described here can be designed as bearing Logical signal or positive logic signal.Therefore, in alternative embodiments, positive logic letter it is described as Number those signals can be implemented as negative logic signal, and be described as negative logic signal that A little signals can be implemented as positive logic signal.

It will be appreciated by those skilled in the art that the boundary between logical block is merely illustrative also And alternate embodiment can merge logical block or component or at various logic block or component On force the decomposition function of replacement.It is therefore to be understood that framework described here is only example Property, and in fact can realize other frameworks a lot of of identical function.Such as, for Readily appreciating, delimiter assembly 150 generally is illustrated as including that integrated circuit sets in FIG Single discrete functional blocks in standby 105.It should be appreciated, however, that the function of delimiter assembly 150 Can alternatively be distributed in multiple functional device, and/or in straight-through forwarding module 100 Or multiple other assembly is implemented.Such as, the function of delimiter assembly 150 can at least portion Point in the receiver assembly 120 of straight-through forwarding module 100 and/or the function of emitter assemblies 130 Unit is implemented.

In order to realize the layout of any assembly of identical function be effectively " associate " make required Function is achieved.Therefore, at this, combination is permissible to realize any two element of specific function Being counted as " is associated " each other makes required function be achieved, regardless of whether framework or cental element Part.Similarly, any two assembly of so association may be considered as each other by " operable Connect " or " operably coupled " function needed for realizing.

Additionally, those skilled in the art are it will be recognized that boundary between operations described above It is merely exemplary.Multiple operations can be combined into single operation, and single operation can divide Cloth is in additional operations and can perform operation the most overlappingly.And, Alternate embodiment can include multiple examples of specific operation, and the order operated various its Its embodiment can be changed.

And for example, in an embodiment, the example of explanation is implemented at single IC for both On circuit or circuit in identical device.Such as, for the example of diagram in Fig. 1, directly Logical forwarding module 100 is implemented in single IC for both equipment 105.Alternatively, show described in Example may be implemented as any number of independent integrated circuit or phase the most each other The specific installation coupled.Such as, the various assemblies of straight-through forwarding module 100, such as receptor Assembly 120, emitter assemblies 130, by processing various assemblies of making of territory 140 etc., permissible It is distributed in one group of multiple IDE.

And for example, example or a part therein can be such as with the hardware descriptions of any suitable type Language is implemented as the soft of physical circuit or code represents, or is implemented as changing into physics Soft or the code of the logical expressions of circuit represents.

Additionally, this invention is not limited to physical equipment or the unit realized in non-programming hardware, But can also apply in programmable equipment or unit.These equipment or unit are by according to conjunction Suitable program code operation is able to carry out desired functions of the equipments, such as main frame, miniature calculating Machine, server, work station, personal computer, notebook, personal digital assistant, electronics are swum Play, automobile and other embedded system, mobile phone and other wireless device various, in this application It is typically expressed as " computer system ".

But, other is revised, changes and substitute also is possible.Specification and drawings is correspondingly Be considered as from illustrative rather than stricti jurise from the point of view of.

In the claims, any reference marks being placed between bracket is not interpreted as limit Claim processed.Word " includes " being not excluded in addition to those listed in a claim other Element or the existence of step.Additionally, as used herein word " " or " " are defined as or incessantly. And, even if when same claim includes introductory phrase " one or more " or " at least One " and during the indefinite article of such as " " or " ", the most such as " the most extremely Few one " and the use of introductory phrase of " one or more " also should not be interpreted as Imply that other claim element introduced by indefinite article " " or " " will be included so Any specific rights of the claim element introduced requires to be constrained to only comprise such element Invention.Use for definite article is also such.Except as otherwise noted, such as " first " is used And the term of " second " at random distinguishes the element of such term description.Therefore, this A little terms are not necessarily intended to indicate time or other order of priority of such element.The most not With claim described in some measure the fact do not indicate that the combination of these measures can not be by For obtaining advantage.

Claims (12)

1. an IDE (105), described IDE (105) includes directly Logical forwarding module (100), described straight-through forwarding module (100) includes at least one receptor Assembly (120), described receiver assembly (120) is arranged to receive data to be forwarded； And at least one emitter assemblies (130), described emitter assemblies (130) is arranged to Transmission is stored in the data in its at least one transmitter buffer (135)；

Wherein said straight-through forwarding module (100) farther includes at least one delimiter assembly, Described delimiter assembly is operatively coupled in described at least one receiver assembly (120) with described Between at least one emitter assemblies (130), and it is arranged to: once by described at least one Individual receiver assembly (120) receives the of respective Frame (410,420,430,440) The data element (Y) (414,424,434,444) of one number, then trigger described extremely The transmission of the frame data in a few transmitter buffer (135), wherein said at least one is fixed Boundary's symbol assembly (150) is further arranged to: before the described transmission of trigger frame data, passes The data element (X) (412,422,432,442) of defeated second number, described first number Data element (Y) include the first data element predefining integer value and described second number Integer value is predefined including second.

IDE the most according to claim 1 (105), wherein said at least One receiver assembly (120) includes at least one reception wherein storing the data received Device buffer (125).

IDE the most according to claim 1 (105), wherein said second The data element (X) (412,422,432,442) of number is less than or equal to described first number Purpose data element (Y) (414,424,434,444).

IDE the most according to claim 2 (105), wherein said at least One delimiter assembly (150) is arranged to: once by described straight-through forwarding module (100) From at least one receptor buffer (125) described at least one transmitter buffer described (135) data element (X) (412,422,432,442) of described second number is received, The number of described second number is then transmitted in the beginning of Frame (410,420,430,440) According to element (X) (412,422,432,442).

5. according to the IDE (105) described in any aforementioned claim, Qi Zhongsuo State at least one receiver assembly (120) to be arranged to be divided into by individually the data received The block of the data element (B) of the 3rd number of the data processed and transmitted subsequently.

IDE the most according to claim 5 (105), wherein come freely with At least one in the group of lower composition is software configurable parameter: the data element of described first number The element described integer value of (Y), the described integer of data element (X) of described second number Value, the data element (B) of described 3rd number.

IDE the most according to claim 1 (105), wherein said demarcation Symbol (150) includes from least one in the group consisted of:

Internal connection bus (155)；And

Shift register (155)；

Enumerator；And

At least one depositor.

8. the method (700) of the straight-through forwarding performing grouped data, described method includes, In straight-through forwarding module:

Receive frame to be forwarded data (710)；And

Once received respective data by least one receiver assembly of described straight-through forwarding module The data element (Y) (414,424,434,444) of the first number of frame, then by delimiter The frame data that assembly triggering is carried out by least one emitter assemblies of described straight-through forwarding module Transmission (760), described delimiter assembly is operatively coupled at least one receiver assembly described And between at least one emitter assemblies described, the data element (Y) of described first number includes First predefines integer value；And

Before the described transmission of the described frame data in triggering described transmitter buffer, transmission The data element (X) (412,422,432,442) (750) of the second number, described The data element of two numbers includes that second predefines integer value.

Method the most according to claim 8 (700), the number of wherein said second number The data of described first number it are less than or equal to according to element (X) (412,422,432,442) Element (Y) (414,424,434,444).

Method the most according to claim 8 (700), wherein transmits described second number Data element (X) (412,422,432,442) including: upon receipt of described second The data element (X) (412,422,432,442) of number, then at the Frame received Beginning the data element (X) (412,422,432,442) of described second number is passed It is passed to transmitter buffer.

11., according to Claim 8 to any one the described method (700) in 10, enter One step includes the frame data received are divided into the data being treated separately and being transmitted subsequently The block of data element (B) of the 3rd number.

12. methods according to claim 11 (700), farther include via software Configure from least one in the group consisted of: the data element of described first number (Y) described integer value, the described integer value of the data element (X) of described second number, The data element (B) of described 3rd number.