CN103675372A - Random-order electrical level generator - Google Patents
Random-order electrical level generator Download PDFInfo
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- CN103675372A CN103675372A CN201310689269.0A CN201310689269A CN103675372A CN 103675372 A CN103675372 A CN 103675372A CN 201310689269 A CN201310689269 A CN 201310689269A CN 103675372 A CN103675372 A CN 103675372A
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Abstract
The invention provides a random-order electrical level generator. The random-order electrical level generator comprises a selection circuit and multiple MOS tubes connected with the selection circuit, wherein the grid electrode of each MOS tube is connected with the selection circuit, and the source electrode or the drain electrode of each MOS tube is connected with one electrical level. According to the random-order electrical level generator, since the multiple MOS tubes are arranged, and the source electrode or the drain electrode of each MOS tube is connected with one electrical level, electrical levels with multiple orders are provided, such as a three-order electrical level and a four-order electrical level, or a two-order electrical level different from a two-order electrical level which can be provided by a testing machine is provided.
Description
Technical field
The present invention relates to integrated circuit manufacturing equipment technical field, particularly a kind of arbitrary order level generator.
Background technology
Due to the rapid introducing of day by day complicated integrated circuit, material and technique, hardly may the requirement up to specification of each chip in the silicon chip of today is manufactured.For correcting the problem in manufacturing process, and guarantee that defective chip can not be sent in client's hand, in ic manufacturing process, introduced chip testing (CP, Circuit Probing).Chip testing is that the electrical parameter carrying out on silicon chip level integrated circuit in order to check the consistance of specification is measured and functional test.Test can check out each chip whether to have acceptable electric property and complete function, and the electricity specification of using in its test process is different with the difference of test purpose.If chip testing imperfection, just may cause more product to lose efficacy, finally to chip maker, bring serious consequence in client's use procedure.In the manufacture process of integrated circuit, introduce and can find early technological problems and the select chip testing of bad chip is absolutely necessary for this reason.
Chip test system generally includes: test machine (Automatic Test Equipment, ATE), probe (Probe Card) and probe station (Prober), wherein, test machine is the aut.eq. that can fast, accurately, repeatedly measure submicron level electric current and millivolt step voltage on measured device; Probe is the coupling arrangement between test machine and measured device; Probe station, can be in the position of X, Y and Z direction adjustment measured device also referred to as chip positioning device.During test, test machine is input to curtage signal in the measured device (DUT, Device Under Test) on probe station via probe, and then this measured device is turned back to tester for the accordingly result of input signal.
Common, test machine can only be exported two rank voltages, and be generally-1V of the voltage range of its output is to 7V.But, in chip testing process, need sometimes more multistage voltage, such as three rank, quadravalence etc.; Or the two rank voltages that sometimes need are different from the voltage that test machine can provide.Therefore, how to provide the voltage more than two rank, or provide two rank voltages of other magnitude of voltage to become those skilled in the art's problem demanding prompt solution.
Summary of the invention
The object of the present invention is to provide a kind of arbitrary order level generator, to solve existing test machine, can only export two rank voltages, and be generally-1V of the voltage range of its output is to 7V, but, in chip testing process, need sometimes more multistage voltage, such as three rank, quadravalence etc.; Or the different problem of two rank magnitudes of voltage that the two rank magnitudes of voltage that sometimes need can provide from test machine.
For solving the problems of the technologies described above, the invention provides a kind of arbitrary order level generator, described arbitrary order level generator comprises: a plurality of metal-oxide-semiconductors selecting circuit and be connected with described selection circuit, wherein, the grid of each metal-oxide-semiconductor is connected with described selection circuit, and the source electrode of each metal-oxide-semiconductor or drain electrode are connected with a level.
Optionally, in described arbitrary order level generator, described selection circuit is by providing level to choose corresponding metal-oxide-semiconductor to grid.
Optionally, in described arbitrary order level generator, the level that described selection circuit provides is 3.5V～5V.
Optionally, in described arbitrary order level generator, described selection circuit is pulse producer.
Optionally, in described arbitrary order level generator,
When the source electrode of metal-oxide-semiconductor is connected with a level, the drain electrode of this metal-oxide-semiconductor provides voltage to measured device;
When the drain electrode of metal-oxide-semiconductor is connected with a level, the source electrode of this metal-oxide-semiconductor provides voltage to measured device.
Optionally, in described arbitrary order level generator, the quantity of described metal-oxide-semiconductor is two, three or four.
Optionally, in described arbitrary order level generator, the level value that the source electrode of each metal-oxide-semiconductor or drain electrode connect is different.
In arbitrary order level generator provided by the invention, source electrode or drain electrode by a plurality of metal-oxide-semiconductors and each metal-oxide-semiconductor are connected with a level, more multistage level (such as three rank or quadravalence etc.) are provided or provide to be different from the two rank level that test machine can provide.
Accompanying drawing explanation
Fig. 1 is the mount structure schematic diagram of the arbitrary order level generator of the embodiment of the present invention one;
Fig. 2 is the mount structure schematic diagram of the arbitrary order level generator of the embodiment of the present invention two.
Embodiment
Arbitrary order level generator the present invention being proposed below in conjunction with the drawings and specific embodiments is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
[embodiment mono-]
Please refer to Fig. 1, it is the mount structure schematic diagram of the arbitrary order level generator of the embodiment of the present invention one.As shown in Figure 1, described arbitrary order level generator comprises: two metal-oxide-semiconductors selecting circuit 10 and be connected with described selection circuit 10, be respectively metal-oxide-semiconductor 11a and metal-oxide-semiconductor 11b, wherein, the grid of each metal-oxide-semiconductor is connected with described selection circuit 10, and the source electrode of each metal-oxide-semiconductor or drain electrode are connected with a level.
In the present embodiment, described selection circuit 10 can be by provide level to choose corresponding metal-oxide-semiconductor to grid, and concrete, described selection circuit 10 can be pulse producer.For example, described selection circuit 10 provides the level of 3.5V to described metal-oxide-semiconductor 11a, thereby described metal-oxide-semiconductor 11a is opened, and realizes described selection circuit 10 for the selection of described metal-oxide-semiconductor 11a.Common, the cut-in voltage of metal-oxide-semiconductor is 3V～5V, and therefore, preferred, the level that described selection circuit 10 provides is 3.5V～5V.Concrete, for example, the cut-in voltage of described metal-oxide-semiconductor is 3V, the level that described selection circuit 10 provides is 3.5V or 4V etc.; The cut-in voltage of described metal-oxide-semiconductor is 4V, and the level that described selection circuit 10 provides is 4V or 4.5V etc.In addition, if the cut-in voltage of described metal-oxide-semiconductor is larger, corresponding, described selection circuit 10 can provide higher level.
In the present embodiment, the source electrode of each metal-oxide-semiconductor can be connected with a level, for example, the source electrode of metal-oxide-semiconductor 11a is connected with level 3.5V, the source electrode of metal-oxide-semiconductor 11b is connected with level 7.6V, and the arbitrary order level generator providing by the present embodiment can provide to measured device the level of 3.5V and 7.6V.Concrete, the drain electrode of the drain electrode of metal-oxide-semiconductor 11a and metal-oxide-semiconductor 11b is connected with measured device, and the drain electrode by metal-oxide-semiconductor 11a provides 3.5V level to measured device, and the drain electrode by metal-oxide-semiconductor 11b provides 7.6V level to measured device.
As can be seen here, the arbitrary order level generator providing by the present embodiment can provide and be different from the two rank level that test machine can provide.
[embodiment bis-]
Please refer to Fig. 2, it is the mount structure schematic diagram of the arbitrary order level generator of the embodiment of the present invention two.As shown in Figure 2, described arbitrary order level generator comprises: three metal-oxide-semiconductors selecting circuit 20 and be connected with described selection circuit 20, be respectively metal-oxide-semiconductor 21a, metal-oxide-semiconductor 21b and metal-oxide-semiconductor 21c, wherein, the grid of each metal-oxide-semiconductor is connected with described selection circuit 20, and the source electrode of each metal-oxide-semiconductor or drain electrode are connected with a level.
Same, in the present embodiment, described selection circuit 20 can be by provide level to choose corresponding metal-oxide-semiconductor to grid, and concrete, described selection circuit 20 can be pulse producer.For example, described selection circuit 20 provides the level of 3.5V to described metal-oxide-semiconductor 21a, thereby described metal-oxide-semiconductor 21a is opened, and realizes described selection circuit 20 for the selection of described metal-oxide-semiconductor 21a.Common, the cut-in voltage of metal-oxide-semiconductor is 3V～5V, and therefore, preferred, the level that described selection circuit 20 provides is 3.5V～5V.Concrete, for example, the cut-in voltage of described metal-oxide-semiconductor is 3V, the level that described selection circuit 20 provides is 3.5V or 4V etc.; The cut-in voltage of described metal-oxide-semiconductor is 4V, and the level that described selection circuit 20 provides is 4V or 4.5V etc.In addition, if the cut-in voltage of described metal-oxide-semiconductor is larger, corresponding, described selection circuit 20 can provide higher level.
In the present embodiment, the drain electrode of each metal-oxide-semiconductor can be connected with a level, for example, the drain electrode of metal-oxide-semiconductor 21a is connected with level 3.2V, the drain electrode of metal-oxide-semiconductor 21b is connected with level 4.7V, the drain electrode of metal-oxide-semiconductor 21c is connected with level 5.4V, and the arbitrary order level generator providing by the present embodiment can provide to measured device the level of 3.2V, 4.7V and 5.4V.Concrete, the source electrode of the source electrode of the source electrode of metal-oxide-semiconductor 21a, metal-oxide-semiconductor 21b and metal-oxide-semiconductor 21c is connected with measured device, source electrode by metal-oxide-semiconductor 21a provides 3.2V level to measured device, source electrode by metal-oxide-semiconductor 21b provides 4.7V level to measured device, and the source electrode by metal-oxide-semiconductor 21c provides 5.4V level to measured device.
As can be seen here, the arbitrary order level generator providing by the present embodiment can provide more multistage level.
In sum, in the arbitrary order level generator providing in the embodiment of the present invention, source electrode or drain electrode by a plurality of metal-oxide-semiconductors and each metal-oxide-semiconductor are connected with a level, more multistage level (such as three rank or quadravalence etc.) can be provided or provide to be different from the two rank level that test machine can provide.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure, all belong to the protection domain of claims.
Claims (7)
1. an arbitrary order level generator, is characterized in that, comprising: a plurality of metal-oxide-semiconductors selecting circuit and be connected with described selection circuit, and wherein, the grid of each metal-oxide-semiconductor is connected with described selection circuit, and the source electrode of each metal-oxide-semiconductor or drain electrode are connected with a level.
2. arbitrary order level generator as claimed in claim 1, is characterized in that, described selection circuit is by providing level to choose corresponding metal-oxide-semiconductor to grid.
3. arbitrary order level generator as claimed in claim 2, is characterized in that, the level that described selection circuit provides is 3.5V～5V.
4. arbitrary order level generator as claimed in claim 1, is characterized in that, described selection circuit is pulse producer.
5. arbitrary order level generator as claimed in claim 1, is characterized in that,
When the source electrode of metal-oxide-semiconductor is connected with a level, the drain electrode of this metal-oxide-semiconductor provides voltage to measured device;
When the drain electrode of metal-oxide-semiconductor is connected with a level, the source electrode of this metal-oxide-semiconductor provides voltage to measured device.
6. arbitrary order level generator as claimed in claim 1, is characterized in that, the quantity of described metal-oxide-semiconductor is two, three or four.
7. the arbitrary order level generator as described in any one in claim 1～6, is characterized in that, the level value that the source electrode of each metal-oxide-semiconductor or drain electrode connect is different.
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| CN201310689269.0A CN103675372A (en) | 2013-12-16 | 2013-12-16 | Random-order electrical level generator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103837823A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Product testing circuit |
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| US5065092A (en) * | 1990-05-14 | 1991-11-12 | Triple S Engineering, Inc. | System for locating probe tips on an integrated circuit probe card and method therefor |
| CN101101393A (en) * | 2007-08-06 | 2008-01-09 | 友达光电股份有限公司 | Liquid crystal display device and its driving method |
| CN101874349A (en) * | 2008-03-27 | 2010-10-27 | 艾格瑞系统有限公司 | High voltage tolerant input/output interface circuit |
| US20100327893A1 (en) * | 2009-06-26 | 2010-12-30 | Vilas Boas Andre Luis L | Probing Structure for Evaluation of Slow Slew-Rate Square Wave Signals in Low Power Circuits |
| CN102507993A (en) * | 2011-10-19 | 2012-06-20 | 电子科技大学 | Burst signal generator with automatic initial phase calibration function |
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2013
- 2013-12-16 CN CN201310689269.0A patent/CN103675372A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5065092A (en) * | 1990-05-14 | 1991-11-12 | Triple S Engineering, Inc. | System for locating probe tips on an integrated circuit probe card and method therefor |
| CN101101393A (en) * | 2007-08-06 | 2008-01-09 | 友达光电股份有限公司 | Liquid crystal display device and its driving method |
| CN101874349A (en) * | 2008-03-27 | 2010-10-27 | 艾格瑞系统有限公司 | High voltage tolerant input/output interface circuit |
| US20100327893A1 (en) * | 2009-06-26 | 2010-12-30 | Vilas Boas Andre Luis L | Probing Structure for Evaluation of Slow Slew-Rate Square Wave Signals in Low Power Circuits |
| CN102507993A (en) * | 2011-10-19 | 2012-06-20 | 电子科技大学 | Burst signal generator with automatic initial phase calibration function |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103837823A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Product testing circuit |
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Application publication date: 20140326 |