CN103748570A - Storage controller with host collaboration for initialization of a logical volume - Google Patents

Storage controller with host collaboration for initialization of a logical volume Download PDF

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CN103748570A
CN103748570A CN201180072861.5A CN201180072861A CN103748570A CN 103748570 A CN103748570 A CN 103748570A CN 201180072861 A CN201180072861 A CN 201180072861A CN 103748570 A CN103748570 A CN 103748570A
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memory controller
sparse
logical volume
initialization
main frame
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纳撒尼尔·S·德内韦
约瑟夫·大卫·布莱克
仁·Q·沃
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Hewlett Packard Development Co LP
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0632—Configuration or reconfiguration of storage systems by initialisation or re-initialisation of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD

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Abstract

A device includes a storage controller for accessing a logical volume. The storage controller collaborates with a host to initialize the logical volume such that host resources perform a portion of the initialization of the logical volume.

Description

For the initialized memory controller of logical volume, cooperate with main frame
Background technology
Memory controller (as Redundant Array of Independent Disks controller) is used for physical memory devices (as hard disk or other memory device) to be organized into can be by the logical volume of host access.For optimum performance, memory controller can carry out initialization to logical volume.Initialization can be parity checking initialization procedure, process of reconstruction, RAID grade/stripe size transition process, volume expansion process or the erase process to logical volume.
The memory resource restriction memory controller of memory controller can be carried out to logical volume the speed of initialization procedure.Further, during initialization procedure, simultaneous main frame I/O (I/O) operation does not promote initialization procedure and can consume memory controller resource, and this hinders memory controller to completing initialization procedure progress.In addition, along with hardware advances, the size of physical disk capacity increases, thereby has increased the quantity completing the needed independent I/O operation of the initialization procedure of logical volume.
Along with the demand of the increase to performance and redundancy, it is more and more of a specified duration that initialization procedure is just becoming, and this can cause the non-optimum performance of memory controller.Longer initialization time in low performance state (for example causes the more substantial time, about uncompleted parity checking initialization procedure) or in have the multiple parts of logical volume data redundancy lose degenerate state (for example,, about uncompleted process of reconstruction).
Accompanying drawing explanation
Fig. 1 is the block diagram of an example of system shown.
Fig. 2 is the block diagram of an example of diagram server.
Fig. 3 is the block diagram of an example of diagram memory controller.
Fig. 4 is the functional block diagram of the initialized example of diagram logical volume.
Fig. 5 is the block diagram of an example of diagram sparse sequence metadata structure.
Fig. 6 is diagram upgrades/follow the tracks of an example of metadata functional block diagram via sparse sequence metadata structure.
Fig. 7 is the process flow diagram of diagram for an example of the method for initialization logic volume.
Embodiment
In the following detailed description, with reference to accompanying drawing, accompanying drawing forms the part of this instructions, and by diagram, the particular example that can put into practice present disclosure is shown in accompanying drawing.Should be understood that and can use other example, and in the case of not departing from the scope of present disclosure, can carry out structural change or logic variation.Therefore, detailed description below should be from the limited significance consideration of getting on, and the scope of present disclosure is defined by the following claims.Should be understood that unless otherwise specifically indicated, otherwise the feature of each example described herein can be bonded to each other.
Fig. 1 is the block diagram of an example of system shown 100.System 100 comprises main frame 102, memory controller 106 and memory device 110.Main frame 102 can be attached to memory controller 106 communicatedly via communication link 104.Memory controller 106 can be attached to memory device 110 communicatedly via communication link 108.Main frame 102 is computing equipments, as server, personal computer or use LBA (Logical Block Addressing) from memory device 110 reading out datas and store other suitable computing equipment of data memory device 110.Memory controller 106 provides the interface between main frame 102 and memory device 110, and this interface is for converting the LBA (Logical Block Addressing) of being used by main frame 102 to physical block address for accessing storage device 110.
Memory controller 106 is also carried out initialization procedure to the logical volume of the physical volume that is mapped to memory device 110, and this initialization procedure comprises parity checking initialization procedure, process of reconstruction, Redundant Array of Independent Disks grade/stripe size transition process, volume expansion process, erase process and/or other suitable initialization procedure.During initialization procedure, memory controller 106 aligns write operation that one or more logical volumes of being initialised carry out and comes the progress of tracking initiation process by following the tracks of memory controller 106 and main frame 102.In one example, by following the tracks of Client-initiated, by main frame 102, aligned the write operation (write operation generating by the normal use of memory controller) of the logical volume execution being initialised outside initialization procedure, main frame 102 promotes completing of initialization procedure indirectly, because memory controller 106 needn't repeat the write operation of being carried out by main frame 102.In another example, main frame 102 also initiatively promotes completing of initialization procedure by the directly execution that cooperates with memory controller 106 about at least a portion of the write operation of initialization procedure.
Compare with the conventional store controller that can not cooperate with main frame, initialization procedure has been accelerated in the cooperation for completing the initialization procedure to logical volume of main frame 102 and memory controller 106.Therefore, logical volume is than turn back to sooner high performance operation state in legacy system.In addition, in one example, can distribute untapped host resource to carry out initialization procedure, thereby more effectively utilize available resources.In one example, by making main frame I/O (I/O) can manage the host resource for carrying out initialization procedure, user can directly specify the speed of initialization procedure.
Fig. 2 is the block diagram of an example of diagram server 120.Server 120 comprises processor 122, storer 126, memory controller 106 and miscellaneous equipment 128 (1)-128 (n), and wherein " n " is the integer that represents any suitable number of miscellaneous equipment.In one example, the main frame 102 that processor 122, storer 126 and miscellaneous equipment 128 (1)-128 (n) are described and illustrated about Fig. 1 before providing.Processor 122, storer 126, memory controller 106 and miscellaneous equipment 128 (1)-128 (n) can connect each other communicatedly via communication link 124.In one example, communication link 124 is buses.In one example, communication link 124 is high-speed buses, as peripheral assembly high-speed interconnect (PCIe) bus or other suitable high-speed bus.Miscellaneous equipment 128 (1)-128 (n) comprises network interface, other memory controller, display adapter, I/O equipment and/or other suitable equipment of a part for server 120 is provided.
Processor 122 comprises central processing unit (CPU) or other suitable processor.In one example, storer 126 store that move by processor 122, for the instruction of operations server 120.Storer 126 comprises volatile memory and/or nonvolatile memory random suitable combination, as the combination of random-access memory (ram), ROM (read-only memory) (ROM), flash memory and/or other suitable storer.Processor 122 is via memory controller 106 accessing storage device 110(Fig. 1).Processor 122 resources are for cooperating with memory controller 106, logical volume is carried out to initialization procedure as described about Fig. 1 before.
Fig. 3 is the block diagram of an example of diagram memory controller 106.Memory controller 106 comprises processor 130, storer 132 and storage protocol equipment 134.Processor 130, storer 132 and storage protocol equipment 134 can be coupled to each other communicatedly via communication link 124.Storage protocol equipment 134 can be attached to memory device 110 (a)-110 (m) communicatedly via communication link 108, and wherein " m " is the integer that represents any suitable number of memory device.Memory device 110 (1)-110 (m) comprises hard disk drive, flash drive, CD-ROM drive and/or other suitable memory device.In one example, communication link 108 comprises bus, as Serial Advanced Technology Attachment (SATA) bus or other suitable bus.
Processor 130 comprises central processing unit (CPU), controller or other suitable processor.In one example, storer 132 store that move by processor 130, for the instruction of operation store controller 106.Storer 132 comprises the combination of any appropriate of volatile memory and/or nonvolatile memory, as the combination of RAM, ROM, flash memory and/or other suitable storer.Storage protocol equipment 134 converts the order receiving from main frame, be sent to memory controller 106 to order for accessing storage device 110 (1)-110 (m).Processor 130 operations are for converting the LBA (Logical Block Addressing) receiving from main frame to instruction for the physical block address of accessing storage device 110 (1)-110 (m).That before processor 130 operation, about Fig. 1, describes in addition, carries out the instruction of initialization procedure and for carrying out the instruction of the progress of following the tracks of this initialization procedure for the logical volume to the physical volume that is mapped to memory device 110 (a)-110 (m).
Fig. 4 is functional block Figure 138 of an initialized example of diagram logical volume 160 (1)-160 (y), and wherein " y " is the integer that represents any suitable number of logical volume.Logical volume 160 (1)-160 (y) is mapped to the physical volume (Fig. 3) of memory device 110 (1)-110 (m).Main frame 102 sends control command via the communication link 124 as shown in 146 to memory controller 106.Memory controller 106 sends control command via the communication link 124 as shown in 148 to main frame 102.Memory controller 106 sends control command to logical volume 160 (1)-160 (y), as shown in 156.Logical volume 160 (1)-160 (y) sends control command to memory controller 106, as shown in 158.
In this example, by host resource is distributed to initialization procedure, main frame 102 promotes logical volume 160 (1)-160 the initialized of (y) to complete on one's own initiative.When notice is during about the initialization procedure of logical volume 160 (1)-160 (y), main frame 102 is one or more computational threads 140 (1)-140 (x) for this initialization procedure distributes, and wherein " x " is the integer that represents any suitable number of the computational threads of distributing.The quantity of the computational threads of distributing to initialization procedure in one example, is that user specifies.By poll memory controller 106, carried out acquired information or passed through other appropriate technology, memory controller 106 can be notified initialization procedure to main frame 102.To each computational threads 140 (1)-140 (x), distribute respectively the buffer zone 142 (1)-142 (x) of himself, to initiate read operation and the write operation to logical volume 160 (1)-160 (y).
In this example, read operation and the write operation to logical volume 160 (1) that initiate as shown in 144 (1) computational threads 140 (1) and buffer zone 142 (1), to promote the completing of initialization procedure of logical volume 160 (1).Read operation and the write operation to logical volume 160 (1) as shown in 144 (2) also initiated in computational threads 140 (2) and buffer zone 142 (2), to promote the completing of initialization procedure of logical volume 160 (1).Computational threads 140 (x) and buffer zone 142 (x) initiate read operation and the write operation to logical volume 160 (y) as shown in 144 (x), to promote the completing of initialization procedure of logical volume 160 (y).In other example, distribute other computational threads and buffer zone separately to initiate read operation and the write operation to other logical volume, to promote the completing of initialization procedure of these logical volumes.The read operation from main frame 102 to logical volume 160 (1)-160 (y) as shown in 144 (1)-144 (x) and write operation are through bus 124 and memory controller 106.In one example, main frame 102 stops the write operation of the piece of Client-initiated to the current logical volume just being operated by computational threads 140 (1)-140 (x).
Memory controller 106 comprises computational threads 150 and buffer zone 152, read operation and the write operation to logical volume 160 (1) as shown in 154 initiated in computational threads 150 and buffer zone 152, to promote the completing of initialization procedure of logical volume 160 (1).In other example, read operation and the write operation to another logical volume initiated in computational threads 150 and buffer zone 152, to promote the completing of initialization procedure of this logical volume.Therefore, in this example, parallel read operation and the write operation of initiating logical volume 160 (1) of the computational threads with buffer zone 152 150 of the computational threads with buffer zone 142 (1) 140 (1) of main frame 102, the computational threads with buffer zone 142 (2) 140 (2) of main frame 102 and memory controller 106, with the initialization procedure of completion logic volume 160 (1).
Memory controller 106 is gone back the progress of the initialization procedure of trace logic volume 160 (1)-160 (y).To each independent logical volume 160 (1)-160 (y), which logical block memory controller 106 follows the tracks of is initialised.For example, to logical volume 160 (1), write operation memory controller 106 which logical block of tracking have been initiated by the computational threads with buffer zone 152 150 of memory controller 106, the write operation of being initiated by the computational threads with buffer zone 142 (1) 140 (1) of main frame 102 and the write operation initialization of being initiated by the computational threads with buffer zone 142 (2) 140 (2) of main frame 102.Similarly, to logical volume 160 (y), which logical block memory controller 106 follows the tracks of by the write operation initialization of being initiated by the computational threads 140 (x) with buffer zone 142 (x).In one example, memory controller 106 sends trace information to main frame 102 termly, makes main frame 102 not repeat the initialization operation of being carried out by memory controller 106.In another example, main frame 102 poll memory controllers 106 obtain the variation of trace information, make main frame 102 not repeat the initialization operation of being carried out by memory controller 106.
Fig. 5 is the block diagram of an example of diagram sparse sequence metadata structure 200.In one example, sparse sequence metadata structure 200 is stored controller 106(Fig. 1-Fig. 4) be used for trace logic volume (as logical volume 160 (1)-160 (y) (Fig. 4)) the progress of initialization procedure.When the initialization procedure of logical volume starts, memory controller 106 is each establishing logical volume sparse sequence metadata structure 200.Once according to the initialization procedure that is stored in metadata in sparse sequence metadata structure 200 and has completed logical volume, just wipe sparse sequence metadata structure 200.
In this example, sparse sequence metadata structure 200 comprises sparse sequence metadata 202 and sparse item 220 (1), 220 (2) and 220 (3).During the initialization procedure of logical volume, can change the quantity of sparse of sparse sequence metadata structure 200.When the initialization procedure of logical volume completes, for the sparse sequence metadata structure 200 of this logical volume, will only comprise one sparse.
Sparse sequence metadata 202 comprises multiple fields, and multiple fields comprise logical volume in pointer, the operation as shown in 208 of head of sparse of sparse quantity, the sensing as shown in 206 as shown in 204 or logical unit number (LUN) and complete parameter as shown in 210.In one example, complete the scope that parameter comprises the LBA (Logical Block Addressing) of the initialization procedure that meets logical volume.In other example, sparse sequence metadata 202 can comprise other appropriate fields for sparse sequence metadata structure 200.
Each sparse 220 (1), 220 (2) and 220 (3) comprises two fields, and these two fields comprise respectively the LBA (Logical Block Addressing) (LBA) as shown in 222 (1), 222 (2) and 222 (3) and the length as shown in 224 (1), 224 (2) and 224 (3).The LBA (Logical Block Addressing) of each sparse and length represent the part being initialised of logical volume.Sparse sequence metadata 202 links to first sparse 220 (1) via the pointer 206 that points to head as shown in 212.As shown in 226 (1), link to second sparse 220 (2) for first sparse 220 (1).Similarly, as shown in 226 (2), link to the 3rd sparse 220 (3) for second sparse 220 (2).Similarly, can link to other sparse (not shown) for the 3rd sparse 220 (3).In one example, according to LBA (Logical Block Addressing) 222 (1), 222 (2) and 222 (3), arrange in order respectively for sparse 220 (1), 220 (2) and 220 (3).
Fig. 6 is diagram upgrades/follow the tracks of an example of metadata functional block diagram 250 via the sparse sequence metadata structure 200 of describing about Fig. 5 before and illustrate.To the in operation each arrival write operation from main frame 102 or memory controller 106 to logical volume as shown in 260, memory controller 106 generates sparse 264 as shown in 262.Comprise just by the LBA as shown in 266 and the length as shown in 268 in the initialized logical volume part of write operation for sparse 264.After generating sparse item 264, memory controller 106 for example merges to, in existing sparse (, sparse 220 (1), 220 (2) or 220 (3)) or sparse 264 is in position inserted in sparse sequence metadata structure 200 as shown in 270 sparse 264.
For example, if sparse 264 comprise represent this logical volume adjacent with the part by shown in LBA and the length of existing sparse this logical volume (just before or just after) LBA266 and the length 268 of part, this existing sparse item of memory controller 106 modifications.This existing sparse item is revised as and comprises suitable LBA and length, make the part being newly initialised based on sparse 264 based on this part being initialised before of existing sparse and this logical volume of sparse revised this logical volume of expression.If sparse 264 comprise and represent this logical volume and LBA266 and length 268 by the non-conterminous part of part shown in LBA and the length of existing sparse this logical volume, memory controller 106 is in position inserted in sparse sequence metadata structure 200 sparse 264.Memory controller 106 (is for example inserted into first sparse according to LBA266 by sparse 264, sparse 220 (1)) before, be inserted into sparse between (for example, between sparse 220 (1) and sparse 220 (2) or between sparse 220 (2) and sparse 220 (3)) or be inserted into last sparse (for example, sparse 220 (3)) afterwards.
After each write operation, the process that memory controller 106 is carried out as shown in 256 completes inspection.Process completes and checks to receive complete parameter 210 as shown in 252, and as shown in 254 from LBA222 (1) and the length 224 (1) of first sparse 220 (1).Process completes and checks completing parameter 210 and comparing from LBA222 (1) and the length 224 (1) of first sparse 220 (1) from sparse sequence metadata 202.When logic volume initialization completes, sparse sequence metadata structure 200 will only comprise first sparse 220 (1), to comprise LBA222 (1) and length 224 (1) for first sparse 220 (1), LBA222 (1) and length 224 (1) represent to meet the LBA scope of this initialization procedure.Therefore, by by sparse 220 (1) LBA222 (1) and length 224 (1) with complete parameter 210 and compare, whether the initialization procedure of memory controller 106 definite these logical volumes completes.In one example, when the initialization procedure of logical volume completes, memory controller 106 is wiped the sparse sequence metadata structure for this logical volume.
By follow the tracks of the part being initialised of this logical volume via sparse sequence metadata structure, the computational threads of main frame 102 can operate in the arbitrary region of this logical volume, even disjunct region, and do not expend memory controller 106 resources.In one example, memory controller 106 can be used for filling the region that is not connected between main frame 102 computational threads operations.In addition,, by using sparse sequence metadata structure, memory controller 106 needn't be stored a large amount of metadata and follow the tracks of the progress of multiple parts that are not connected of this logical volume.The write operation from main frame that Client-initiated generates by the normal use of memory controller outside initialization procedure is also counted initialization procedure, and follows the tracks of by sparse sequence metadata structure.
Fig. 7 is for example, process flow diagram for an example of the method 300 of initialization logic volume (logical volume 160 (1) or the logical volume 160 (y), describing and illustrate about Fig. 4) before of diagram.At 302 places, start the initialization procedure of logical volume.This initialization procedure can comprise parity checking initialization procedure, process of reconstruction, RAID grade/stripe size transition process, volume expansion process, erase process or other suitable initialization procedure.Logic volume initialization can be started by memory controller or main frame.
At 304 places, memory controller (memory controller 106 of for example, describing and illustrating about Fig. 1-Fig. 4 before) creates metadata and follows the tracks of the progress of this initialization procedure (the sparse sequence metadata structure 200 of for example, describing and illustrating about Fig. 5 before).At 306 places, memory controller is carried out initialization operation to this logical volume.At 308 places, parallel with memory controller initialization operation, main frame is carried out write operation to this logical volume.In one example, main frame write operation is the write operation that Client-initiated generates by the normal use of memory controller outside initialization procedure.In another example, main frame write operation is the initialization operation for initiatively promoting initialization procedure.
At 310 places, upgrade/tracking of memory controller is used for memory controller initialization operation and/or the metadata for main frame write operation.In one example, be used for the sparse sequence metadata structure of logical volume by renewal, memory controller upgrades/follows the tracks of metadata.At 312 places, memory controller determines according to metadata whether initialization procedure completes.If initialization procedure does not complete, so at 306 places, memory controller is carried out another initialization operation.As shown in 308, main frame can also continue to write to logical volume.If initialization procedure completes, so as 314 shown in, the method finishes.
The example of present disclosure provides a kind of system that comprises main frame and memory controller, and this main frame and this memory controller have cooperated the initialization procedure to logical volume.The progress of memory controller tracking initiation process, makes not repetitive operation.In one example, by the normal main frame write operation outside initialization procedure, main frame promotes initialization procedure indirectly.In another example, by giving initialization procedure Resources allocation, main frame promotes initialization procedure on one's own initiative.
By cooperation, complete initialization procedure, can distribute untapped host resource to carry out initialization operation.User can configure host resource is enshrined and worship to the speed to initialization procedure, and this allows the control of user to host resource, to accelerate initialization procedure.Host resource can be used in the multiple logical volumes on the multiple attached memory controllers of initialization simultaneously, and this allows parallel initialization process faster.Therefore, not increasing under the condition of the available resources in main frame or memory controller, compare with the legacy system not cooperating with memory controller about initialization procedure main frame, improve the speed of initialization procedure.
Although illustrated herein and described multiple concrete examples, it will be understood by those skilled in the art that various implementations alternative and/or that be equal to can replace shown and described concrete example, and do not depart from the scope of present disclosure.The application is intended to cover modification or the modification of the concrete example of introducing herein.Therefore, wish that present disclosure is only by claims and equivalents thereof.

Claims (15)

1. an equipment, comprising:
Memory controller, for access logic volume, described memory controller and the main frame logical volume described in initialization that cooperates with, makes host resource carry out an initialized part for described logical volume.
2. equipment according to claim 1, wherein said memory controller is followed the tracks of described initialized progress by main frame write operation and the memory controller write operation followed the tracks of described logical volume.
3. equipment according to claim 2, wherein said memory controller is followed the tracks of described initialized progress via sparse sequence metadata structure, and
Wherein said memory controller is that each main frame write operation and each memory controller write operation generate sparse, and by generated sparse item merge to described sparse sequence metadata structure before sparse in or generated sparse is inserted in described sparse sequence metadata structure.
4. equipment according to claim 3, wherein said memory controller is that the each main frame write operation to described logical volume of Client-initiated generates sparse.
5. equipment according to claim 1, the computational threads of wherein said host assignment user's specified quantity, each computational threads has the buffer zone being assigned with, to carry out a described initialized part for described logical volume.
6. equipment according to claim 5, wherein said main frame stops the write operation of the piece of Client-initiated to the current described logical volume just being operated by computational threads.
7. equipment according to claim 1, wherein said initialization one of comprises in parity checking initialization procedure, process of reconstruction, RAID grade/stripe size transition process, volume expansion process and erase process.
8. an equipment, comprising:
Main frame; And
Memory controller, for access logic volume, described memory controller cooperates with described main frame described logical volume is carried out to initialization procedure, makes host resource carry out a part for described initialization procedure,
Wherein said memory controller, by following the tracks of main frame write operation and the memory controller write operation to described logical volume, is followed the tracks of the progress of described initialization procedure as promoting described initialization procedure.
9. equipment according to claim 8, wherein said memory controller is followed the tracks of the progress of described initialization procedure via the sparse sequence metadata structure for described logical volume, described sparse sequence metadata structure comprises sparse, and described sparse item comprises logical block address field and the length field of the part being initialised that represents described logical volume.
10. equipment according to claim 8, wherein said memory controller and described main frame are parallel carries out initialization operation to described logical volume.
11. 1 kinds of methods for initialization logic volume, described method comprises:
Use memory controller resource to carry out initialization operation to described logical volume;
Use host resource to carry out Client-initiated operation to described logical volume; And
Follow the tracks of the described Client-initiated operation of using the described initialization operation of memory controller resource execution and using host resource to carry out, as promoting described logic volume initialization.
12. methods according to claim 11, further comprise:
Use host resource to carry out initialization operation to described logical volume.
13. methods according to claim 12, further comprise:
With parallel to described logical volume execution initialization operation, use host resource to carry out initialization operation to other logical volume.
14. methods according to claim 11, wherein said tracking comprises:
For each initialization operation and the operation of each Client-initiated, generate sparse for sparse sequence metadata structure; And
Generated sparse item is merged in the sparse item generating before of described sparse sequence metadata structure, or generated sparse item is inserted in described sparse sequence metadata structure.
15. methods according to claim 11, wherein carry out initialization operation and comprise and one of carrying out in parity checking initialization operation, reconstruction operation, RAID grade/stripe size migration operation, volume extended operation and erase operation.
CN201180072861.5A 2011-12-13 2011-12-13 Storage controller with host collaboration for initialization of a logical volume Pending CN103748570A (en)

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