CN103779221A - Semiconductor device forming method - Google Patents

Semiconductor device forming method Download PDF

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Publication number
CN103779221A
CN103779221A CN201210406255.9A CN201210406255A CN103779221A CN 103779221 A CN103779221 A CN 103779221A CN 201210406255 A CN201210406255 A CN 201210406255A CN 103779221 A CN103779221 A CN 103779221A
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semiconductor device
stressor layers
layer
formation method
semiconductor
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

The invention discloses a semiconductor device forming method. The method comprises a first step of providing a semiconductor substrate internally doped with N-type or P-type ions, a second step of forming a first stress layer inside the opening located on the surface of the semiconductor substrate, a third step of carrying out doping in the first stress layer and carrying out annealing to form a second stress layer, and a fourth step of forming an intrinsic layer on the surface of the second stress layer, wherein an insulation layer and a protection layer covering the insulation layer are formed on the surface of the semiconductor substrate, an opening penetrates through the protection layer and the insulation layer, and the opening is exposed out of the surface of the semiconductor substrate; the surface of the first stress layer is lower than the surface of the protection layer; the second stress layer is made of Si-Ge-C; and the surface of the intrinsic layer is flush with the surface of the protection layer. According to the semiconductor device forming method disclosed by the embodiment of the invention, performances of the formed semiconductor device are good, N-type or P-type ions inside the semiconductor substrate can be prevented from diffusing upwardly, stress in the groove region of the semiconductor devices is increased, and the carrier mobility is high.

Description

The formation method of semiconductor device
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of semiconductor device.
Background technology
Along with the development of semiconductor process techniques, process node reduces gradually, and rear grid (gate-last) technique is widely applied, and to obtain desirable threshold voltage, improves device performance.But as the characteristic size (CD of device, Critical Dimension) while further declining, even grid technique after adopting, the structure of conventional metal-oxide-semiconductor field effect transistor also cannot meet the demand to device performance, and multiple-grid device is paid close attention to widely as alternative having obtained of conventional device.
Fin field effect pipe (Fin FET) is a kind of common multiple-grid device, and Fig. 1 shows the perspective view of a kind of fin formula field effect transistor of prior art.As shown in Figure 1, comprising: Semiconductor substrate 10, in described Semiconductor substrate 10, be formed with the fin 14 of protrusion, fin 14 is generally by obtaining after Semiconductor substrate 10 etchings; Dielectric layer 11, covers the part of the surface of described Semiconductor substrate 10 and the sidewall of fin 14; Grid structure 12, across on described fin 14, covers top and the sidewall of described fin 14, and grid structure 12 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on gate dielectric layer.For Fin FET, the part that the top of fin 14 and the sidewall of both sides contact with grid structure 12 all becomes channel region, has multiple grid, is conducive to increase drive current, improves device performance.
But, no matter be metal-oxide-semiconductor field effect transistor, or fin field effect pipe, its device performance still has much room for improvement.
More formation methods about semiconductor device, please refer to the United States Patent (USP) that the patent No. is " US7868380B2 ".
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor device, the superior performance of the semiconductor device of formation.
For addressing the above problem, embodiments of the invention provide a kind of formation method of semiconductor device, comprise: the inner Semiconductor substrate doped with N-shaped or p-type ion is provided, described semiconductor substrate surface is formed with insulating barrier and covers the protective layer of described insulating barrier, in described protective layer and insulating barrier, be penetrated with opening, described opening exposes semiconductor substrate surface; In described opening, form the first stressor layers that is positioned at described semiconductor substrate surface, described the first stressor layers surface is lower than described protective layer; Form the second stressor layers to adulterating and anneal in described the first stressor layers, the material of described the second stressor layers is Si-Ge-C; Form intrinsic layer on described the second stressor layers surface, described intrinsic layer surface flushes with described protective layer.
Alternatively, the thickness of described the first stressor layers is less than or equal to 1/2 of the described opening degree of depth.
Alternatively, the formation technique of described the first stressor layers is selective epitaxial depositing operation.
Alternatively, in the time that described semiconductor device is NMOS pipe, the material of described the first stressor layers is carborundum, and the pressure while forming described the first stressor layers is atmospheric pressure, and reaction temperature is 700 degrees Celsius-800 degrees Celsius.
Alternatively, in described the first stressor layers, the molar percentage of carbon is 3%-15%.
Alternatively, be germanium ion or tin ion to the ion adulterating in described the first stressor layers, its process parameters range is: energy is 2 kiloelectron-volts-50 kiloelectron-volts, dosage is 1e15 atomicity/square centimeter-1e16 atomicity/square centimeter.
Alternatively, in the time that described semiconductor device is PMOS pipe, the material of described the first stressor layers is germanium silicon.
Alternatively, in described the first stressor layers, the molar percentage of germanium is 10%-30%.
Alternatively, the thickness of described the first stressor layers is 5 nanometer-30 nanometers.
Alternatively, the method for described annealing is rapid thermal annealing or laser pulse annealing.
Alternatively, the process parameters range of described rapid thermal annealing is: annealing temperature is 900 degrees Celsius-1100 degrees Celsius, annealing time 10 seconds-30 seconds.
Alternatively, the process parameters range of described laser pulse annealing is: annealing temperature is 1200 degrees Celsius-1400 degrees Celsius, 40 milliseconds-100 milliseconds of annealing times.
Alternatively, the material of described intrinsic layer is Si, Si 1-yc yor Si xge1-x, wherein the scope of x is 3%-35%, the scope of y is 10%-30%.
Alternatively, the thickness of described intrinsic layer is 5 nanometer-30 nanometers.
Alternatively, also comprise: form after intrinsic layer, remove described protective layer, expose surface of insulating layer.
Alternatively, in the time that described semiconductor device is fin field effect pipe, also comprise: form across the top of described the second stressor layers and intrinsic layer and the first grid structure of sidewall; Formation is positioned at described first grid structure both sides and is positioned at intrinsic layer and the first source region of the second stressor layers and the first drain region.
Alternatively, in the time that described semiconductor device is metal-oxide-semiconductor, also comprise: form the semiconductor layer that covers described insulating barrier, described semiconductor layer surface and described intrinsic layer flush; After semiconductor layer to be formed, form the second grid structure of the top surface that covers described intrinsic layer; Formation is positioned at the second source region and second drain region of the semiconductor layer of described second grid structure both sides.
Described Semiconductor substrate is silicon substrate or silicon-on-insulator substrate, and the crystal face of described semiconductor substrate surface is (110) or (100).
Compared with prior art, technical scheme of the present invention has the following advantages:
In opening, form the first stressor layers, and adulterate, anneal in described the first stressor layers, formation has the second stressor layers of silicon, germanium, carbon, lattice in described the second stressor layers is arranged and is different from Semiconductor substrate, N-shaped in Semiconductor substrate or p-type ion are difficult for spreading in the second stressor layers, not only stop N-shaped or the p-type ion in Semiconductor substrate upwards to spread, also increased the stress of the channel region of the semiconductor device forming.And, described the second stressor layers surface is formed with intrinsic layer, and described intrinsic layer is as the top of the channel region of semiconductor device, and follow-up charge carrier is mainly by moving in intrinsic layer, further improved the carrier mobility of semiconductor device, the performance of the semiconductor device of formation is good.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the fin field effect pipe of prior art;
Fig. 2-Fig. 8 is the cross-sectional view of the forming process of the semiconductor device of the embodiment of the present invention;
Fig. 9 is the cross-sectional view of the forming process of fin field effect pipe in example 1 of the present invention;
Figure 10 is the cross-sectional view of the forming process of metal-oxide-semiconductor in example 2 of the present invention.
Embodiment
The performance of the semiconductor device that as described in background, prior art forms still has much room for improvement.
Through research, inventor finds, on the one hand, when prior art forms N-shaped or p-type semiconductor device, in Semiconductor substrate conventionally doped with N-shaped or p-type ion, the N-shaped in described Semiconductor substrate or p-type ion be diffusion towards periphery in subsequent technique, when said n type or p-type ion upwards diffuse to channel region, even in grid structure time, easily produce leakage current, affect the performance of semiconductor device; On the other hand, the carrier mobility of channel region is not high enough, also can have influence on the performance of semiconductor device.
After further research, inventor finds, can in channel region, form and suppress knot raceway groove, stop said n type or p-type ion upwards to spread, form stressor layers in bottom, channel region simultaneously, form intrinsic layer at its top near grid structure place, to improve the carrier mobility of semiconductor device.Through further finding, inventor has found a kind of formation method of semiconductor device, both can prevent that said n type or p-type ion from upwards spreading, can improve again the mobility of the charge carrier in semiconductor device channel district, thereby reach the object that improves performance of semiconductor device.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Concrete, please refer to Fig. 2-Figure 10, Fig. 2-Figure 10 shows respectively the cross-sectional view of the forming process of semiconductor device in each example.
Please refer to Fig. 2, the Semiconductor substrate 200 doped with N-shaped or p-type ion is provided, described semiconductor substrate surface is formed with insulating barrier 201.
Described Semiconductor substrate 200 is used to subsequent technique that platform is provided, and described Semiconductor substrate 200 can be monocrystalline silicon (Si) substrate or silicon-on-insulator (SOI) substrate; Or can also be III-V compounds of group such as other material, such as GaAs.The crystal face on described Semiconductor substrate 200 surfaces is (110) or (100).In the present embodiment, the material of described Semiconductor substrate 200 is monocrystalline silicon.
In described Semiconductor substrate 200, doped with N-shaped or p-type ion, specifically determine according to the type of semiconductor device to be formed.In the time that the semiconductor device of follow-up formation is NMOS pipe, described Semiconductor substrate 200 is interior doped with p-type ion, for example boron ion; In the time that the semiconductor device of follow-up formation is PMOS pipe, described Semiconductor substrate 200 is interior for example, doped with N-shaped ion, phosphonium ion.In embodiments of the invention, the fin field effect pipe that the semiconductor device of follow-up formation is N-shaped.Described Semiconductor substrate 200 is interior doped with boron ion.
It should be noted that, to the technique of the interior doped with boron ion of Semiconductor substrate 200, be well known to those skilled in the art, do not repeat them here.
Described insulating barrier 201, for follow-up isolation of semiconductor devices and Semiconductor substrate 200, improves the performance of the semiconductor device forming.The material of described insulating barrier 201 is silica or silicon oxynitride.In an embodiment of the present invention, the material of described insulating barrier 201 is silica, and in subsequent technique, described insulating barrier 201 can also increase the binding ability between protective layer and Semiconductor substrate 200.
The formation technique of described insulating barrier 201 is depositing operation, for example chemical vapor deposition method.The technique that forms insulating barrier 201 due to chemical vapour deposition (CVD) is well known to those skilled in the art, does not repeat them here.
Please refer to Fig. 3, form the protective film (do not indicate) that covers described insulating barrier 201, protective film and insulating barrier 201(are as shown in Figure 2 described in etching), form protective layer 205, insulating barrier 201a and expose the opening 203 of Semiconductor substrate 200.
Described protective layer 205, for subsequent etching technique, protects the Semiconductor substrate 200 of its bottom not to be damaged.The formation step of described protective layer 205 comprises: form the protective film that covers described insulating barrier 201; Formation is positioned at the photoresist layer on described protective film surface, has the figure that exposes part protective film in described photoresist layer; Take described photoresist layer as mask, protective film and insulating barrier 201 described in etching, form the opening 203, protective layer 205 and the insulating barrier 201a that expose Semiconductor substrate 200.In embodiments of the invention, the degree of depth of described opening 203 is 60 nanometers.
Wherein, the material of described protective film is silicon nitride.The formation technique of described protective film is chemical vapor deposition method, does not repeat them here.
It should be noted that, in embodiments of the invention, forming after opening 203, protective layer 205 and insulating barrier 201a, also comprise: remove described photoresist layer.For example, adopt cineration technics to remove described photoresist layer.
Please refer to Fig. 4, be positioned at first stressor layers 207 on described Semiconductor substrate 200 surfaces in the interior formation of described opening 203, described the first stressor layers 207 surfaces are lower than described protective layer 205 surfaces.
Inventor finds, N-shaped in above-mentioned Semiconductor substrate 200 or p-type ion, the speed spreading in semi-conducting material in different crystalline lattice is arranged is not identical, if form carborundum or SiGe in opening 203 bottoms, can effectively stop N-shaped or p-type ion in Semiconductor substrate 200 upwards to spread, and contribute to improve the stress in semiconductor device channel district.
Described the first stressor layers 207 is for the stress of follow-up raising channel region, and stops N-shaped or p-type ion in Semiconductor substrate 200 upwards to spread.The formation technique of described the first stressor layers 207 is depositing operation, for example selective epitaxial depositing operation.The material of described the first stressor layers 207 is relevant with the type of semiconductor device to be formed, and for example, in the time forming NMOS pipe, the material of described the first stressor layers 207 is carborundum, and in the time forming PMOS pipe, the material of described the first stressor layers 207 is germanium silicon.In embodiments of the invention, owing to forming the fin field effect pipe of N-shaped, the material of described the first stressor layers 207 is carborundum.Pressure while forming described the first stressor layers 207 is atmospheric pressure, and reaction temperature is 700 degrees Celsius-800 degrees Celsius.
Inventor's discovery, the ability that in the first stressor layers 207, the stress of the channel region of the NMOS pipe of the content of carbon on follow-up formation and prevention p-type ion upwards spread has larger impact.In the time that the molar percentage of carbon in described the first stressor layers 207 is 3%-15%, the stress of the channel region of the NMOS pipe of follow-up formation is larger, and can effectively stop the p-type ion in Semiconductor substrate 200 upwards to spread.In embodiments of the invention, for making the stress of channel region of fin field effect pipe of N-shaped of follow-up formation larger, in described the first stressor layers 207, the molar percentage of carbon is 10%.
Consider follow-up also will be to described the first stressor layers 207 interior doped germanium (Ge) ion or tin (Sn) ion, to form the second larger stressor layers of thickness, and to form intrinsic layer on the second stressor layers surface, the thickness of described the first stressor layers 207 should be less than or equal to 1/2 of described opening 203 degree of depth.For example, be the opening 203 of 60 nanometers for the degree of depth in embodiments of the invention, the thickness of described the first stressor layers 207 is less than or equal to 30 nanometers, preferably, is 5 nanometer-30 nanometers.
It should be noted that, in the time that described semiconductor device is PMOS pipe, the material of described the first stressor layers is germanium silicon.And, for improving the stress of channel region of PMOS pipe, improving its carrier mobility, in described the first stressor layers 207, the molar percentage of germanium is 10%-30%.
Please refer to Fig. 5, to the interior doped germanium ion of described the first stressor layers 207, tin ion or carbon ion, form first stressor layers 208 with described germanium ion, tin ion or carbon ion;
To the described germanium ion of the interior doping of described the first stressor layers 207, tin ion or carbon ion, further to stop N-shaped or p-type ion in Semiconductor substrate 200 upwards to spread.In the time forming NMOS pipe, to the interior doped germanium ion of described the first stressor layers 207 or tin ion; In the time forming PMOS pipe, to the interior doped germanium ion of described the first stressor layers 207.In embodiments of the invention, owing to forming the fin field effect pipe of N-shaped, be germanium ion or tin ion to the ion of described the first stressor layers 207 interior doping.
For making germanium ion or the follow-up similar diffusion that both can play the interior p-type ion of prevention Semiconductor substrate 200 of tin ion of doping, can not have a negative impact to the stress of the fin field effect pipe channel region of N-shaped again.Process parameters range during to the interior doped germanium ion of described the first stressor layers 207 or tin ion is: energy is 2 kiloelectron-volts-50 kiloelectron-volts, and dosage is 1e15 atomicity/square centimeter-1e16 atomicity/square centimeter.Make the mole percent level of the germanium ion that comprises in the first stressor layers 208 or tin ion be less than the mole percent level of carbon.In embodiments of the invention, the technological parameter during to the interior doped germanium ion of described the first stressor layers 207 or tin ion is: energy is 20 kiloelectron-volts, and dosage is 1e15 atomicity/square centimeter.
It should be noted that, in the time forming PMOS pipe, can be to doping carbon ion in the first stressor layers 207, technological parameter when its technological parameter is managed with above-mentioned formation NMOS is identical, does not repeat them here.
It should be noted that, in other embodiments of the invention, in the time forming NMOS pipe, can also first form material is the first stressor layers 207 of germanium silicon, follow-up is doping carbon ion in the first stressor layers 207 of germanium silicon to material, as long as the mole percent level of the first stressor layers 208 interior carbon after doping is greater than the mole percent level of germanium or tin; In like manner, in the time forming PMOS pipe, also can first form material is the first stressor layers 207 of carborundum, follow-up to doped germanium ion or tin ion in the first stressor layers 207 of described carborundum, as long as the mole percent level of the first stressor layers 208 interior germanium after doping is greater than the mole percent level of carbon or tin.
Please refer to Fig. 6, to doping after the first stressor layers 208(as shown in Figure 5) anneal, form the second stressor layers 209.
For above-mentioned germanium ion, tin ion or carbon ion are evenly distributed in the first stressor layers 208, strengthen the ability that it stops N-shaped in Semiconductor substrate 200 or p-type ion upwards to spread, the first stressor layers 208 after described doping is annealed, for example rapid thermal anneal process (RTA) or laser pulse annealing (LTA), form the second stressor layers 209.The material of described the second stressor layers 209 is Si-Ge-C.
In an example of the present invention, adopt rapid thermal anneal process, its process parameters range is: annealing temperature is 900 degrees Celsius-1100 degrees Celsius, annealing time 10 seconds-30 seconds, being evenly distributed of the interior germanium of the second stressor layers 209, the silicon that form, carbon, follow-uply stop that p-type ion is by diffusion effective upwards in Semiconductor substrate 200, and effectively increased the stress of the channel region of NMOS pipe.
In another example of the present invention, adopt laser pulse annealing process, its process parameters range is: annealing temperature is 1200 degrees Celsius-1400 degrees Celsius, 40 milliseconds-100 milliseconds of annealing times.Except having the above-mentioned advantage of rapid thermal anneal process, and the speed of laser pulse annealing process is faster, and efficiency is high, better effects if.
It should be noted that, during due to aforementioned doping ion to the first stressor layers 207(as shown in Figure 4) bombardment effect, doping after form the first stressor layers 208 be amorphousness.Therefore, above-mentioned annealing process is in fact the first stressor layers 208 process of crystallization again.Under above-mentioned annealing process, silicon, carbon, germanium by amorphous state shrink, crystallization forms the second stressor layers 209 again, the top shape of the second stressor layers 209 forming is arch, the follow-up intrinsic layer to its top of the second stressor layers 209 of described arch has stronger stress, more contributes to the stress of the channel region of improving semiconductor device.
Please refer to Fig. 7, form intrinsic layer 211 on described the second stressor layers 209 surfaces, described intrinsic layer 211 surfaces and described protective layer 205 flush.
Inventor finds, when the material in the top channel district of semiconductor device be pure, during containing the semi-conducting material of doping ion, be more conducive to improve the carrier mobility of its channel region.Therefore,, in embodiments of the invention, form intrinsic layer 211 on described the second stressor layers 209 surfaces.
Described intrinsic layer 211 is for the stress of the channel region of follow-up raising semiconductor device, to improve its carrier mobility.The material of described intrinsic layer 211 is Si, Si1-yCy or SixGe1-x, and wherein the scope of x is 3%-35%, and the scope of y is 10%-30%, to obtain the semiconductor device that carrier mobility is high.In an embodiment of the present invention, the material of described intrinsic layer 211 is SixGe1-x, and wherein x is 10%-20%, and the stress of the channel region of the semiconductor device of follow-up formation is larger, and carrier mobility is high.
The formation technique of described intrinsic layer 211 is depositing operation.In an embodiment of the present invention, for saving processing step, described intrinsic layer 211 adopts selective epitaxial depositing operation to form.
In addition, inventor's discovery, when semiconductor device work, charge carrier is mainly in the migration of top, channel region, and described intrinsic layer 211 should mainly be positioned at the region at top, above-mentioned channel region.In embodiments of the invention, the thickness of described intrinsic layer 211 is 5 nanometer-30 nanometers, and the carrier mobility of the channel region of the semiconductor device of formation is high.
Please refer to Fig. 8, after intrinsic layer 211 to be formed, remove described protective layer 205(as shown in Figure 7), expose insulating barrier 201a surface.
Remove described protective layer 205, expose insulating barrier 201a surface, be beneficial to follow-up formation metal-oxide-semiconductor or fin field effect pipe.The technique of described removal protective layer 205 is etching technics, because the technique of removing described protective layer 205 is well known to those skilled in the art, does not repeat them here.
It should be noted that, the kind difference of the semiconductor device of formation, follow-up formation technique is not identical yet.Carry out exemplary illustrated by two examples below.
Example 1
In example 1 of the present invention, the follow-up fin field effect pipe that is used to form.Please refer to Fig. 9, form across described the second stressor layers 209 and the top of intrinsic layer 211 and the first grid structure of sidewall (not indicating); Formation is positioned at described first grid structure both sides and is positioned at intrinsic layer 211 and the first source region of the second stressor layers 209 (not indicating) and the first drain region (not indicating).
Wherein, the formation step of described first grid structure comprises: form across the top of described the second stressor layers 209 and intrinsic layer 211 and the first grid dielectric layer 213a of sidewall; Form the first grid electrode layer 215a that covers described first grid dielectric layer 213a.The material of described first grid dielectric layer 213a is silica or high K dielectric, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium oxide tantalum, hafnium oxide titanium, hafnium oxide zirconium etc.The material of described first grid electrode layer 215a is polysilicon or metal material, such as tungsten, aluminium etc.
After above-mentioned steps completes, the completing of the fin field effect pipe of example 1 of the present invention.Described the second stressor layers 209 and intrinsic layer 211 form the fin of fin field effect pipe, the bottom, channel region of the fin field effect pipe forming has the second stressor layers 209, top, channel region has intrinsic layer 211, effectively stop N-shaped or p-type ion in Semiconductor substrate 200 upwards to spread, and the stress of the channel region of the fin field effect pipe forming is large, and carrier mobility is high.
Example 2
In example 2 of the present invention, the semiconductor device of formation is metal-oxide-semiconductor.Please refer to Figure 10, form the semiconductor layer 220 that covers described insulating barrier 201a, described semiconductor layer 220 surfaces and described intrinsic layer 211 flush; After semiconductor layer 220 to be formed, form the second grid structure (not indicating) of the top surface that covers described intrinsic layer 211; Formation is positioned at the second source region (not shown) and the second drain region (not shown) of the semiconductor layer 220 of described second grid structure both sides.
Described semiconductor layer 220 is for the second source region and second drain region of follow-up formation metal-oxide-semiconductor.The formation technique of described semiconductor layer 220 is depositing operation.The material of described semiconductor layer 220 is identical with the material of Semiconductor substrate 200, is monocrystalline silicon.
The formation step of described second grid structure comprises: the second gate dielectric layer 213b that forms the top surface that covers described intrinsic layer 211; Form the second gate electrode layer 215b that covers described second gate dielectric layer 213b surface; Be positioned at described second gate dielectric layer 213b and second gate electrode layer 215b sidewall and be positioned at the side wall 217 on described semiconductor layer 220 surfaces.The material of described second gate dielectric layer 213b and second gate electrode layer 215b, please refer to first grid dielectric layer 213a(in example 1 of the present invention as shown in Figure 9), first grid electrode layer 215a(as shown in Figure 9) material, do not repeat them here.
After above-mentioned steps completes, the completing of the metal-oxide-semiconductor of example 2 of the present invention.Described the second stressor layers 209 and intrinsic layer 211 are still positioned at the channel region of metal-oxide-semiconductor, can play equally the N-shaped or the p-type ion that stop in Semiconductor substrate 200 and upwards spread, and improve the stress of the channel region of metal-oxide-semiconductor, the effect that improves its carrier mobility.
To sum up, in opening, form the first stressor layers, and adulterate, anneal in described the first stressor layers, formation has the second stressor layers of silicon, germanium, carbon, lattice in described the second stressor layers is arranged and is different from Semiconductor substrate, N-shaped in Semiconductor substrate or p-type ion are difficult for spreading in the second stressor layers, have not only stoped N-shaped or the p-type ion in Semiconductor substrate upwards to spread, and have also increased the stress of the channel region of the semiconductor device forming.And, described the second stressor layers surface is formed with intrinsic layer, and described intrinsic layer is as the top of the channel region of semiconductor device, and follow-up charge carrier is mainly by moving in intrinsic layer, further improved the carrier mobility of semiconductor device, the performance of the semiconductor device of formation is good.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (18)

1. a formation method for semiconductor device, is characterized in that, comprising:
The inner Semiconductor substrate doped with N-shaped or p-type ion is provided, and described semiconductor substrate surface is formed with insulating barrier and covers the protective layer of described insulating barrier, in described protective layer and insulating barrier, is penetrated with opening, and described opening exposes semiconductor substrate surface;
In described opening, form the first stressor layers that is positioned at described semiconductor substrate surface, described the first stressor layers surface is lower than described protective layer;
Form the second stressor layers to adulterating and anneal in described the first stressor layers, the material of described the second stressor layers is Si-Ge-C;
Form intrinsic layer on described the second stressor layers surface, described intrinsic layer surface flushes with described protective layer.
2. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the thickness of described the first stressor layers is less than or equal to 1/2 of the described opening degree of depth.
3. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the formation technique of described the first stressor layers is selective epitaxial depositing operation.
4. the formation method of semiconductor device as claimed in claim 3, it is characterized in that, in the time that described semiconductor device is NMOS pipe, the material of described the first stressor layers is carborundum, pressure while forming described the first stressor layers is atmospheric pressure, and reaction temperature is 700 degrees Celsius-800 degrees Celsius.
5. the formation method of semiconductor device as claimed in claim 4, is characterized in that, in described the first stressor layers, the molar percentage of carbon is 3%-15%.
6. the formation method of semiconductor device as claimed in claim 4, it is characterized in that, be germanium ion or tin ion to the ion adulterating in described the first stressor layers, its process parameters range is: energy is 2 kiloelectron-volts-50 kiloelectron-volts, and dosage is 1e15 atomicity/square centimeter-1e16 atomicity/square centimeter.
7. the formation method of semiconductor device as claimed in claim 3, is characterized in that, in the time that described semiconductor device is PMOS pipe, the material of described the first stressor layers is germanium silicon.
8. the formation method of semiconductor device as claimed in claim 7, is characterized in that, in described the first stressor layers, the molar percentage of germanium is 10%-30%.
9. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the thickness of described the first stressor layers is 5 nanometer-30 nanometers.
10. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the method for described annealing is rapid thermal annealing or laser pulse annealing.
The formation method of 11. semiconductor device as claimed in claim 10, is characterized in that, the process parameters range of described rapid thermal annealing is: annealing temperature is 900 degrees Celsius-1100 degrees Celsius, annealing time 10 seconds-30 seconds.
The formation method of 12. semiconductor device as claimed in claim 10, is characterized in that, the process parameters range of described laser pulse annealing is: annealing temperature is 1200 degrees Celsius-1400 degrees Celsius, 40 milliseconds-100 milliseconds of annealing times.
The formation method of 13. semiconductor device as claimed in claim 1, is characterized in that, the material of described intrinsic layer is Si, Si 1-yc yor Si xge 1-x, wherein the scope of x is 3%-35%, the scope of y is 10%-30%.
The formation method of 14. semiconductor device as claimed in claim 1, is characterized in that, the thickness of described intrinsic layer is 5 nanometer-30 nanometers.
The formation method of 15. semiconductor device as claimed in claim 1, is characterized in that, also comprises: form after intrinsic layer, remove described protective layer, expose surface of insulating layer.
The formation method of 16. semiconductor device as claimed in claim 15, is characterized in that, in the time that described semiconductor device is fin field effect pipe, also comprises: form across the top of described the second stressor layers and intrinsic layer and the first grid structure of sidewall; Formation is positioned at described first grid structure both sides and is positioned at intrinsic layer and the first source region of the second stressor layers and the first drain region.
The formation method of 17. semiconductor device as claimed in claim 15, is characterized in that, in the time that described semiconductor device is metal-oxide-semiconductor, also comprises: form the semiconductor layer that covers described insulating barrier, described semiconductor layer surface and described intrinsic layer flush; After semiconductor layer to be formed, form the second grid structure of the top surface that covers described intrinsic layer; Formation is positioned at the second source region and second drain region of the semiconductor layer of described second grid structure both sides.
The formation method of 18. semiconductor device as claimed in claim 1, is characterized in that, described Semiconductor substrate is silicon substrate or silicon-on-insulator substrate, and the crystal face of described semiconductor substrate surface is (110) or (100).
CN201210406255.9A 2012-10-22 2012-10-22 Semiconductor device forming method Pending CN103779221A (en)

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CN105742336A (en) * 2014-12-08 2016-07-06 中芯国际集成电路制造(上海)有限公司 Method for forming stress structure
CN106571335A (en) * 2015-10-12 2017-04-19 中芯国际集成电路制造(上海)有限公司 Fin type field effect transistor forming method

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Application publication date: 20140507