CN103809958A - Method for improving numerical value comparison efficiency of processor and numerical value comparison processor - Google Patents
Method for improving numerical value comparison efficiency of processor and numerical value comparison processor Download PDFInfo
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- CN103809958A CN103809958A CN201210548321.6A CN201210548321A CN103809958A CN 103809958 A CN103809958 A CN 103809958A CN 201210548321 A CN201210548321 A CN 201210548321A CN 103809958 A CN103809958 A CN 103809958A
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Abstract
The invention relates to a method for improving the numerical value comparison efficiency of a processor and a numerical value comparison processor, wherein the processor mainly comprises a data memory, a comparison unit and an instruction unit; the data memory temporarily stores a plurality of groups of rewritable critical values, the processor reads the critical values of the data memory after receiving the digital values to be detected output by the electronic device, the critical values of the data memory are directly compared with the digital values to be detected, comparison codes are output, and then the instruction unit executes corresponding program functions according to the comparison codes; therefore, the processor does not need to gradually and slowly judge the magnitude relation between the digital value to be detected and the preset critical value in sequence by using a firmware program, and the processing efficiency can be improved.
Description
Technical field
The present invention relates to the technology that a kind of processor detects digital numerical value scope, particularly a kind of numeric ratio that promotes processor is compared with efficiency method and be applied to the numerical value comparator processor of electronic installation.
Background technology
As shown in Figure 5, for processor 10 carries out numeric ratio flow process with firmware, first this processor 10 stores scale value and a subscript value on one in datarams 11, when receiving after the digital numerical value to be detected of outside input, be stored in the lump this datarams 11 (S50), in the time that these processor 10 these numerical ranges of execution compare flow process, the arithmetic logic unit 30 of this 8 bit first reads the FD0H of most-significant byte unit of digital numerical value FD0 to be detected and the first AH of the most-significant byte of scale value on this compare (S51) from datarams 11, if while being greater than (FD0H>AH), represent that this digital numerical value FD0 to be measured is higher than upper scale value, and execution corresponding function program A (S511), if be not more than, further judge whether to equal (FD0H=AH) (S52), if unequal, represent that this digital numerical value FD0 to be measured is not greater than the possibility of scale value, if equate, further read the FD0L of least-significant byte unit of digital numerical value to be detected and the first AL of the least-significant byte of upper scale value compare (S53), if be greater than (FD0L>AL), represent equally that this digital numerical value FD0 to be measured is higher than upper scale value, and carry out corresponding function program A (S511), if be not more than, represent that this digital numerical value FD0 to be measured is not greater than the possibility of scale value.
When this digital numerical value FD0 to be measured is not greater than the possible of upper scale value, the FD0H of most-significant byte unit that will then read digital numerical value to be detected compares the most-significant byte BH of unit (S54) of this subscript value, if while being less than (FD0H<BH), represent that this digital numerical value FD0 to be measured is lower than subscript value, and carry out corresponding function program B (S541); If be not less than, further judge whether to equate (S55); If unequal, represent that digital numerical value FD0 to be detected is between upper and lower scale value, therefore carry out corresponding function program C (S551); If equate (FD0H=BH), read the FD0L of least-significant byte unit of digital numerical value to be detected and the first BL of the least-significant byte of subscript value compare (S56), if be less than (FD0L<BL), represent equally that this digital numerical value FD0 to be measured is lower than subscript value, and carry out corresponding function program B (S541).If the FD0H of the most-significant byte of digital numerical value to be detected unit is not less than the BL of most-significant byte unit of this subscript value, represent that digital numerical value FD0 to be detected is between upper and lower scale value, therefore carry out corresponding function program C (S551).
The procedure code of corresponding this flow process is further provided below:
Processor is carried out this numeric ratio to flow process at present, judge that for need digital numerical value to be detected falls into the result between upper scale value and subscript value, if judged with firmware program merely, the minimum said procedure code that needs can be realized, if be applied to the more judgement of multiple digital numerical range, the required judgement time increases relatively, and often processor must could be carried out alignment processing or control program according to result after judged result occurs, if therefore elongate the judgement time, certainly will also cause processor respective handling or control insensitive, and be necessary to improve for numerical range detection efficiency for processor.
Summary of the invention
For above-mentioned technical disadvantages, fundamental purpose of the present invention is to provide a kind of numeric ratio that promotes processor compared with efficiency method and is applied in electronic installation carries out numerical value comparator processor.
Want to reach above-mentioned purpose, the technical way using is to make the numeric ratio of this lifting processor include compared with efficiency method:
Receive a digital numerical value to be detected;
Utilize a comparing unit to this numerical value to be detected and organize preset critical more to compare, and output comparison code; And
Carry out corresponding program function according to comparison code.
As preferably, above-mentioned many group critical values and comparison code are all temporarily stored in the datarams of processor, and wherein many group critical values can be rewritten.
As preferably, wherein the bit number of this comparison code is less than the bit number of digital numerical value to be detected.
As preferably, the default two groups of critical values of this comparing unit are respectively subscript numerical value and subscript numerical value, each critical value bit number is identical with the bit number of digital numerical value to be detected, and this comparing unit includes three groups of input ends, to receive side by side respectively digital numerical value to be detected and upper and lower mark numerical value, and include two output terminals, represent to compare code with two bits.
As preferably, above-mentioned comparing unit output comparison code steps includes:
From datarams read the high bit of digital numerical value to be detected and on this high bit of scale value compare; If while being greater than, represent that this digital numerical value to be measured is higher than upper scale value, and output the first comparison code, and be stored in datarams;
If the high bit of digital numerical value to be detected is not more than the high bit of scale value on this, further judge whether the two equates;
If unequal, represent that this digital numerical value to be measured is not greater than the possibility of scale value;
If equate, further read the low bit of digital numerical value to be detected and the low bit of upper scale value is compared;
If the low bit of digital numerical value to be detected is greater than the low bit of scale value, this digital numerical value to be measured, higher than upper scale value, is compared code and export first, and is stored in datarams; If be not more than, this digital numerical value to be measured is not greater than the possibility of scale value;
Read the high bit of digital numerical value to be detected and the high bit of this subscript value is compared; If while being less than, representing that this digital numerical value to be measured is lower than subscript value, and produce the second comparison code, and be stored to datarams; Otherwise, further compare the two and whether equate;
If unequal, represent that this digital numerical value to be measured drops between scale value and subscript value, and produce the 3rd comparison code;
If equate, further read the low bit of digital numerical value to be detected and the low bit of subscript value is compared;
If the low bit of digital numerical value to be detected is less than the low bit of subscript value, represents that this digital numerical value to be measured is lower than subscript value, and produce the second comparison code; If be not less than, represent that this digital numerical value to be measured drops between scale value and subscript value, and produce the 3rd comparison code.
As preferably, the above-mentioned step of carrying out corresponding function program according to comparison code includes:
Store the multibank capability program of corresponding comparison code in the program internal memory of processor;
Comparison code is added to the programmable counter of processor, obtain a new address, to point to and to carry out the function program of new address in this program internal memory.
Moreover the present invention is applied in electronic installation and carries out numerical value comparator processor and include:
One datarams, stores many group critical values;
One comparing unit, connect this electronic installation and receive the numeral digital numerical value to be detected of its output, and this comparing unit connects this datarams to read many group critical values, and this numeral digital numerical value to be detected is compared, and is stored to this datarams after output comparison code; And
One command unit, connects this datarams, reads this comparison code and carries out corresponding function program according to this comparison code.
As preferably, many groups critical value that this datarams stores can be rewritten.
The invention described above is mainly at the inner newly-increased comparing unit being made up of hardware circuit of processor, this comparing unit first in datarams, reads digital numerical value to be measured and critical value is compared, because comparing unit is hardware circuit, therefore can produce rapidly comparison code, make this command unit directly carry out corresponding function program according to this comparison code; Therefore, processor needn't sequentially and step by step be compared this digital numerical value to be measured and critical value with firmware program again, and can promote processor than the treatment effeciency of logarithm value.
Accompanying drawing explanation
Fig. 1 is the functional flow diagram of processor of the present invention.
Fig. 2 A is the signal wiring schematic diagram of comparing unit of the present invention.
Fig. 2 B is the logical flow chart of comparing unit of the present invention.
Fig. 3 is the process flow diagram that the present invention promotes the digital numerical value range detection efficiency method of processor:
Fig. 4 is the functional flow diagram of existing processor.
Fig. 5 is the process flow diagram of the digital numerical value range detection method of existing processor.
Main element symbol description
10,10a processor 11 datarams
12 arithmetic logical unit 121 totalizers
20 comparing unit 30 command units
31 program internal memory 32 instruction registors
33 instruction decoder 34 programmable counters.
Embodiment
First referring to shown in Fig. 1, is processor 10a mono-functional flow diagram of the present invention, and it consists predominantly of a datarams 11, a comparing unit 20 and a command unit 30; Wherein: this comparing unit 20 is connected with this datarams 11 and this command unit 30 with data bus.Above-mentioned datarams 11 can be written into and store many group critical values, and wherein this many groups critical value can be rewritten, and receives in processor 10a after the digital numerical value to be detected of outside input, is kept in this digital numerical value to be detected.
When processor 10a receives after digital numerical value to be detected, this comparator circuit 20 reads this digital numerical value to be detected and organizes critical value more from datarams 11, because this comparator circuit 20 is hardware circuit, therefore this digital numerical value to be detected can be carried out fast size with many groups critical value and compared, and then produces and store a comparison code.
Now, command unit 30 by data bus reads comparison code (2 bit) that comparator circuit 20 produce equally, and carry out corresponding function program according to this comparison code; Particularly, this command unit 30 coordinates an arithmetic logical unit 12 and a totalizer 121 of this processor 10a, the programmable counter of command unit 30 34 is directly added to the comparison code of 2 bits, to produce new destination address, make program internal memory 31, instruction registor 32 and the instruction decoder 33 of command unit point to and jump (JUMP) to the new destination address of this program internal memory 31, to carry out the stored function program A in this new address, B or C.Detailed procedure code is as follows:
Therefore, compare judgement with program (firmware) completely with respect to existing processor, except reducing 25 instruction times, also reduce the storage volume that occupies program internal memory 31.
As shown in Figure 2 A and 2 B, suppose to receive digital numerical value to be detected (HD0) and upper scale value FD0GT, subscript value FD0LT, to export and to store comparison code as 16 carries, and the most group critical values of comparing unit 20 default two (upper scale value FD0GT, subscript value DF0LT); Equal 16 carries), to define three sensing ranges, therefore this comparing unit 20 includes 48 input pins altogether, and is three sensing ranges of reaction, therefore includes 2 output connecting pins; Wherein comparing that code orders is temporarily 00,01,10; Wherein this comparing unit 20 is realized following comparison step with hardware circuit: firmware
Read the HD0H of most-significant byte unit of digital numerical value HD0 to be detected and the first FD0GTH of the most-significant byte of scale value FD0GT on this compare (S21) from datarams 11, if while being greater than (HD0H>FD0GTH), represent that this digital numerical value HD0 to be measured is higher than upper scale value FD0GT, and output comparison code 10, and be stored in the address FD0WC of datarams 11; If be not more than, further judge whether the two equates (S22); If unequal, represent that this digital numerical value HD0 to be measured is not greater than the possibility of scale value FD0GT; If equate (HD0H=FD0GTH), further read the HD0L of least-significant byte unit of digital numerical value to be detected and the first FD0GTL of the least-significant byte of upper scale value compare (S23), if be greater than (HD0L>FD0GTL), represent equally that this digital numerical value HD0 to be measured is higher than upper scale value FD0GT, and output comparison code 10, and be stored in the address FD0WC of datarams 11; If be not more than, represent that this digital numerical value HD0 to be measured is not greater than the possibility of scale value FD0GT.Do not exist
When this digital numerical value HD0 to be measured is not greater than the possible of upper scale value FD0GT, then carry out size ratio with subscript value FD0LT, the HD0H of most-significant byte unit that reads digital numerical value to be detected compares the most-significant byte FD0LTH of unit (S24) of this subscript value, if while being less than (HD0H<FD0LTH), represent that this digital numerical value HD0 to be measured is lower than subscript value FD0LT, and produce comparison code 01, and be stored in the position FD0WC of datarams; Otherwise, further compare the two and whether equate (S25); If be not equal to, represent that this digital numerical value HD0 to be measured drops between scale value and subscript value, and produce comparison code 00; If equate (HD0H=FD0LTH), further read the HD0L of least-significant byte unit of digital numerical value to be detected and the first FD0LTL of the least-significant byte of subscript value compare (S26), if be less than (HD0L<FD0LTL), represent that this digital numerical value FD0 to be measured is lower than subscript value, and produce comparison code 01; Otherwise, represent that this digital numerical value HD0 to be measured drops between scale value and subscript value, and produce comparison code 00.
As shown in Figure 3, processor 10a judges the workflow of its sensing range to outside numerical value to be detected, first by array critical value FD0GT, FD0LT is stored in 11 (S10) in the datarams of processor 10a, when after the numerical value input to be detected of outside, this comparing unit 20 receives digital numerical value HD0 to be detected (S11), and the array critical value FD0GT of reading out data internal memory 11, FD0LT, compare digital numerical value HD0 to be detected compared with array critical value FD0GT with hardware structure, FD0LT is large or little, and output and storage comparison code (S12), now just by command unit 30, comparison code is added to the current address of programmable counter 34, produce a new destination locations, point to and carry out the function program of this destination address, if take Fig. 2 B as illustration, when comparison code is 00 (S13), carry out the function program C (S131) of these programmable counter 34 current indication program addresses, if comparison code is 01 (S14), carry out the function program B (S141) that these programmable counter 34 current indication program addresses add 1 destination address, if this comparison code is 10 (S15) in addition, carry out the function program A (S151) that the current indication program point of this programmable counter 34 adds 2 destination address, these three sections of function program A ~ C are stored in program internal memory 31.
Hence one can see that, and the numeric ratio that the present invention promotes processor, utilizes a comparing unit to this digital numerical value to be detected and organize preset critical more to compare compared with efficiency method after receiving a digital digital numerical value to be detected, and output comparison code; Make the command unit of processor carry out corresponding function program according to comparison code again.
In sum, the present invention is mainly in the inner newly-increased comparing unit being made up of hardware circuit of processor, this comparing unit can be inputted many group critical values, compare with the digital numerical value to be measured of changing and exporting with this interface circuit, because comparing unit is hardware circuit, therefore can produce rapidly comparison code, make this arithmetic logic unit needn't progressively sequentially judge again the sensing range of this digital numerical value to be measured with program, and the direct basis comparison corresponding program address of code, and directly carry out this function program; Thus, judge that with firmware program sensing range is quicker with respect to existing processor, and promote the treatment effeciency of processor; Moreover, if above-mentioned processor is for the circuit of the sensing range that detects external signal as regular in the needs such as contactor control device, input, after long-time execution, because the procedure code of processor of the present invention effectively reduces with respect to existing processor, therefore the consumed power of processor will be contributed to reduce.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the claims in the present invention scope change and modify, and all should belong to the covering scope of the claims in the present invention.
Claims (8)
1. promote the numeric ratio of processor compared with an efficiency method, include:
Receive a digital numerical value to be detected;
Utilize a comparing unit to this digital numerical value to be detected and organize preset critical more to compare, and output comparison code; And
Carry out corresponding function program according to comparison code.
2. the method for claim 1, above-mentioned many group critical values and comparison code are all temporarily stored in the datarams of processor, and wherein many group critical values can be rewritten.
3. method as claimed in claim 1 or 2, wherein the bit number of this comparison code is less than the bit number of digital numerical value to be detected.
4. method as claimed in claim 3, the default two groups of critical values of this comparing unit are respectively subscript numerical value and subscript numerical value, each critical value bit number is identical with the bit number of digital numerical value to be detected, and this comparing unit includes three groups of input ends, to receive side by side respectively digital numerical value to be detected and upper and lower mark numerical value, and include two output terminals, represent to compare code with two bits.
5. method as claimed in claim 4, above-mentioned comparing unit output comparison code steps includes:
From datarams read the high bit of digital numerical value to be detected and on this high bit of scale value compare; If while being greater than, represent that this digital numerical value to be measured is higher than upper scale value, and output the first comparison code, and be stored in datarams;
If the high bit of digital numerical value to be detected is not more than the high bit of scale value on this, further judge whether the two equates;
If unequal, represent that this digital numerical value to be measured is not greater than the possibility of scale value;
If equate, further read the low bit of digital numerical value to be detected and the low bit of upper scale value is compared;
If the low bit of digital numerical value to be detected is greater than the low bit of scale value, this digital numerical value to be measured, higher than upper scale value, is compared code and export first, and is stored in datarams; If be not more than, this digital numerical value to be measured is not greater than the possibility of scale value;
Read the high bit of digital numerical value to be detected and the high bit of this subscript value is compared; If while being less than, representing that this digital numerical value to be measured is lower than subscript value, and produce the second comparison code, and be stored to datarams; Otherwise, further compare the two and whether equate;
If unequal, represent that this digital numerical value to be measured drops between scale value and subscript value, and produce the 3rd comparison code;
If equate, further read the low bit of digital numerical value to be detected and the low bit of subscript value is compared;
If the low bit of digital numerical value to be detected is less than the low bit of subscript value, represents that this digital numerical value to be measured is lower than subscript value, and produce the second comparison code; If be not less than, represent that this digital numerical value to be measured drops between scale value and subscript value, and produce the 3rd comparison code.
6. method as claimed in claim 5, the step that above-mentioned foundation comparison code is carried out corresponding function program includes:
Store the multibank capability program of corresponding comparison code at the program internal memory of processor;
Comparison code is added to the programmable counter of processor, obtain a new address, to point to and to carry out the function program of new address in this program internal memory.
7. a numerical value comparator processor that is applied to electronic installation, includes:
One datarams, stores many group critical values;
One comparing unit, connect this electronic installation and receive the digital numerical value to be detected of its output, and this comparing unit connects this datarams to read many group critical values, and this digital numerical value to be detected is compared, and is stored to this datarams after output comparison code; And
One command unit, connects this datarams, reads this comparison code and carries out corresponding program function according to this comparison code.
8. a kind of numerical value comparator processor that is applied to electronic installation as claimed in claim 7, many groups critical value that this datarams stores can be rewritten.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101140954 | 2012-11-05 | ||
| TW101140954A TWI607375B (en) | 2012-11-05 | 2012-11-05 | Numerical comparing method of a processor and the processor applied to an electronic device |
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| CN103809958A true CN103809958A (en) | 2014-05-21 |
| CN103809958B CN103809958B (en) | 2017-08-18 |
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| US5123108A (en) * | 1989-09-11 | 1992-06-16 | Wang Laboratories, Inc. | Improved cpu pipeline having register file bypass and working register bypass on update/access address compare |
| US5253349A (en) * | 1991-01-30 | 1993-10-12 | International Business Machines Corporation | Decreasing processing time for type 1 dyadic instructions |
| US20020083108A1 (en) * | 2000-12-27 | 2002-06-27 | Tierno Jose A. | Method and apparatus for comparing two binary numbers with a power-of-two threshold |
| CN1466715A (en) * | 2000-09-28 | 2004-01-07 | ض� | Array search operation |
| TW200705255A (en) * | 2005-04-15 | 2007-02-01 | Intel Corp | Ring management |
| CN102109980A (en) * | 2009-12-22 | 2011-06-29 | 英特尔公司 | Methods and apparatus for performing adaptive pre-fetch operations in managed runtime environments |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI505104B (en) * | 2010-11-03 | 2015-10-21 | Inventec Corp | Controlling method for baseboard management controller with customization sensor data record |
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2012
- 2012-11-05 TW TW101140954A patent/TWI607375B/en active
- 2012-12-17 CN CN201210548321.6A patent/CN103809958B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5123108A (en) * | 1989-09-11 | 1992-06-16 | Wang Laboratories, Inc. | Improved cpu pipeline having register file bypass and working register bypass on update/access address compare |
| US5253349A (en) * | 1991-01-30 | 1993-10-12 | International Business Machines Corporation | Decreasing processing time for type 1 dyadic instructions |
| CN1466715A (en) * | 2000-09-28 | 2004-01-07 | ض� | Array search operation |
| US20020083108A1 (en) * | 2000-12-27 | 2002-06-27 | Tierno Jose A. | Method and apparatus for comparing two binary numbers with a power-of-two threshold |
| TW200705255A (en) * | 2005-04-15 | 2007-02-01 | Intel Corp | Ring management |
| CN102109980A (en) * | 2009-12-22 | 2011-06-29 | 英特尔公司 | Methods and apparatus for performing adaptive pre-fetch operations in managed runtime environments |
Also Published As
| Publication number | Publication date |
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| CN103809958B (en) | 2017-08-18 |
| TWI607375B (en) | 2017-12-01 |
| TW201419137A (en) | 2014-05-16 |
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