CN103810054A - Error checking and correcting methods and related error checking and correcting circuit - Google Patents
Error checking and correcting methods and related error checking and correcting circuit Download PDFInfo
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- CN103810054A CN103810054A CN201210455619.2A CN201210455619A CN103810054A CN 103810054 A CN103810054 A CN 103810054A CN 201210455619 A CN201210455619 A CN 201210455619A CN 103810054 A CN103810054 A CN 103810054A
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Abstract
The invention provides an error checking and correcting method, which comprises the following steps of compressing an original data packet, and generating a compressed data packet; determining a correcting code length according to a data length; performing error checking and correcting coding on packet data to generate a correcting code according to the correcting code length; combining the packet data and the correcting code to form a coded data packet. The invention also provides another error checking and correcting method, which comprises the following steps of reading the coded data packet, wherein the coded data packet comprises the packet data and the correcting code, and the packet data comprises the compressed data packet; performing error checking and correcting decoding on the packet data according to the correcting code, and generating a decoded compressed data packet corresponding to the compressed data packet; decompressing the decoded compressed data packet to generate a decompressed data packet.
Description
Technical field
The disclosed embodiment of the present invention system is relevant to bug check and correction, espespecially a kind of bug check and bearing calibration and relevant error inspection and correcting circuit that decides correcting code length according to data length.
Background technology
Error-correcting code (Error Correcting Code, ECC) be a kind of known debug technology, can be applicable on storer, for example, in Sheffer stroke gate flash memory (NAND flash), this debug technology is used for checking that whether be sent to the data of storer correct.System can, in the time transmitting data data, for instance, be that 8 bit data add the extra same bit code of 1 bit (parity code) to be used as correcting code.When data occur that when wrong, bug check and correcting code just can be righted the wrong voluntarily, or require the system data that retransfer.Can guarantee like this system normal operation and can factor data mistake and cause working as machine.Because many one debug steps, therefore bug check and patch memory (ECCmemory) travelling speed can be slightly slower than non-bug check and patch memory.In addition for example, because bug check and patch memory have added correcting code (same to bit code), therefore its running bit length becomes longer, for example 72 bits and unconventional 64 bits.This class storer is applied to high-order computer as on servomechanism more.
Traditionally, correcting code is stored in the particular space that system provides, when this particular space larger, the length that represents correcting code can be longer, that is to say, bug check now and calibration result can be better, but, in general this particular space is a predetermined regular length, not only lacks flexibility and does not use fully frequency range.Therefore, need a kind of bug check of innovation and proofread and correct design and utilize fully frequency range, to promote the usefulness of storer.
Summary of the invention
One of object of the present invention is to provide a kind of bug check and bearing calibration and relevant error inspection and correcting circuit that decides correcting code length according to data length, improves the problems referred to above.
According to the first embodiment of the present invention, disclose a kind of bug check and bearing calibration.This bug check and bearing calibration include: a raw data package is compressed, and produce a packed data package; Dynamically determine a correcting code length according to a data length of this packed data package; According to this correcting code length, one packet data is carried out to bug check and correction coding to produce a correcting code, wherein this packet data at least comprises this packed data package; And this packet data and this correcting code are combined into a coded data package.
According to a second embodiment of the present invention, disclose a kind of bug check and bearing calibration.This bug check and bearing calibration include: read a coded data package, wherein this coded data package comprises a packet data and a correcting code, and this packet data at least comprises a packed data package; According to this correcting code, this packet data is carried out to bug check and correction decoder, and produce a decoding compressed data packet that should packed data package; And this decoding compressed data packet is decompressed, and produce a decompressed data package.
A third embodiment in accordance with the invention, discloses a kind of bug check and correcting circuit.This bug check and correcting circuit include a compressor circuit, a code length control circuit, a correcting code scrambler and a package generator.Wherein this compressor circuit is used for a raw data package to compress, and produces a packed data package.This code length control circuit is used for dynamically determining a correcting code length according to a data length of this packed data package.This correcting code scrambler is used for, according to this correcting code length, one packet data is carried out to bug check and correction coding to produce a correcting code, and wherein this packet data at least comprises this packed data package.This package generator is used for this packet data and this correcting code to be combined into a coded data package.
A fourth embodiment in accordance with the invention, discloses a kind of bug check and correcting circuit.This bug check and correcting circuit include an input working storage, a correction code decoder device and a decompression circuit.Wherein this input working storage is used for reading a coded data package, and wherein this coded data package comprises a packet data and a correcting code, and this packet data at least comprises a packed data package.This correction code decoder device is used for, according to this correcting code, this packet data is carried out to bug check and correction decoder, and produces a decoding compressed data packet that should packed data package.This decompression circuit is used for this decoding compressed data packet to decompress, and produces a decompressed data package.
The present invention except fully by the limited frequency range utilization obtaining via undistorted compression more bug check and proofread and correct on, utilize more in addition not enough scattered filling bit further to promote the accuracy of bug check and correction, reduced the burden of system and the time that user waits for.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of an one exemplary embodiment of bug check of the present invention and bearing calibration.
Fig. 2 is the schematic diagram that dynamically determines an one exemplary embodiment of correcting code length according to the data length of packed data package.
Fig. 3 is the schematic diagram that dynamically determines another one exemplary embodiment of correcting code length according to the data length of packed data package.
Fig. 4 is the schematic diagram that the present invention is directed to an one exemplary embodiment of bug check that data write and correcting circuit.
Fig. 5 is the schematic diagram of an embodiment of the code length control circuit in the bug check shown in Fig. 4 and correcting circuit.
Fig. 6 is the schematic diagram of another embodiment of the code length control circuit in the bug check shown in Fig. 4 and correcting circuit.
Fig. 7 is the schematic diagram that the present invention is directed to an one exemplary embodiment of bug check that data read and correcting circuit.
Fig. 8 is the schematic diagram that the present invention is directed to another one exemplary embodiment of bug check that data read and correcting circuit.
[main element symbol description]
100～11 steps
120 data write flow process
130 data read flow process
200,202 correcting codes
400,700,800 bug check and correcting circuits
402 compressor circuits
404 code length control circuits
406 correcting code scramblers
408 package generators
410,504,602 comparers
412,804 fill bit treatment circuit
502 dividers
506,604 switchs
702,802 package parsers
704,806 correction code decoder devices
706,808 decompression circuit
Embodiment
In the middle of instructions and appending claims, use some vocabulary to censure specific element.Person with usual knowledge in their respective areas should understand, and same element may be called with different nouns by manufacturer.This instructions and appending claims are not used as distinguishing the mode of element with the difference of title, but the difference in function is used as the criterion of distinguishing with element.In the whole text instructions and claim in the middle of mentioned " comprising " be an open term, therefore should be construed to " comprise but be not limited to ".Coupling in addition, " " word comprises directly any and is indirectly electrically connected means at this.Therefore, be coupled to one second device if describe a first device in literary composition, represent that this first device can directly be electrically connected in this second device, or be indirectly electrically connected to this second device by other devices or connection means.
In existing memory access system, in order to solve the problem of error in data, for instance, applicable error-correcting code (Error Correcting Code can arrange in pairs or groups, ECC) framework is with the data of detecting error recovery in the time transmitting, in other words, at receiving end by the inspection of coded data to detect and to proofread and correct error of transmission.Whether error-correcting code is used electronic method inspection to be stored in data in storer consistent.The storer of common wrong inspection and calibration function is mainly used in high-order PC, servomechanism or workstation, with the system of identical element (single-bit) memory error avoiding day by day increasing when machine problem.But; be limited to limited frequency range; system can limit the correcting code (for example same bit code) being additional in data packet conventionally a less length; and the length of correcting code is shorter; the debugger capacity that represents bug check and calibration function is just poorer; otherwise correcting code length is longer, sacrifice frequency range (that is volume of transmitted data is less).Therefore, the disclosed embodiment of the present invention can increase the debugger capacity of bug check and calibration function under the situation that does not affect volume of transmitted data, is described in detail as follows.
Please refer to Fig. 1, Fig. 1 is the process flow diagram of an one exemplary embodiment of bug check of the present invention and bearing calibration.If can reach substantially identical result, do not need necessarily to carry out in accordance with the step order in the flow process shown in Fig. 1, and the step shown in Fig. 1 not necessarily will be carried out continuously, that is other steps also can be inserted wherein, in addition, some step in Fig. 1 also can be omitted according to different embodiment or design requirement.The method includes following steps:
Step 100: a raw data package is compressed, and produce a packed data package;
Step 102: dynamically determine a correcting code length (for example together bit code length) according to a data length of this packed data package;
Step 104: according to this correcting code length, one packet data is for example carried out to bug check and correction coding, to produce a correcting code (together bit code), wherein this packet data at least comprises this packed data package;
Step 106: this packet data and this correcting code are combined into a coded data package;
Step 108: read a coded data package, wherein this coded data package comprises a packet data and a correcting code, and this packet data at least comprises a packed data package;
Step 110: according to this correcting code, this packet data is carried out to bug check and correction decoder, and produce a decoding compressed data packet that should packed data package; And
Step 112: this decoding compressed data packet is decompressed, and produce a decompressed data package.
Please note, step 100～step 106 shown in the embodiment of Fig. 1 of the present invention is that the data that write data to storer (for example flash memory) write flow process 120, reads flow process 130 and step 108～step 112 is the data that read these data from this storer.Write flow process 120 about data, please also refer to Fig. 4, Fig. 4 is the schematic diagram of an one exemplary embodiment of bug check of the present invention and correcting circuit 400.It should be noted, bug check and correcting circuit 400 are used for writing data to storer, and include a compressor circuit 402, a code length control circuit 404, a correcting code scrambler 406, a package generator 408, a comparer 410 and a filling bit treatment circuit 412.First,, as shown in step 100, compressor circuit 402 can be to wanting to write to a raw data package D of this storer
originalcompress, and produce a packed data package D
compit should be noted, of the present inventionly focus on not affecting original data frequency range, also do not destroy the correctness of raw data simultaneously, therefore the condensing routine that carries out in step 100 (that is compressor circuit 402 use compress mode) is a undistorted condensing routine (lossless data compression), compress compared to distortion, undistorted compression method has been preserved the integrality of data, in other words, this raw data package and the data through overcompression and after decompressing are identical.For instance, variation length coding (run-length encoding), Huffman (Huffman) coding, and blue Bo Lifu (Lempel Ziv) algorithm is all common undistorted compression method, but undistorted compression method of the present invention does not limit to above-mentioned coding method one of them, in practice, any mechanism that can reach undistorted compression all can adopt by compressed circuit 402.
Complete the packed data package D producing after the program of compression
compthere is a data length, and this data length can be according to the content of this raw data package or the kind of the undistorted compressed encoding using and variant, that is to say packed data package D
compcompressibility R
compcannot learnt in advance, and must after compression completes, obtained compressibility R via calculating
comp, be to carry out completing steps 102 by the code length control circuit 404 shown in Fig. 4 in the present embodiment, please refer to Fig. 5, Fig. 5 is the schematic diagram of an embodiment of the code length control circuit 404 in the bug check shown in Fig. 4 and correcting circuit 400.In the present embodiment, code length control circuit 404 includes a divider 502, a comparer 504 and a switch 506.First, divider 502 can be by packed data package D
complength divided by known raw data package D
originallength, and produce above-mentioned compressibility R
comp, that is to say compressibility R
compif less, represent raw data package D
originalcompressed degree is larger, and follow-up can have more idle space to be utilized.Next, comparer 504 can be by compressibility R
compwith a specific compression rate R
tHcompare, if compressibility R
compbe not less than specific compression rate R
tH, switch 506 can be set corresponding packed data package D
compa correcting code P
codea correcting code length P
lengthbe one first numerical value D1, otherwise, if compressibility R
compbe less than specific compression rate R
tH, switch 506 is just by correcting code length P
lengthbe set as a second value D2, wherein second value D2 is greater than the first numerical value D1 (that is D2>D1), thus, just can dynamically switch correcting code length P according to the compression result of the content of this raw data package
length.More particularly, of the present inventionly focus on trying one's best utilizing limited frequency range to increase correcting code length P
lengthwith the protection data that will transmit, but not adopt traditionally fixing correcting code length, but due to the characteristic of bug check and correcting code, be not suitable for using correcting code length P arbitrarily
lengththerefore the present embodiment has proposed to divide into the correcting code length P of two sections
length, that is to say, can come in two kinds of different correcting code length P according to the compression result of the content of raw data package
lengthbetween dynamically switch.But, under spirit of the present invention, define plural compressibility section if set multiple different specific compression rates, and compare one by one each specific compression rate and compressibility R via comparer 504
compcarry out detecting pressure shrinkage R
compfall within which compressibility section, afterwards, switch 506 comes dynamically between different correcting code length numerical value, to switch according to the comparative result of comparer 504 again, and the variation in this design also ought to belong to category of the present invention.
Note that by compressibility and decide the numerical value of correcting code length only as example explanation, but not restriction of the present invention.Please refer to Fig. 6, Fig. 6 is the schematic diagram of another embodiment of the code length control circuit 404 in the bug check shown in Fig. 4 and correcting circuit 400.Code length control circuit 404 includes a comparer 602 and a switch 604.First, relatively packed data package D of comparer 602
complength and a tentation data length L
tH, next, switch 604 can be according to the comparative result of comparer 602 by correcting code length P
legnthoptionally be set as above-mentioned the first numerical value D1 or second value D2, wherein D2>D1.Similarly, under spirit of the present invention, define plural data length section if set multiple different particular data length, and compare one by one each particular data length and packed data package D via comparer 604
complength, detect compression data packet D
complength fall within which data length section, afterwards, switch 604 comes dynamically between different correcting code length numerical value, to switch according to the comparative result of comparer 602 again, this one design on variation also ought to belong to category of the present invention.
Please refer to Fig. 2 and Fig. 3, it is for dynamically determining the schematic diagram of a correcting code length according to a data length of this packed data package.The length of the data packet in Fig. 2 is tentation data length L
tH, and the correcting code length P of a corresponding correcting code 202
lengthbe second value D2, be therefore less than tentation data length L
tHpacked data package D
compcorresponding correcting code length P
lengthcan be set to second value D2, otherwise, be greater than tentation data length L
tHpacked data package D
compthe correcting code length P of a corresponding correcting code 200
lengthcan be set to the first numerical value D1.It should be noted, in this one exemplary embodiment, the first numerical value D1 is the length of the correcting code 200 that corresponds to raw data package.As mentioned above, also can set multiple different correcting code length and plant different compressibility predetermined values with corresponding plural number, for instance, compressibility is divided into three sections, be respectively 0.25,0.5,0.55 and 1, and corresponding correcting code length is respectively 868 bit groups, 616 bit groups, 350 bit groups and 112 bit groups.It should be noted, select the mode of the compressibility of dividing different hop counts and the hop count marking off to be not limited to above-mentioned example, it also can or should be used for according to different demands in practice setting, and the mode of compression or algorithm also can affect the mode of dividing hop count.But, no matter dynamically switch correcting code length or only use the correcting code length of corresponding one fixing compressibility, within all belonging to category of the present invention, that is to say, no matter hop count divide number, all belong to interest field of the present invention.
In general, packed data package D
complength can just not be equal to the length L of the packet data shown in Fig. 2
tH, but therefore the vacancy that has some bit groups as shown in Figure 3 in step 104, is producing correcting code P
codebefore, relatively packed data package D of the comparer 410 in bug check and correcting circuit 400
complength and tentation data length L
tHdecide a filling (padding) bit length, and the vacancy that predetermined filling bit (for example ' 0 ' or ' 1 ') is attached to the some bit groups shown in Fig. 3 with a filling bit treatment circuit 412 is to produce this packet data, thus, correcting code scrambler 406 can produce correcting code P with this packet data
code.Data in the present embodiment write in flow process 120, finally also need a package generator 408 in mistake in using inspection and correcting circuit 400 by packed data package D
comp, fill bit, correcting code P
code, correcting code length P
lengthinformation and fill information (the correcting code length P of bit length
lengthinformation and fill the information of bit length and be not shown in Fig. 4) be combined into a coded data package (being step 106), please note, the information of filling bit length also can not be additional in this coded data package, and corresponding read operation can be described respectively in subsequent paragraph.
Read flow process 130 about the data shown in Fig. 1, please also refer to Fig. 7, Fig. 7 is the schematic diagram of an one exemplary embodiment of bug check of the present invention and correcting circuit 700.It should be noted, bug check and correcting circuit 700 are used for for example, (for example being write to the coded data package D of storer by bug check and correcting circuit 400 from storer (flash memory) reading out data
encoded), and include a package parser 702, a correction code decoder device 704 and a decompression circuit 706.First,, as shown in step 108, package parser 702 can be by first by a coded data package DR who reads into
encodedin correcting code P
codecorrecting code length P
lengthand the information of above-mentioned filling bit length dissects out, then according to correcting code P
codecorrecting code length capture correcting code P
codeand packet data DR
data, note that compared to the coded data package D in Fig. 4
encoded, the coded data package DR of Fig. 7
encodedmay be because of the interference of noise in passage or the damage of storer itself, and have the situation of wrong bit, therefore, compared to the packet data DR in Fig. 4
data, the packet data DR of Fig. 7
datajust may have wrong bit, this namely needs the reason of bug check and correcting circuit.
By coded data package DR
encodedin packet data DR
data, correcting code P
codeand after the information of above-mentioned this filling bit length dissects out, correction code decoder device 704 just can be according to correcting code P
codecome packet data DR
datacarry out bug check and correction decoder, therefore can pass through correcting code P
code(for example same bit code) detects packet data DR
datain wrong bit and corrected, finally produce corresponding above-mentioned packed data package D
compa decoding compressed data packet D
data(being step 110).Next, the decompression circuit 110 in the bug check in Fig. 7 and correcting circuit 700 can be to decoding compressed data packet D
datadecompress, that is the step 112 shown in Fig. 1, and produce a decompressed data package D
original', in the present embodiment, the gunzip that decompression circuit 110 in bug check and correcting circuit 700 is carried out is the condensing routine that the compressor circuit 402 in bug check and the correcting circuit 400 corresponding in Fig. 4 carries out, also be a undistorted compression simultaneously, for instance, if the gunzip that the compressor circuit 402 in bug check and correcting circuit 400 carries out adopts a variation length coding algorithm, the gunzip that decompression circuit 110 in bug check and correcting circuit 700 is carried out adopts a variation length decoder algorithm, but undistorted decompression method of the present invention is not limited to variation length decoder algorithm, in practice, any mechanism that can reach undistorted decompression all belongs to interest field of the present invention.It should be noted decoding compressed data packet D
datain comprised above-mentioned packed data package D
compand filling bit, but decompressed data package D
original' length be fixing and known, therefore the general practice can be in order to decoding compressed data packet D
datain bit decompress, the data length that the compressor circuit 402 in bug check and correcting circuit 400 is exported reaches decompressed data package D
original' length till, that is to say, can not need to process being additional to above-mentioned packed data package D completely
compfilling bit.It should be noted, if all wrong bits all can be by correction code decoder device 704 according to correcting code P
codeproofreaied and correct, decompressed data package D
original' and raw data package D
originalcan there is identical data content.
Please refer to Fig. 8, Fig. 8 is the schematic diagram of an one exemplary embodiment of bug check of the present invention and correcting circuit 800.Read flow process 130 about the data shown in Fig. 1, also can adopt the bug check shown in Fig. 8 and correcting circuit 800 from coded data package DR
encodedin obtain desired decompressed data package D
original'.In the present embodiment, filling bit treatment circuit 804 can be for being additional to above-mentioned packed data package D
compfilling bit process, to promote usefulness of the present invention and debugger capacity.The information of this filling bit length that first, filling bit treatment circuit 804 can produce according to package parser 702 checks packet data DR
datain filling bit, due to fill bit be known bit (for example ' 0 ' or ' 1 '), that is to say, by the information of this filling bit length, just can learn packet data DR
datain the whether wrong bit of filling bit, if yes, can directly be corrected and not need to correct by correction code decoder device 806, saved thus the wrong bit remaining sum that can correct.For instance, if corresponding correcting code length can be corrected 40 bits, and received packet data DR
datain have altogether 41 wrong bit bits, one of them is positioned at packet data DR
datain the scope of filling bit in, other 40 are positioned at above-mentioned packed data package D
compscope in, do not correcting in advance packet data DR
datain filling bit in the situation of 1 wrong bit under, because wrong bit outnumbers the bit number that correcting code can be corrected, whole coded data package DR
encodedcannot be corrected and be abandoned, but, in the present embodiment, pass through to fill bit treatment circuit 804 directly to packet data DR
datain filling bit in 1 wrong bit corrected, and do not need to correct by correction code decoder device 806, can make overall packet data DR
datain wrong bit bit number be reduced to 40, thus, follow-up correction code decoder device 806 just can successfully be corrected all wrong bit bits, coded data package DR
encodedto correctly be reduced into raw data package D
origimal(that is D
origimal'=D
origimal).In addition, all the other elements (that is package parser 802, correction code decoder device 804 and decompression circuit 806) principle of operation of bug check and correcting circuit 800 is substantially identical with the element of the same name in bug check and correcting circuit 700, in this case ask simple and clear, therefore seldom repeat.
The present invention except fully by the limited frequency range utilization obtaining via undistorted compression more bug check and proofread and correct on, utilize more in addition not enough scattered filling bit further to promote the accuracy of bug check and correction, reduced the burden of system and the time that user waits for.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (27)
1. bug check and a bearing calibration, includes:
One raw data package is compressed, and produce a packed data package;
Dynamically determine a correcting code length according to a data length of this packed data package;
According to this correcting code length, one packet data is carried out to bug check and correction coding to produce a correcting code, wherein this packet data at least comprises this packed data package; And
This packet data and this correcting code are combined into a coded data package.
2. bug check as claimed in claim 1 and bearing calibration, is characterized in that, it is used in a memory access system.
3. bug check as claimed in claim 1 and bearing calibration, is characterized in that, the undistorted compression of boil down to that this raw data package is carried out.
4. bug check as claimed in claim 1 and bearing calibration, is characterized in that, dynamically determines that according to this data length of this packed data package the step of this correcting code length includes:
This data length of this packed data package is obtained a compressibility that should raw data package divided by a data length of this raw data package; And
Dynamically determine this correcting code length according to this compressibility.
5. bug check as claimed in claim 4 and bearing calibration, is characterized in that, dynamically determines that the step of this correcting code length includes according to this compressibility:
Relatively this compressibility and a specific compression rate;
If this compressibility is not less than this specific compression rate, be one first numerical value by this correcting code length setting; And
If this compressibility is less than this specific compression rate, be a second value by this correcting code length setting, wherein this second value is greater than this first numerical value.
6. bug check as claimed in claim 1 and bearing calibration, is characterized in that, dynamically determines that according to this data length of this packed data package the step of this correcting code length separately includes:
Relatively this data length of this packed data package and a tentation data length;
If this this data length is not less than this tentation data length, be one first numerical value by this correcting code length setting; And
If this this data length is less than this tentation data length, be a second value by this correcting code length setting, wherein this second value is greater than this first numerical value.
7. bug check as claimed in claim 1 and bearing calibration, is characterized in that, separately includes:
The information of this correcting code length is added to this coded data package.
8. bug check as claimed in claim 1 and bearing calibration, is characterized in that, separately includes:
Relatively this data length of this packed data package and a tentation data length decide a filling bit length; And
Add and fill bit to this packed data package, to produce this packet data according to this filling bit length.
9. bug check as claimed in claim 1 and bearing calibration, is characterized in that, separately includes:
The information of this filling bit length is added to this coded data package.
10. bug check and a bearing calibration, includes:
Read a coded data package, wherein this coded data package comprises a packet data and a correcting code, and this packet data at least comprises a packed data package;
According to this correcting code, this packet data is carried out to bug check and correction decoder, and produce a decoding compressed data packet that should packed data package; And
This decoding compressed data packet is decompressed, and produce a decompressed data package.
11. bug check as claimed in claim 10 and bearing calibrations, is characterized in that, it is used in a memory access system.
12. bug check as claimed in claim 10 and bearing calibrations, is characterized in that, the decompress(ion) that this decoding compressed data packet is carried out is condensed to undistorted decompression.
13. bug check as claimed in claim 10 and bearing calibrations, is characterized in that, this coded data package separately comprises the information of a correcting code length of this correcting code, and this bug check and bearing calibration separately comprise:
Obtain this correcting code in this coded data package according to this correcting code length.
14. bug check as claimed in claim 10 and bearing calibrations, is characterized in that, this coded data package separately comprises the information of a filling bit length, and this bug check and bearing calibration separately comprise:
Check the filling bit that is additional to this packet data according to this filling bit length.
15. 1 kinds of bug check and correcting circuit, include:
One compressor circuit, is used for a raw data package to compress, and produces a packed data package;
One code length control circuit, is used for dynamically determining a correcting code length according to a data length of this packed data package;
One correcting code scrambler, is used for, according to this correcting code length, one packet data is carried out to bug check and correction coding to produce a correcting code, and wherein this packet data at least comprises this packed data package; And
One package generator, is used for this packet data and this correcting code to be combined into a coded data package.
16. bug check as claimed in claim 15 and correcting circuits, is characterized in that, it is used in a memory access system.
17. bug check as claimed in claim 15 and correcting circuits, is characterized in that, the undistorted compression of boil down to that this compressor circuit carries out.
18. bug check as claimed in claim 15 and correcting circuits, is characterized in that, this code length control circuit includes:
One divider, is used for this data length of this packed data package to obtain a compressibility that should raw data package divided by a data length of this raw data package; And
One selects circuit, dynamically determines this correcting code length according to this compressibility.
19. bug check as claimed in claim 18 and correcting circuits, is characterized in that, this selection circuit includes:
One comparer, is used for relatively this compressibility and a specific compression rate; And
One switch, the comparative result being used for according to this compressibility and this specific compression rate, is optionally set as one first numerical value or a second value by this correcting code length, and wherein this second value is greater than this first numerical value.
20. bug check as claimed in claim 15 and correcting circuits, is characterized in that, this code length control circuit includes:
One comparer, is used for relatively this data length and a tentation data length of this packed data package; And
One switch, is used for, according to this data length and this tentation data length, this correcting code length being optionally set as to one first numerical value or a second value, and wherein this second value is greater than this first numerical value.
21. bug check as claimed in claim 15 and correcting circuits, is characterized in that, this package generator is separately added to the information of this correcting code length this coded data package.
22. bug check as claimed in claim 15 and correcting circuits, is characterized in that, separately include:
One comparer, is used for relatively this data length and a tentation data length of this packed data package to decide a filling bit length; And
One fills bit treatment circuit, is used for adding and filling bit to this packed data package, to produce this packet data according to this filling bit length.
23. 1 kinds of bug check and correcting circuit, include:
One package parser, is used for reading a coded data package, and wherein this coded data package comprises a packet data and a correcting code, and this packet data at least comprises a packed data package;
One correction code decoder device, is used for, according to this correcting code, this packet data is carried out to bug check and correction decoder, and produces a decoding compressed data packet that should packed data package; And
One decompression circuit, is used for this decoding compressed data packet to decompress, and produces a decompressed data package.
24. bug check as claimed in claim 23 and correcting circuits, is characterized in that, it is used in a memory access system.
25. bug check as claimed in claim 23 and correcting circuits, is characterized in that, the decompress(ion) that this compressor circuit carries out is condensed to undistorted decompression.
26. bug check as claimed in claim 23 and correcting circuits, it is characterized in that, this coded data package separately comprises the information of a correcting code length of this correcting code, and this package parser is separately used for obtaining this correcting code in this coded data package according to this correcting code length.
27. bug check as claimed in claim 23 and correcting circuits, is characterized in that, this coded data package separately comprises the information of a filling bit length, and this bug check and correcting circuit separately include:
One fills bit treatment circuit, is used for checking according to this filling bit length the filling bit that is additional to this packet data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210455619.2A CN103810054A (en) | 2012-11-14 | 2012-11-14 | Error checking and correcting methods and related error checking and correcting circuit |
Applications Claiming Priority (1)
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| CN106935271A (en) * | 2016-01-21 | 2017-07-07 | 威盛电子股份有限公司 | Controller device and operation method of three-dimensional framework nonvolatile memory |
| CN108595289A (en) * | 2018-01-12 | 2018-09-28 | 江苏华存电子科技有限公司 | The method for improving short code word information checking rate for data storage error correction code check |
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| CN108595289A (en) * | 2018-01-12 | 2018-09-28 | 江苏华存电子科技有限公司 | The method for improving short code word information checking rate for data storage error correction code check |
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