CN103823785B - Multi-way ARINC429 data transmit-receive circuit structure based on development of DSP and CPLD - Google Patents
Multi-way ARINC429 data transmit-receive circuit structure based on development of DSP and CPLD Download PDFInfo
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- CN103823785B CN103823785B CN201410113491.0A CN201410113491A CN103823785B CN 103823785 B CN103823785 B CN 103823785B CN 201410113491 A CN201410113491 A CN 201410113491A CN 103823785 B CN103823785 B CN 103823785B
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Abstract
The invention discloses a multi-way ARINC429 data transmit-receive circuit structure based on the development of a DSP and a CPLD. The multi-way ARINC429 data transmit-receive circuit structure based on the development of the DSP and the CPLD comprises a DSP circuit, multiple sets of ARINC429 bus transmit-receive chip circuits, an auxiliary control circuit achieved through CPLD programming, wherein a data end of each ARINC429 bus transmit-receive chip is connected with the DSP, a control end of each ARINC429 bus transmit-receive chip is connected with the CPLD, the DSP circuit achieves control over the multiple sets of ARINC429 bus transmit-receive chips by sending an control instruction to a register circuit achieved through CPLD chip programming, and receiving decoding and sending coding of ARINC429 data are achieved through software in a DSP chip. The multi-way ARINC429 data transmit-receive circuit structure based on the development of the DSP and the CPLD can achieve real-time reading and sending of multiple ways of ARINC429 data through a data bus of the DSP chip, avoids collision, loss and error codes of the data, and achieves high-speed processing of the data.
Description
Technical field
The present invention relates to the technical field of ARINC429 data transmit-receive circuit, be specifically related to one and open based on DSP and CPLD
The multi-channel A RINC429 data transmit-receive circuit structure sent out.
Background technology
At present, known ARINC429 data transmit-receive circuit based on DSP and FPGA by DSP circuit, FPGA circuitry and
ARINC429 bus transceiving chip circuit is constituted, when carrying out multichannel data reception, and the ways using FPGA algorithm examples more, although
This design has multichannel transmitting-receiving ability, but multiplexer channel synchronization receives ARINC429 data and easily occurs that data are rushed
Dash forward, lose and error code.And known multi-channel A RINC429 based on DSP and CPLD receives in the too much outside that circuit takies DSP
It is disconnected so that DSP is the most limited in circuit function, and communication conflict easily occurs when multichannel data synchronization is received and dispatched,
Make in DSP processes data procedures, easily occur that the reception of multi-channel A RINC429 data is lost.
Summary of the invention
It is contemplated that overcome deficiency of the prior art, it is provided that a kind of multichannel based on DSP and CPLD exploitation
ARINC429 data transmit-receive circuit structure, this data transmit-receive circuit structure can not only apply the data/address bus of dsp chip directly to read
Write the data terminal organizing ARINC429 bus transceiving chip more, utilize CPLD(CPLD) the depositing of programming realization
Device circuit controls sequential and logical relation, and incorporates multiple external interrupt letter of many group ARINC429 bus transceiving chips
Number, it is greatly saved the use to DSP external interrupt resource, effectively prevent data collision, loss and error code.
The present invention solves above-mentioned technical problem and be the technical scheme is that a kind of multichannel based on DSP and CPLD exploitation
ARINC429 data transmit-receive circuit structure, including DSP circuit, many group ARINC429 bus transceiving chip circuit, also include by
The register circuit that CPLD chip programming realizes；
Data/address bus XD0～XD15 of described DSP circuit is by electrical level matching circuit and described many group ARINC429 buses
Data/address bus BD00～BD15 of transceiving chip circuit connects, control instruction end D429_A0～D429_A7 of described DSP circuit,
Control instruction completes to encourage end D429_ARDY, data to send state end D429_TX/R, data send Enable Pin D429_ENTX,
Integrated Receiver interruptive port D429_RINT, receive channel coding address end D429_RINTA0～D429_RINTA3 with described by
Control instruction end D429_A0～D429_A7 of register circuit, control instruction that CPLD chip programming realizes complete to encourage end
D429_ARDY, data send state end D429_TX/R, data send Enable Pin D429_ENTX, Integrated Receiver interruptive port
D429_RINT, receive channel coding address end D429_RINTA0～D429_RINTA3 correspondence and connect, described organize ARINC429 more
Bus transceiving chip circuit includes 4 groups, it is possible to receive 8 road ARINC429 data simultaneously, sends 4 road ARINC429 data, wherein
The data sink 1 of the 1st group of transmission circuit receive interruptive portData sink 2 receives interruptive portReceive high/low 16 of data and read selection end SEL, data sink 1 Enable PinData sink 2 enables
EndSend low 16 writes of data and select endSend high 16 writes of data and select endData are sent out
State end TX/R, data are sent to send Enable Pin ENTX, chip configuration Enable PinBy electrical level matching circuit and institute
The data sink 1 of the 1st group of transmission circuit stating the register circuit realized by CPLD chip programming receives interruptive port
C429A_RDY1, the data sink 2 of the 1st group of transmission circuit receive interruptive port C429A_RDY2, the connecing of the 1st group of transmission circuit
Receive data high/low 16 read select end C429A_SEL, data sink 1 Enable Pin C429A_EN1 of the 1st group of transmission circuit,
Data sink 2 Enable Pin C429A_EN2 of the 1st group of transmission circuit, low 16 the write choosings of transmission data of the 1st group of transmission circuit
Select end C429A_PL1, high 16 writes of transmission data of the 1st group of transmission circuit select end C429A_PL2, the 1st group of transmission circuit
Data send state end C429A_TX/R, the 1st group of transmission circuit data send Enable Pin C429A_ENTX, the 1st group of transmitting-receiving
The chip configuration Enable Pin C429A_CWSTR correspondence of circuit connects, the 2nd group of transmission circuit SEL、TX/R、ENTX、Hold by electrical level matching circuit with described by
The data sink 1 of the 2nd group of transmission circuit of the register circuit that CPLD chip programming realizes receives interruptive port C429B_
RDY1, the data sink 2 of the 2nd group of transmission circuit receive interruptive port C429B_RDY2, the reception data of the 2nd group of transmission circuit
High/low 16 are read selection C429B_SEL, data sink 1 Enable Pin C429B_EN1 of the 2nd group of transmission circuit, the 2nd group of receipts
Data sink 2 Enable Pin C429B_EN2 of Power Generation Road, low 16 writes of transmission data of the 2nd group of transmission circuit select end
C429B_PL1, high 16 writes of transmission data of the 2nd group of transmission circuit select end C429B_PL2, the number of the 2nd group of transmission circuit
According to the data transmission Enable Pin C429B_ENTX, the 2nd group of transmission circuit that send state end C429B_TX/R, the 2nd group of transmission circuit
Chip configuration Enable Pin C429B_CWSTR correspondence connect, the 3rd group of transmission circuitSEL、 TX/R、ENTX、Hold by electrical level matching circuit with described by
The data sink 1 of the 3rd group of transmission circuit of the register circuit that CPLD chip programming realizes receives interruptive port C429C_
RDY1, the data sink 2 of the 3rd group of transmission circuit receive interruptive port C429C_RDY2, the reception data of the 3rd group of transmission circuit
High/low 16 read select end C429C_SEL, data sink 1 Enable Pin C429C_EN1 of the 3rd group of transmission circuit, the 3rd group
Data sink 2 Enable Pin C429C_EN2 of transmission circuit, low 16 writes of transmission data of the 3rd group of transmission circuit select end
C429C_PL1, high 16 writes of transmission data of the 3rd group of transmission circuit select end C429C_PL2, the number of the 3rd group of transmission circuit
According to the data transmission Enable Pin C429C_ENTX, the 3rd group of transmission circuit that send state end C429C_TX/R, the 3rd group of transmission circuit
Chip configuration Enable Pin C429C_CWSTR correspondence connect, the 4th group of transmission circuitSEL、TX/R、ENTX、Hold by electrical level matching circuit with described by
The data sink 1 of the 4th group of transmission circuit of the register circuit that CPLD chip programming realizes receives interruptive port C429D_
RDY1, the data sink 2 of the 4th group of transmission circuit receive interruptive port C429D_RDY2, the reception data of the 4th group of transmission circuit
High/low 16 read select end C429D_SEL, data sink 1 Enable Pin C429D_EN1 of the 4th group of transmission circuit, the 4th group
Data sink 2 Enable Pin C429D_EN2 of transmission circuit, low 16 writes of transmission data of the 4th group of transmission circuit select end
C429D_PL1, high 16 writes of transmission data of the 4th group of transmission circuit select end C429D_PL2, the number of the 4th group of transmission circuit
According to the data transmission Enable Pin C429D_ENTX, the 4th group of transmission circuit that send state end C429D_TX/R, the 4th group of transmission circuit
Chip configuration Enable Pin C429D_CWSTR correspondence connect.
Wherein, the chip that described DSP circuit uses is TMS320F28335.
Wherein, the chip that the register circuit that described CPLD chip programming realizes uses is EPM570.
Wherein, the chip that described ARINC429 bus transceiving chip circuit uses is HS3282 and HS3182.
The principle of the present invention is:
As Figure 1-5, a kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation, including
DSP circuit 1, many group ARINC429 bus transceiving chip circuit 2, also include the register circuit 3 that realized by CPLD chip programming；
Read and write the data bus terminal organizing ARINC429 bus transceiving chip circuit 2 by DSP circuit 1, to real by CPLD chip programming more
Existing register circuit 3 sends control instruction and realizes the controls organizing ARINC429 bus transceiving chip more.First by depositing
Device circuit 3 coordinates DSP circuit 1 to pass to configuration signal successively organize ARINC429 bus transceiving chip electricity by data/address bus more
Road 2, the ARINC429 bus transceiving chip configured receives ARINC429 data, any one road serial interface by serial line interface
After mouth receives ARINC429 data, CPLD chip programming the register circuit 3 realized is by D429_RINT end reset, to touch
Sending out the external interrupt of DSP circuit 1, DSP circuit 1 judges ARINC429 number by reading D429_RINTA0～D429RINTA3
According to specifically receive passage, then by configuring the control instruction of D429_A0～D429_A7 end and generating one at D429_ARDY end
Individual trailing edge signal reads the ARINC429 data of correspondingly received passage, owing to the data of ARINC429 bus transceiving chip are total
Line is 16, and the transceiving format of ARINC429 data is 32, therefore reads road ARINC429 data, DSP circuit 1 company of need
Continuous twice operation D429_A0～D429_A7 and D429_ARDY end, after current read data has operated, DSP circuit 1 detects
D429_RINT port status, if register circuit 3 set that D429_RINT end is realized by CPLD chip programming, then shows
Current read operation completes, if register circuit 3 reset that D429_RINT end is realized by CPLD chip programming, then it represents that have
Multi-path serial interface is simultaneously received ARINC429 data, or is reading the process of the ARINC429 data that current interface receives
In other road serial line interfaces receive other follow-up ARINC429 data, now DSP circuit 1 again read off D429_RINTA0～
What D429RINTA3 judged not read ARINC429 data specifically receives passage, and repeats aforementioned read operation process, and again
Detection D429_RINT port status, until detecting the register circuit that D429_RINT port is realized by CPLD chip programming
3 sets.When the ARINC429 bus transceiving chip configured sends ARINC429 data by serial line interface, DSP circuit 1
According to wanting the control instruction of the required transmission interface correspondence used configuration D429_A0～D429_A7 end and in the life of D429_ARDY end
A trailing edge signal is become to write the ARINC429 data of corresponding transmission interface, due to the number of ARINC429 bus transceiving chip
It is 16 according to bus, and the transceiving format of ARINC429 data is 32, therefore sends road ARINC429 data, DSP circuit 1
Needing double operation D429_A0～D429_A7 and D429_ARDY end, DSP circuit 1 detects the shape of D429_TX/R end afterwards
State, after D429_TX/R end is by reset, DSP circuit 1 is by D429_ENTX end set, and then DSP circuit 1 detects again
The state of D429_TX/R end, after D429_TX/R end is by set, DSP circuit 1 is by D429_ENTX end reset.
The various circuit used in this circuit are all bus read modes at a high speed, by realized by CPLD chip programming
Register circuit 3 controls transmitting-receiving sequential and the logical relation of multi-channel A RINC429 data, it is to avoid multichannel data conflict, data occur
Lose and error code, and connected the reset signal of ARINC429 bus transceiving chip by dsp chip, in order in the feelings that data are overflowed
ARINC429 bus transceiving chip is made to reset under condition, it is ensured that data normal transmission.
Compared with prior art, the invention has the beneficial effects as follows:
1, multi-channel A RINC429 data can be read by dsp chip data/address bus and be sent by the present invention in real time, it is to avoid
Data collision, loss and error code, it is achieved the high speed processing to data.
2, the multiple external interrupt signals organizing ARINC429 bus transceiving chip are integrated into one by circuit structure of the present invention more
Individual, greatly reduce the usage quantity of DSP circuit external interrupt, in the case of DSP external interrupt resource-constrained, make more multichannel
ARINC429 data transmit-receive is possibly realized, and thoroughly solves data collision when multi-channel A RINC429 data accept simultaneously, sum
A yard problem is lost according to the data in processing procedure.
3, circuit structure of the present invention is the most succinct, it is to avoid sequential during transceiving data is chaotic, and save within DSP is big
Amount calculates resource, rationally distributed, easy to operate, low cost.
Accompanying drawing explanation
Fig. 1 is that the circuit structure structural diagrams of the present invention is intended to；
Fig. 2 is the following characteristics Processing Algorithm schematic diagram of the specific embodiment of the invention；
Fig. 3 is the DSP circuit schematic diagram of the specific embodiment of the invention；
Fig. 4 is the ARINC429 bus transceiving chip circuit theory diagrams of the specific embodiment of the invention；
Fig. 5 is the register circuit schematic diagram of the CPLD chip programming realization of the specific embodiment of the invention；
Fig. 6 is the transmission example waveform of the ARINC429 bus data 0x8025806A of the specific embodiment of the invention；
Fig. 7 is the reception example waveform of the ARINC429 bus data 0x03958584 of the specific embodiment of the invention.
Detailed description of the invention
The present invention will be further described with embodiment below in conjunction with the accompanying drawings.The present invention is to receive 8 road ARINC429 numbers
According to, send 4 road ARINC429 data instances and illustrate.All brackets " (transmission) " and " (reception) " only represent data and signal
Direction.
In FIG, the closure of each functional block diagram and arrow represents basic circuit principle and the signal control of the present invention
Relation processed, multi-channel A RINC429 data transmit-receive circuit based on DSP and CPLD exploitation, including DSP circuit 1, also include many groups
ARINC429 bus transceiving chip circuit 2 and the register circuit 3 realized by CPLD chip programming；
The present invention is further described for 2-accompanying drawing 4 below in conjunction with the accompanying drawings.
16 bit data bus XD0 of described DSP circuit 1～XD15 organize ARINC429 by electrical level matching circuit with described more
Data/address bus BD00～BD15 of bus transceiving chip circuit 2 connects；
Control output end D429_A0～D429_A7 of described DSP circuit 1, D429_ARDY, D429_ENTX end are with described
Control input D429_A0～D429_A7 of the register circuit 3 realized by CPLD chip programming, D429_ARDY, D429_
ENTX end correspondence connects；
The data accepted flag transmitting terminal D429_RINT of the described register circuit 3 realized by CPLD chip programming,
D429_RINTA0～D429_RINTA3 and data accepted flag receiving terminal D429_RINT and D429_ of described DSP circuit 1
RINTA0～D429_RINTA3 connects；
The ARINC429 data of the described register circuit 3 realized by CPLD chip programming send state output end D429_
TX/R sends state output terminal D429_TX/R with the data of described DSP circuit 1 and is connected；
Described many group ARINC429 bus transceiving chip circuit include 4 groups, the Read-write Catrol end of the 1st group of transmission circuit therein
SEL、ENTX、Input by after electrical level matching circuit respectively with post
Read-write Catrol outfan C429A_SEL, C429A_EN1, C429A_EN2, C429A_PL1, C429A_PL2, C429A_ of latch circuit 3
ENTX, C429A_CWSTR connect, the Read-write Catrol end SEL of the 2nd group of transmission circuit, ENTX、Input by after electrical level matching circuit respectively Read-write Catrol with register circuit 3 export
End C429B_SEL, C429B_EN1, C429B_EN2, C429B_PL1, C429B_PL2, C429B_ENTX, C429B_CWSTR are even
Connect, the Read-write Catrol end SEL of the 3rd group of transmission circuit,
Input by after electrical level matching circuit respectively with the Read-write Catrol outfan C429C_SEL of register circuit 3, C429C_EN1,
C429C_EN2, C429C_PL1, C429C_PL2, C429C_ENTX, C429C_CWSTR connect, the read-write of the 4th group of transmission circuit
Control end SEL,ENTX、Input is by after electrical level matching circuit
Respectively with the Read-write Catrol outfan C429D_SEL of register circuit 3, C429D_EN1, C429D_EN2, C429D_PL1,
C429D_PL2, C429D_ENTX, C429D_CWSTR connect；
The reiving/transmitting state outfan of the 1st group of transmission circuit in described many group ARINC429 bus transceiving chip circuit 2The transmitting-receiving of the register circuit 3 that TX/R is realized with described CPLD chip programming by electrical level matching circuit
State output terminal C429A_RDY1, C429A_RDY2, C429A_TX/R correspondence connects, and the reiving/transmitting state of the 2nd group of transmission circuit is defeated
Go out endThe register circuit 3 that TX/R is realized with described CPLD chip programming by electrical level matching circuit
Reiving/transmitting state input C429B_RDY1, C429B_RDY2, C429B_TX/R correspondence connects, the transmitting-receiving shape of the 3rd group of transmission circuit
State outfanThe register circuit that TX/R is realized with described CPLD chip programming by electrical level matching circuit
Reiving/transmitting state input C429C_RDY1, C429C_RDY2, C429C_TX/R correspondence of 3 connects, the transmitting-receiving of the 4th group of transmission circuit
State output endThe depositor electricity that TX/R is realized by electrical level matching circuit and described CPLD chip programming
Reiving/transmitting state input C429D_RDY1, C429D_RDY2, C429D_TX/R correspondence on road 3 connects.
According to above-mentioned connected mode, as in figure 2 it is shown, the control instruction that DSP circuit is sent at D429_A0～D429_A7
Data read command, ARINC429 is received including the instruction of ARINC429 bus transceiving chip initial configuration, ARINC429 bus
Bus sends data write instruction, after receiving these one-level control instructions, passes through the register circuit of CPLD programming realization
Directly operate the Read-write Catrol end of corresponding A RINC429 bus transceiving chip after electrical level matching circuit, the most also decode out one-level control
Two-stage control instruction contained in system instruction, Two-stage control instruction will indicate the ARINC429 bus transmitting-receiving of correspondence in first-level instruction
The data of chip circuit send the level of state end (C429A_TX/R, C429B_TX/R, C429C_TX/R or C429D_TX/R)
State copies to the data of the register circuit by CPLD programming realization and sends state (transmission) end D429_TX/R for DSP electricity
Road detection judges, and it is multiple that the data of the register circuit by CPLD programming realization are sent Enable Pin D429_ENTX level state
System sends Enable Pin (C429A_ENTX, C429B_ENTX, C429C_ to the data of corresponding ARINC429 bus transceiving chip
ENTX or C429D_ENTX) to realize the DSP circuit data transmission enable to ARINC429 bus transceiving chip circuit.Receiving
During ARINC429 data, the register circuit of CPLD programming realization all the time 8 road ARINC429 buses are received the reception of passage
Interrupt (reception) port (C429A_RDY1, C429A_RDY2, C429B_RDY1, C429B_RDY2, C429C_RDY1, C429C_
RDY2, C429D_RDY1, C429D_RDY2) it is comprehensively a road Integrated Receiver interruptive port D429_RINT, when interrupting occurring,
Send to receive channel coding address (transmission) end D429_RINTA0～D429_RINTA3 confession by currently receiving channel coding address
DSP circuit interrupts reading, if occur new reception to interrupt when Multiple Interrupt occurs or reads data simultaneously, then DSP circuit completes
After current data read operation, Integrated Receiver interruptive port D429_RINT maintains interrupt status, and leading to other non-read channels
Coded address, road is sent to receive channel coding address (transmission) end D429_RINTA0～D429_RINTA3, realizes whole connecing with this
Receipts circuit is accurate, high speed processing, it is to avoid data collision, loss and error code.
The chip that DSP circuit of the present invention uses is TMS320F28335.
CPLD chip of the present invention uses EPM570.
The chip that ARINC429 bus transceiving chip circuit of the present invention uses is HS3282 and HS3182.
Fig. 5 is the register circuit schematic diagram of the CPLD chip programming realization of the specific embodiment of the invention；
Fig. 6 is the transmission example waveform of the ARINC429 bus data 0x8025806A of the specific embodiment of the invention；This
Sending example waveform is the schematic diagram that correct coding of the present invention is sent out several.
Fig. 7 is the reception example waveform of the ARINC429 bus data 0x03958584 of the specific embodiment of the invention.This connects
Receiving example waveform is that the present invention correctly, inerrably encodes the schematic diagram receiving number.
The non-detailed disclosure of the present invention partly belong to techniques known.
Although detailed description of the invention illustrative to the present invention is described above, in order to the technology of the art
Personnel understand the present invention, the common skill it should be apparent that the invention is not restricted to the scope of detailed description of the invention, to the art
From the point of view of art personnel, as long as various change limits and in the spirit and scope of the present invention that determine in appended claim, these
Change is apparent from, and all utilize the innovation and creation of present inventive concept all at the row of protection.
Claims (4)
1. a multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation, including DSP circuit (1), many groups
ARINC429 bus transceiving chip circuit (2), it is characterised in that also include the register circuit realized by CPLD chip programming
(3)；
Data/address bus XD0～XD15 of described DSP circuit (1) is received with described many group ARINC429 buses by electrical level matching circuit
Data/address bus BD00～BD15 sending out chip circuit (2) connects, the control instruction end D429_A0 of described DSP circuit (1)～
D429_A7, control instruction complete to encourage end D429_ARDY, data to send state end D429_TX/R, data send Enable Pin
D429_ENTX, Integrated Receiver interruptive port D429_RINT, reception channel coding address end D429_RINTA0～D429_
Control instruction end D429_A0～D429_A7 of RINTA3 and the described register circuit (3) realized by CPLD chip programming, control
Instruction processed completes to encourage end D429_ARDY, data to send state end D429_TX/R, data transmission Enable Pin D429_ENTX, combine
Splice grafting is received interruptive port D429_RINT, is received channel coding address end D429_RINTA0～the connection of D429_RINTA3 correspondence, institute
State many groups ARINC429 bus transceiving chip circuit (2) and include 4 groups, it is possible to receive 8 road ARINC429 data simultaneously, send 4 tunnels
ARINC429 data, the data sink 1 of the 1st group of ARINC429 bus transceiving chip circuit therein receives interruptive portData sink 2 receives interruptive portReceive high/low 16 of data and read selection end SEL, data receiver
Device 1 Enable PinData sink 2 Enable PinSend low 16 writes of data and select endSend data
High 16 writes select endData send state end TX/R, data send Enable Pin ENTX, chip configuration Enable PinThe 1st group of transmitting-receiving electricity by electrical level matching circuit with the described register circuit (3) realized by CPLD chip programming
The data sink 1 on road receives interruptive port C429A_RDY1, the data sink 2 of the 1st group of transmission circuit receives interruptive port
C429A_RDY2, high/low 16 of the reception data of the 1st group of transmission circuit read and select end C429A_SEL, the 1st group of transmission circuit
Data sink 1 Enable Pin C429A_EN1, data sink 2 Enable Pin C429A_EN2 of the 1st group of transmission circuit, the 1st group of transmitting-receiving
Low 16 writes of transmission data of circuit select end C429A_PL1, high 16 writes of transmission data of the 1st group of transmission circuit select end
C429A_PL2, the data of the 1st group of transmission circuit send state end C429A_TX/R, the data of the 1st group of transmission circuit send Enable Pin
C429A_ENTX, the chip configuration Enable Pin C429A_CWSTR correspondence of the 1st group of transmission circuit connect, the 2nd group of ARINC429 bus
Transceiving chip circuitSEL、 TX/R、ENTX、Hold the 2nd group of transmitting-receiving by electrical level matching circuit with the described register circuit (3) realized by CPLD chip programming
The data sink 1 of circuit receive interruptive port C429B_RDY1, the 2nd group of transmission circuit data sink 2 receive in the broken ends of fractured bone
Mouthful C429B_RDY2, high/low 16 of the receptions data of the 2nd group of transmission circuit read selection C429B_SEL, the 2nd group of transmission circuit
Data sink 1 Enable Pin C429B_EN1, data sink 2 Enable Pin C429B_EN2 of the 2nd group of transmission circuit, the 2nd group of transmitting-receiving
Low 16 writes of transmission data of circuit select end C429B_PL1, high 16 writes of transmission data of the 2nd group of transmission circuit select
End C429B_PL2, the data of the 2nd group of transmission circuit send state end C429B_TX/R, the data of the 2nd group of transmission circuit send and enable
End C429B_ENTX, the chip configuration Enable Pin C429B_CWSTR correspondence of the 2nd group of transmission circuit connect, and the 3rd group of ARINC429 is total
Line transceiving chip circuitSEL、 TX/R、ENTX、Hold the 3rd group of transmitting-receiving by electrical level matching circuit with the described register circuit (3) realized by CPLD chip programming
The data sink 1 of circuit receives interruptive port C429C_RDY1, the data sink 2 of the 3rd group of transmission circuit receives interruptive port
C429C_RDY2, high/low 16 of the reception data of the 3rd group of transmission circuit read selection end C429C_SEL, the 3rd group of transmission circuit
Data sink 1 Enable Pin C429C_EN1, data sink 2 Enable Pin C429C_EN2 of the 3rd group of transmission circuit, the 3rd group
Low 16 writes of transmission data of transmission circuit select end C429C_PL1, high 16 writes of transmission data of the 3rd group of transmission circuit
Select end C429C_PL2, the data of the 3rd group of transmission circuit send state end C429C_TX/R, the data of the 3rd group of transmission circuit are sent out
Send Enable Pin C429C_ENTX, the chip configuration Enable Pin C429C_CWSTR correspondence of the 3rd group of transmission circuit connects, the 4th group
ARINC429 bus transceiving chip circuitSEL、 TX/R、
ENTX、End is by electrical level matching circuit and the 4th of the described register circuit (3) realized by CPLD chip programming
The data sink 1 of group transmission circuit receives interruptive port C429D_RDY1, the data sink 2 of the 4th group of transmission circuit receives
Interruptive port C429D_RDY2, the 4th group of transmission circuit reception data high/low 16 read select end C429D_SEL, the 4th group
Data sink 1 Enable Pin C429D_EN1 of transmission circuit, data sink 2 Enable Pin C429D_ of the 4th group of transmission circuit
EN2, low 16 writes of transmission data of the 4th group of transmission circuit select end C429D_PL1, the transmission data of the 4th group of transmission circuit
High 16 writes select end C429D_PL2, the data of the 4th group of transmission circuit send state end C429D_TX/R, the 4th group of transmitting-receiving electricity
The data on road send Enable Pin C429D_ENTX, the chip configuration Enable Pin C429D_CWSTR correspondence of the 4th group of transmission circuit connects
Connect.
A kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation the most according to claim 1,
It is characterized in that: the chip that described DSP circuit (1) uses is TMS320F28335.
A kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation the most according to claim 1,
It is characterized in that: the chip that the register circuit (3) that CPLD chip programming realizes uses is EPM570.
A kind of multi-channel A RINC429 data transmit-receive circuit structure based on DSP and CPLD exploitation the most according to claim 1,
It is characterized in that: the chip that described ARINC429 bus transceiving chip circuit (2) uses is HS3282 and HS3182.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410113491.0A CN103823785B (en) | 2014-03-25 | 2014-03-25 | Multi-way ARINC429 data transmit-receive circuit structure based on development of DSP and CPLD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410113491.0A CN103823785B (en) | 2014-03-25 | 2014-03-25 | Multi-way ARINC429 data transmit-receive circuit structure based on development of DSP and CPLD |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103823785A CN103823785A (en) | 2014-05-28 |
| CN103823785B true CN103823785B (en) | 2017-01-11 |
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| CN104764453A (en) * | 2015-03-26 | 2015-07-08 | 北京航空航天大学 | Navigation and interface computer based on dual-DSP and CPLD |
| CN107783934B (en) * | 2016-08-30 | 2021-05-28 | 中国飞行试验研究院 | Airborne multi-channel ARINC429 bus real-time acquisition and data filtering method |
| CN106940544B (en) * | 2017-03-14 | 2019-03-26 | 西安电子科技大学 | Airborne-bus communication control method based on DSP and CPLD |
| CN107765677A (en) * | 2017-11-22 | 2018-03-06 | 长沙景嘉微电子股份有限公司 | A kind of 2 road ARINC429 transtation mission circuits share the design method of 1 physical bus |
| CN109445325A (en) * | 2018-10-15 | 2019-03-08 | 四川九洲空管科技有限责任公司 | A kind of high speed ARINC429 data processing method based on FPGA |
| CN112231266B (en) * | 2020-10-15 | 2023-03-24 | 天津津航计算技术研究所 | ARINC429 bus control method based on lookup table |
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